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Sync ixg(4) up to FreeBSD r279805 (or r280181) which include some bugfixes.

Browse Source 
TODO:
 - Merge r280182 and newer. It's required to support X55x.
 - MSI/MSI-X support.
This commit is contained in:
msaitoh 2015-08-05 04:08:44 +00:00
parent 0d97816049
commit 619731ad48
18 changed files with 1612 additions and 769 deletions
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246
sys/dev/pci/ixgbe/README
View File

@ -1,9 +1,8 @@
FreeBSD Driver for 10 Gigabit PCI Express Server Adapters
=============================================
/*$FreeBSD: src/sys/dev/ixgbe/README,v 1.2 2009/04/10 00:22:48 jfv Exp $*/
/*$NetBSD: README,v 1.1 2011/08/12 21:55:28 dyoung Exp $*/
FreeBSD Driver for Intel(R) Ethernet 10 Gigabit PCI Express Server Adapters
============================================================================
/*$FreeBSD: head/sys/dev/ixgbe/README 251964 2013-06-18 21:28:19Z jfv $*/
May 14, 2008
Jun 18, 2013
Contents
@ -12,15 +11,15 @@ Contents
- Overview
- Supported Adapters
- Building and Installation
- Additional Configurations
- Additional Configurations and Tuning
- Known Limitations
Overview
========
This file describes the FreeBSD* driver for the 10 Gigabit PCIE Family of
Adapters. Drivers has been developed for use with FreeBSD 7 or later.
This file describes the FreeBSD* driver for the
Intel(R) Ethernet 10 Gigabit Family of Adapters.
For questions related to hardware requirements, refer to the documentation
supplied with your Intel 10GbE adapter. All hardware requirements listed
@ -30,100 +29,103 @@ apply to use with FreeBSD.
Supported Adapters
==================
The following Intel network adapters are compatible with the drivers in this
release:
The driver in this release is compatible with 82598 and 82599-based Intel
Network Connections.
Controller Adapter Name Physical Layer
---------- ------------ --------------
82598EB Intel(R) 10 Gigabit XF SR/AF 10G Base -LR (850 nm optical fiber)
Dual Port Server Adapter 10G Base -SR (1310 nm optical fiber)
82598EB Intel(R) 10 Gigabit XF SR/LR
Server Adapter
Intel(R) 82598EB 10 Gigabit AF
Network Connection
Intel(R) 82598EB 10 Gigabit AT
CX4 Network Connection
SFP+ Devices with Pluggable Optics
----------------------------------
82599-BASED ADAPTERS
Building and Installation
=========================
NOTE: If your 82599-based Intel(R) Ethernet Network Adapter came with Intel
optics, or is an Intel(R) Ethernet Server Adapter X520-2, then it only supports
Intel optics and/or the direct attach cables listed below.
NOTE: You must have kernel sources installed in order to compile the driver
module.
When 82599-based SFP+ devices are connected back to back, they should be set to
the same Speed setting. Results may vary if you mix speed settings.
In the instructions below, x.x.x is the driver version as indicated in
the name of the driver tar.
Supplier Type Part Numbers
1. Move the base driver tar file to the directory of your choice. For
example, use /home/username/ixgbe or /usr/local/src/ixgbe.
SR Modules
Intel DUAL RATE 1G/10G SFP+ SR (bailed) FTLX8571D3BCV-IT
Intel DUAL RATE 1G/10G SFP+ SR (bailed) AFBR-703SDZ-IN2
Intel DUAL RATE 1G/10G SFP+ SR (bailed) AFBR-703SDDZ-IN1
LR Modules
Intel DUAL RATE 1G/10G SFP+ LR (bailed) FTLX1471D3BCV-IT
Intel DUAL RATE 1G/10G SFP+ LR (bailed) AFCT-701SDZ-IN2
Intel DUAL RATE 1G/10G SFP+ LR (bailed) AFCT-701SDDZ-IN1
2. Untar/unzip the archive:
tar xfz ixgbe-x.x.x.tar.gz
The following is a list of 3rd party SFP+ modules and direct attach cables that
have received some testing. Not all modules are applicable to all devices.
3. To install man page:
cd ixgbe-x.x.x
gzip -c ixgbe.4 > /usr/share/man/man4/ixgbee.4.gz
Supplier Type Part Numbers
4. To load the driver onto a running system:
cd ixgbe-x.x.x/src
make load
Finisar SFP+ SR bailed, 10g single rate FTLX8571D3BCL
Avago SFP+ SR bailed, 10g single rate AFBR-700SDZ
Finisar SFP+ LR bailed, 10g single rate FTLX8571D3BCV-IT
5. To assign an IP address to the interface, enter the following:
ifconfig ix<interface_num> <IP_address>
Finisar DUAL RATE 1G/10G SFP+ SR (No Bail) FTLX8571D3QCV-IT
Avago DUAL RATE 1G/10G SFP+ SR (No Bail) AFBR-703SDZ-IN1
Finisar DUAL RATE 1G/10G SFP+ LR (No Bail) FTLX1471D3QCV-IT
Avago DUAL RATE 1G/10G SFP+ LR (No Bail) AFCT-701SDZ-IN1
Finistar 1000BASE-T SFP FCLF8522P2BTL
Avago 1000BASE-T SFP ABCU-5710RZ
6. Verify that the interface works. Enter the following, where <IP_address>
is the IP address for another machine on the same subnet as the interface
that is being tested:
ping <IP_address>
NOTE: As of driver version 2.5.13 it is possible to allow the operation
of unsupported modules by setting the static variable 'allow_unsupported_sfp'
to TRUE and rebuilding the driver. If problems occur please assure that they
can be reproduced with fully supported optics first.
7. If you want the driver to load automatically when the system is booted:
82599-based adapters support all passive and active limiting direct attach
cables that comply with SFF-8431 v4.1 and SFF-8472 v10.4 specifications.
cd ixgbe-x.x.x/src
make
make install
Laser turns off for SFP+ when ifconfig down
--------------------------------------------------------
"ifconfig down" turns off the laser for 82599-based SFP+ fiber adapters.
"ifconfig up" turns on the later.
Edit /boot/loader.conf, and add the following line:
ixgbe_load="YES"
82598-BASED ADAPTERS
OR
NOTES for 82598-Based Adapters:
- Intel(R) Ethernet Network Adapters that support removable optical modules
only support their original module type (i.e., the Intel(R) 10 Gigabit SR
Dual Port Express Module only supports SR optical modules). If you plug
in a different type of module, the driver will not load.
- Hot Swapping/hot plugging optical modules is not supported.
- Only single speed, 10 gigabit modules are supported.
- LAN on Motherboard (LOMs) may support DA, SR, or LR modules. Other module
types are not supported. Please see your system documentation for details.
compile the driver into the kernel (see item 8).
The following is a list of 3rd party SFP+ modules and direct attach cables that have
received some testing. Not all modules are applicable to all devices.
Supplier Type Part Numbers
Edit /etc/rc.conf, and create the appropriate ifconfig_ixgbe<interface_num>
entry:
Finisar SFP+ SR bailed, 10g single rate FTLX8571D3BCL
Avago SFP+ SR bailed, 10g single rate AFBR-700SDZ
Finisar SFP+ LR bailed, 10g single rate FTLX1471D3BCL
ifconfig_ix<interface_num>="<ifconfig_settings>"
Example usage:
ifconfig_ix0="inet 192.168.10.1 netmask 255.255.255.0"
NOTE: For assistance, see the ifconfig man page.
8. If you want to compile the driver into the kernel, enter:
FreeBSD 7 or later:
cd ixgbe-x.x.x/src
cp *.[ch] /usr/src/sys/dev/ixgbe
cp Makefile.kernel /usr/src/sys/modules/ixgbe/Makefile
Edit the kernel configuration file (i.e., GENERIC or MYKERNEL) in
/usr/src/sys/i386/conf (replace "i386" with the appropriate system
architecture if necessary), and ensure the following line is present:
device ixgbe
Compile and install the kernel. The system must be reboot for the kernel
updates to take affect. For additional information on compiling the kernel,
consult the FreeBSD operating system documentation.
82598-based adapters support all passive direct attach cables that comply
with SFF-8431 v4.1 and SFF-8472 v10.4 specifications. Active direct attach
cables are not supported.
Third party optic modules and cables referred to above are listed only for the
purpose of highlighting third party specifications and potential compatibility,
and are not recommendations or endorsements or sponsorship of any third party's
product by Intel. Intel is not endorsing or promoting products made by any
third party and the third party reference is provided only to share information
regarding certain optic modules and cables with the above specifications. There
may be other manufacturers or suppliers, producing or supplying optic modules
and cables with similar or matching descriptions. Customers must use their own
discretion and diligence to purchase optic modules and cables from any third
party of their choice. Customer are solely responsible for assessing the
suitability of the product and/or devices and for the selection of the vendor
for purchasing any product. INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
SUCH THIRD PARTY PRODUCTS OR SELECTION OF VENDOR BY CUSTOMERS.
Configuration and Tuning
=========================
========================
The driver supports Transmit/Receive Checksum Offload and Jumbo Frames on
all 10 Gigabit adapters.
@ -144,7 +146,7 @@ all 10 Gigabit adapters.
The Jumbo Frames MTU range for Intel Adapters is 1500 to 16114. The default
MTU range is 1500. To modify the setting, enter the following:
ifconfig ix <interface_num> <hostname or IP address> mtu 9000
ifconfig ix<interface_num> <hostname or IP address> mtu 9000
To confirm an interface's MTU value, use the ifconfig command. To confirm
the MTU used between two specific devices, use:
@ -201,6 +203,8 @@ all 10 Gigabit adapters.
TSO
---
TSO is enabled by default.
To disable:
ifconfig <interface_num> -tso
@ -210,58 +214,92 @@ all 10 Gigabit adapters.
ifconfig <interface_num> tso
LRO
___
---
Large Receive Offload is available in version 1.4.4, it is on
by default. It can be toggled off and on by using:
sysctl dev.ix.X.enable_lro=[0,1]
Large Receive Offload is available in the driver; it is on by default.
It can be disabled by using:
ifconfig <interface_num> -lro
To enable:
ifconfig <interface_num> lro
NOTE: when changing this feature you MUST be sure the interface
is reinitialized, it is easy to do this with ifconfig down/up.
The LRO code will ultimately move into the kernel stack code,
but for this first release it was included with the driver.
Important system configuration changes:
---------------------------------------
When there is a choice run on a 64bit OS rather than 32, it makes
a significant difference in improvement.
When there is a choice run on a 64bit OS rather than 32, it makes a
significant difference in improvement.
The default scheduler SCHED_4BSD is not smart about SMP locality issues.
Significant improvement can be achieved by switching to the ULE scheduler.
The interface can generate a high number of interrupts. To avoid running
into the limit set by the kernel, adjust hw.intr_storm_threshold
setting using sysctl:
This is done by changing the entry in the config file from SCHED_4BSD to
SCHED_ULE. Note that this is only advisable on FreeBSD 7, on 6.X there have
been stability problems with ULE.
sysctl hw.intr_storm_threshold=9000 (the default is 1000)
Change the file /etc/sysctl.conf, add the line:
For this change to take effect on boot, edit /etc/sysctl.conf and add the
line:
hw.intr_storm_threshold=9000
hw.intr_storm_threshold: 8000 (the default is 1000)
If you still see Interrupt Storm detected messages, increase the limit to a
higher number, or the detection can be disabled by setting it to 0.
Best throughput results are seen with a large MTU; use 9000 if possible.
The default number of descriptors is 256, increasing this to 1024 or even
2048 may improve performance.
The default number of descriptors is 2048, increasing or descreasing
may improve performance in some workloads, but change carefully.
Known Limitations
=================
For known hardware and troubleshooting issues, refer to the following website.
http://support.intel.com/support/go/network/adapter/home.htm
Either select the link for your adapter or perform a search for the adapter
number. The adapter's page lists many issues. For a complete list of hardware
issues download your adapter's user guide and read the Release Notes.
UDP stress test with 10GbE driver
---------------------------------
Under small packets UDP stress test with 10GbE driver, the FreeBSD system
will drop UDP packets due to the fullness of socket buffers. You may want
to change the driver's Flow Control variables to the minimum value for
controlling packet reception.
Attempting to configure larger MTUs with a large numbers of processors may
generate the error message "ix0:could not setup receive structures"
--------------------------------------------------------------------------
When using the ixgbe driver with RSS autoconfigured based on the number of
cores (the default setting) and that number is larger than 4, increase the
memory resources allocated for the mbuf pool as follows:
Add to the sysctl.conf file for the system:
kern.ipc.nmbclusters=262144
kern.ipc.nmbjumbop=262144
Lower than expected performance on dual port 10GbE devices
----------------------------------------------------------
Some PCI-E x8 slots are actually configured as x4 slots. These slots have
insufficient bandwidth for full 10Gbe line rate with dual port 10GbE devices.
The driver will detect this situation and will write the following message in
the system log: "PCI-Express bandwidth available for this card is not
sufficient for optimal performance. For optimal performance a x8 PCI-Express
slot is required."
If this error occurs, moving your adapter to a true x8 slot will resolve the
issue.
Support
=======
For general information and support, go to the Intel support website at:
http://support.intel.com
www.intel.com/support/
If an issue is identified with the released source code on the supported
kernel with a supported adapter, email the specific information related to
the issue to freebsd@intel.com.
the issue to freebsd@intel.com

822
sys/dev/pci/ixgbe/ixgbe.c
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File diff suppressed because it is too large Load Diff

17
sys/dev/pci/ixgbe/ixgbe.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2001-2012, Intel Corporation
Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -58,8 +58,8 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 244514 2012-12-20 22:26:03Z luigi $*/
/*$NetBSD: ixgbe.h,v 1.7 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 279393 2015-02-28 14:57:57Z ngie $*/
/*$NetBSD: ixgbe.h,v 1.8 2015/08/05 04:08:44 msaitoh Exp $*/
#ifndef _IXGBE_H_
@ -180,8 +180,10 @@
* modern Intel CPUs, results in 40 bytes wasted and a significant drop
* in observed efficiency of the optimization, 97.9% -> 81.8%.
*/
#define IXGBE_RX_COPY_LEN 160
#define IXGBE_RX_COPY_ALIGN (MHLEN - IXGBE_RX_COPY_LEN)
#define MPKTHSIZE (offsetof(struct _mbuf_dummy, m_pktdat))
#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32)
#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED)
#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE)
/* Keep older OS drivers building... */
#if !defined(SYSCTL_ADD_UQUAD)
@ -230,6 +232,7 @@
#define IXGBE_BULK_LATENCY 1200
#define IXGBE_LINK_ITR 2000
/*
*****************************************************************************
* vendor_info_array
@ -357,7 +360,6 @@ struct rx_ring {
#endif /* LRO */
bool lro_enabled;
bool hw_rsc;
bool discard;
bool vtag_strip;
u16 next_to_refresh;
u16 next_to_check;
@ -470,6 +472,7 @@ struct adapter {
/* Multicast array memory */
u8 *mta;
/* Misc stats maintained by the driver */
struct evcnt dropped_pkts;
struct evcnt mbuf_defrag_failed;
@ -496,6 +499,7 @@ struct adapter {
ixgbe_extmem_head_t jcl_head;
};
/* Precision Time Sync (IEEE 1588) defines */
#define ETHERTYPE_IEEE1588 0x88F7
#define PICOSECS_PER_TICK 20833
@ -518,7 +522,6 @@ struct adapter {
#define IXGBE_CORE_LOCK_ASSERT(_sc) KASSERT(mutex_owned(&(_sc)->core_mtx))
#define IXGBE_TX_LOCK_ASSERT(_sc) KASSERT(mutex_owned(&(_sc)->tx_mtx))
static inline bool
ixgbe_is_sfp(struct ixgbe_hw *hw)
{

22
sys/dev/pci/ixgbe/ixgbe_82598.c
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_82598.c,v 1.4 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_82598.c,v 1.5 2015/08/05 04:08:44 msaitoh Exp $*/
#include "ixgbe_type.h"
#include "ixgbe_82598.h"
@ -167,6 +167,8 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
/* Manageability interface */
mac->ops.set_fw_drv_ver = NULL;
mac->ops.get_rtrup2tc = NULL;
return ret_val;
}
@ -1116,10 +1118,19 @@ static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
u16 sfp_addr = 0;
u16 sfp_data = 0;
u16 sfp_stat = 0;
u16 gssr;
u32 i;
DEBUGFUNC("ixgbe_read_i2c_phy_82598");
if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
gssr = IXGBE_GSSR_PHY1_SM;
else
gssr = IXGBE_GSSR_PHY0_SM;
if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
return IXGBE_ERR_SWFW_SYNC;
if (hw->phy.type == ixgbe_phy_nl) {
/*
* NetLogic phy SDA/SCL registers are at addresses 0xC30A to
@ -1128,14 +1139,14 @@ static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
*/
sfp_addr = (dev_addr << 8) + byte_offset;
sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
hw->phy.ops.write_reg(hw,
hw->phy.ops.write_reg_mdi(hw,
IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
IXGBE_MDIO_PMA_PMD_DEV_TYPE,
sfp_addr);
/* Poll status */
for (i = 0; i < 100; i++) {
hw->phy.ops.read_reg(hw,
hw->phy.ops.read_reg_mdi(hw,
IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
IXGBE_MDIO_PMA_PMD_DEV_TYPE,
&sfp_stat);
@ -1152,7 +1163,7 @@ static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
}
/* Read data */
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
*eeprom_data = (u8)(sfp_data >> 8);
@ -1161,6 +1172,7 @@ static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
}
out:
hw->mac.ops.release_swfw_sync(hw, gssr);
return status;
}

108
sys/dev/pci/ixgbe/ixgbe_82599.c
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82599.c 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_82599.c,v 1.9 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82599.c 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_82599.c,v 1.10 2015/08/05 04:08:44 msaitoh Exp $*/
#include "ixgbe_type.h"
#include "ixgbe_82599.h"
@ -78,7 +78,7 @@ void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
* and MNG not enabled
*/
if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
!(ixgbe_mng_enabled(hw))) {
!hw->mng_fw_enabled) {
mac->ops.disable_tx_laser =
&ixgbe_disable_tx_laser_multispeed_fiber;
mac->ops.enable_tx_laser =
@ -181,11 +181,13 @@ s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
goto setup_sfp_out;
}
hw->eeprom.ops.read(hw, ++data_offset, &data_value);
if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
goto setup_sfp_err;
while (data_value != 0xffff) {
IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
IXGBE_WRITE_FLUSH(hw);
hw->eeprom.ops.read(hw, ++data_offset, &data_value);
if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
goto setup_sfp_err;
}
/* Release the semaphore */
@ -230,6 +232,15 @@ s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
setup_sfp_out:
return ret_val;
setup_sfp_err:
/* Release the semaphore */
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
/* Delay obtaining semaphore again to allow FW access */
msec_delay(hw->eeprom.semaphore_delay);
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed", data_offset);
return IXGBE_ERR_PHY;
}
/**
@ -315,6 +326,11 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
/* Cache if MNG FW is up */
hw->mng_fw_enabled = ixgbe_mng_enabled(hw);
return ret_val;
}
@ -479,6 +495,29 @@ out:
return media_type;
}
/**
* ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
* @hw: pointer to hardware structure
*
* Disables link during D3 power down sequence.
*
**/
void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
{
u32 autoc2_reg;
u16 ee_ctrl_2 = 0;
DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
if (!hw->mng_fw_enabled && !hw->wol_enabled &&
ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
}
}
/**
* ixgbe_start_mac_link_82599 - Setup MAC link settings
* @hw: pointer to hardware structure
@ -1123,7 +1162,8 @@ s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
{
ixgbe_link_speed link_speed;
s32 status;
u32 ctrl, i, autoc, autoc2;
u32 ctrl, i, autoc2;
u32 curr_lms;
bool link_up = FALSE;
DEBUGFUNC("ixgbe_reset_hw_82599");
@ -1157,6 +1197,13 @@ s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
hw->phy.ops.reset(hw);
/* remember AUTOC from before we reset */
if (hw->mac.cached_autoc)
curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK;
else
curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) &
IXGBE_AUTOC_LMS_MASK;
mac_reset_top:
/*
* Issue global reset to the MAC. Needs to be SW reset if link is up.
@ -1205,7 +1252,7 @@ mac_reset_top:
* stored off yet. Otherwise restore the stored original
* values since the reset operation sets back to defaults.
*/
autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
/* Enable link if disabled in NVM */
@ -1216,12 +1263,24 @@ mac_reset_top:
}
if (hw->mac.orig_link_settings_stored == FALSE) {
hw->mac.orig_autoc = autoc;
hw->mac.orig_autoc = hw->mac.cached_autoc;
hw->mac.orig_autoc2 = autoc2;
hw->mac.cached_autoc = autoc;
hw->mac.orig_link_settings_stored = TRUE;
} else {
if (autoc != hw->mac.orig_autoc) {
/* If MNG FW is running on a multi-speed device that
* doesn't autoneg with out driver support we need to
* leave LMS in the state it was before we MAC reset.
* Likewise if we support WoL we don't want change the
* LMS state.
*/
if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
hw->wol_enabled)
hw->mac.orig_autoc =
(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
curr_lms;
if (hw->mac.cached_autoc != hw->mac.orig_autoc) {
/* Need SW/FW semaphore around AUTOC writes if LESM is
* on, likewise reset_pipeline requires us to hold
* this lock as it also writes to AUTOC.
@ -2276,11 +2335,11 @@ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
* Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
* if the FW version is not supported.
**/
s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_EEPROM_VERSION;
u16 fw_offset, fw_ptp_cfg_offset;
u16 fw_version = 0;
u16 fw_version;
DEBUGFUNC("ixgbe_verify_fw_version_82599");
@ -2291,22 +2350,37 @@ s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
}
/* get the offset to the Firmware Module block */
hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed", IXGBE_FW_PTR);
return IXGBE_ERR_EEPROM_VERSION;
}
if ((fw_offset == 0) || (fw_offset == 0xFFFF))
goto fw_version_out;
/* get the offset to the Pass Through Patch Configuration block */
hw->eeprom.ops.read(hw, (fw_offset +
if (hw->eeprom.ops.read(hw, (fw_offset +
IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
&fw_ptp_cfg_offset);
&fw_ptp_cfg_offset)) {
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed",
fw_offset +
IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
return IXGBE_ERR_EEPROM_VERSION;
}
if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
goto fw_version_out;
/* get the firmware version */
hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
IXGBE_FW_PATCH_VERSION_4), &fw_version);
if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed",
fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
return IXGBE_ERR_EEPROM_VERSION;
}
if (fw_version > 0x5)
status = IXGBE_SUCCESS;

28
sys/dev/pci/ixgbe/ixgbe_api.c
View File

@ -30,12 +30,25 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.c 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_api.c,v 1.7 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.c 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_api.c,v 1.8 2015/08/05 04:08:44 msaitoh Exp $*/
#include "ixgbe_api.h"
#include "ixgbe_common.h"
/**
* ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
* @hw: pointer to hardware structure
* @map: pointer to u8 arr for returning map
*
* Read the rtrup2tc HW register and resolve its content into map
**/
void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
{
if (hw->mac.ops.get_rtrup2tc)
hw->mac.ops.get_rtrup2tc(hw, map);
}
/**
* ixgbe_init_shared_code - Initialize the shared code
* @hw: pointer to hardware structure
@ -94,6 +107,12 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_set_mac_type\n");
if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) {
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
"Unsupported vendor id: %x", hw->vendor_id);
return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
}
switch (hw->device_id) {
case IXGBE_DEV_ID_82598:
case IXGBE_DEV_ID_82598_BX:
@ -140,6 +159,9 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
break;
default:
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
"Unsupported device id: %x",
hw->device_id);
break;
}
@ -996,6 +1018,8 @@ s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
}
/**
* ixgbe_read_analog_reg8 - Reads 8 bit analog register
* @hw: pointer to hardware structure

6
sys/dev/pci/ixgbe/ixgbe_api.h
View File

@ -30,14 +30,15 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.h 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_api.h,v 1.4 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.h 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_api.h,v 1.5 2015/08/05 04:08:44 msaitoh Exp $*/
#ifndef _IXGBE_API_H_
#define _IXGBE_API_H_
#include "ixgbe_type.h"
void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map);
s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
@ -135,6 +136,7 @@ u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);
s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);

356
sys/dev/pci/ixgbe/ixgbe_common.c
View File

@ -30,11 +30,13 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 238149 2012-07-05 20:51:44Z jfv $*/
/*$NetBSD: ixgbe_common.c,v 1.5 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_common.c,v 1.6 2015/08/05 04:08:44 msaitoh Exp $*/
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
#include "ixgbe_dcb.h"
#include "ixgbe_dcb_82599.h"
#include "ixgbe_api.h"
static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
@ -135,31 +137,63 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
mac->ops.get_link_capabilities = NULL;
mac->ops.setup_link = NULL;
mac->ops.check_link = NULL;
mac->ops.dmac_config = NULL;
mac->ops.dmac_update_tcs = NULL;
mac->ops.dmac_config_tcs = NULL;
return IXGBE_SUCCESS;
}
/**
* ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
* control
* ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
* of flow control
* @hw: pointer to hardware structure
*
* There are several phys that do not support autoneg flow control. This
* function check the device id to see if the associated phy supports
* autoneg flow control.
* This function returns TRUE if the device supports flow control
* autonegotiation, and FALSE if it does not.
*
**/
s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
{
bool supported = FALSE;
ixgbe_link_speed speed;
bool link_up;
DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
switch (hw->phy.media_type) {
case ixgbe_media_type_fiber_fixed:
case ixgbe_media_type_fiber:
hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
/* if link is down, assume supported */
if (link_up)
supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
TRUE : FALSE;
else
supported = TRUE;
break;
case ixgbe_media_type_backplane:
supported = TRUE;
break;
case ixgbe_media_type_copper:
/* only some copper devices support flow control autoneg */
switch (hw->device_id) {
case IXGBE_DEV_ID_82599_T3_LOM:
case IXGBE_DEV_ID_X540T:
return IXGBE_SUCCESS;
case IXGBE_DEV_ID_X540_BYPASS:
supported = TRUE;
break;
default:
return IXGBE_ERR_FC_NOT_SUPPORTED;
supported = FALSE;
}
default:
break;
}
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
"Device %x does not support flow control autoneg",
hw->device_id);
return supported;
}
/**
@ -182,7 +216,8 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
* ixgbe_fc_rx_pause because it will cause us to fail at UNH.
*/
if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
"ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
goto out;
}
@ -269,7 +304,8 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
"Flow control param set incorrectly\n");
ret_val = IXGBE_ERR_CONFIG;
goto out;
break;
@ -321,7 +357,7 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
hw->mac.ops.release_swfw_sync(hw,
IXGBE_GSSR_MAC_CSR_SM);
} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
(ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
(ixgbe_device_supports_autoneg_fc(hw))) {
hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
}
@ -920,23 +956,18 @@ s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
}
/**
* ixgbe_get_bus_info_generic - Generic set PCI bus info
* ixgbe_set_pci_config_data_generic - Generic store PCI bus info
* @hw: pointer to hardware structure
* @link_status: the link status returned by the PCI config space
*
* Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
* Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
**/
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
{
struct ixgbe_mac_info *mac = &hw->mac;
u16 link_status;
DEBUGFUNC("ixgbe_get_bus_info_generic");
hw->bus.type = ixgbe_bus_type_pci_express;
/* Get the negotiated link width and speed from PCI config space */
link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
switch (link_status & IXGBE_PCI_LINK_WIDTH) {
case IXGBE_PCI_LINK_WIDTH_1:
hw->bus.width = ixgbe_bus_width_pcie_x1;
@ -971,6 +1002,25 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
}
mac->ops.set_lan_id(hw);
}
/**
* ixgbe_get_bus_info_generic - Generic set PCI bus info
* @hw: pointer to hardware structure
*
* Gets the PCI bus info (speed, width, type) then calls helper function to
* store this data within the ixgbe_hw structure.
**/
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
{
u16 link_status;
DEBUGFUNC("ixgbe_get_bus_info_generic");
/* Get the negotiated link width and speed from PCI config space */
link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
ixgbe_set_pci_config_data_generic(hw, link_status);
return IXGBE_SUCCESS;
}
@ -1470,11 +1520,13 @@ s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
if (words == 0) {
status = IXGBE_ERR_INVALID_ARGUMENT;
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
goto out;
}
if (offset >= hw->eeprom.word_size) {
status = IXGBE_ERR_EEPROM;
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
goto out;
}
@ -1576,11 +1628,13 @@ s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
if (words == 0) {
status = IXGBE_ERR_INVALID_ARGUMENT;
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
goto out;
}
if (offset >= hw->eeprom.word_size) {
status = IXGBE_ERR_EEPROM;
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
goto out;
}
@ -1649,6 +1703,11 @@ s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
}
usec_delay(5);
}
if (i == IXGBE_EERD_EEWR_ATTEMPTS)
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"EEPROM read/write done polling timed out");
return status;
}
@ -1784,13 +1843,14 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
* was not granted because we don't have access to the EEPROM
*/
if (i >= timeout) {
DEBUGOUT("SWESMBI Software EEPROM semaphore "
"not granted.\n");
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"SWESMBI Software EEPROM semaphore not granted.\n");
ixgbe_release_eeprom_semaphore(hw);
status = IXGBE_ERR_EEPROM;
}
} else {
DEBUGOUT("Software semaphore SMBI between device drivers "
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"Software semaphore SMBI between device drivers "
"not granted.\n");
}
@ -2215,7 +2275,8 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
/* Make sure we are using a valid rar index range */
if (index >= rar_entries) {
DEBUGOUT1("RAR index %d is out of range.\n", index);
ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
"RAR index %d is out of range.\n", index);
return IXGBE_ERR_INVALID_ARGUMENT;
}
@ -2264,7 +2325,8 @@ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
/* Make sure we are using a valid rar index range */
if (index >= rar_entries) {
DEBUGOUT1("RAR index %d is out of range.\n", index);
ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
"RAR index %d is out of range.\n", index);
return IXGBE_ERR_INVALID_ARGUMENT;
}
@ -2707,7 +2769,8 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
"Flow control param set incorrectly\n");
ret_val = IXGBE_ERR_CONFIG;
goto out;
break;
@ -2768,8 +2831,13 @@ out:
static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
{
if ((!(adv_reg)) || (!(lp_reg)))
if ((!(adv_reg)) || (!(lp_reg))) {
ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
"Local or link partner's advertised flow control "
"settings are NULL. Local: %x, link partner: %x\n",
adv_reg, lp_reg);
return IXGBE_ERR_FC_NOT_NEGOTIATED;
}
if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
/*
@ -2820,8 +2888,11 @@ static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
(!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
(!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"Auto-Negotiation did not complete or timed out");
goto out;
}
pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
@ -2853,14 +2924,20 @@ static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
* - we are 82599 and link partner is not AN enabled
*/
links = IXGBE_READ_REG(hw, IXGBE_LINKS);
if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"Auto-Negotiation did not complete");
goto out;
}
if (hw->mac.type == ixgbe_mac_82599EB) {
links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
"Link partner is not AN enabled");
goto out;
}
}
/*
* Read the 10g AN autoc and LP ability registers and resolve
* local flow control settings accordingly
@ -2921,12 +2998,17 @@ void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
* - FC autoneg is disabled, or if
* - link is not up.
*/
if (hw->fc.disable_fc_autoneg)
if (hw->fc.disable_fc_autoneg) {
ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
"Flow control autoneg is disabled");
goto out;
}
hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
if (!link_up)
if (!link_up) {
ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
goto out;
}
switch (hw->phy.media_type) {
/* Autoneg flow control on fiber adapters */
@ -2943,7 +3025,7 @@ void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
/* Autoneg flow control on copper adapters */
case ixgbe_media_type_copper:
if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
if (ixgbe_device_supports_autoneg_fc(hw))
ret_val = ixgbe_fc_autoneg_copper(hw);
break;
@ -2960,6 +3042,53 @@ out:
}
}
/*
* ixgbe_pcie_timeout_poll - Return number of times to poll for completion
* @hw: pointer to hardware structure
*
* System-wide timeout range is encoded in PCIe Device Control2 register.
*
* Add 10% to specified maximum and return the number of times to poll for
* completion timeout, in units of 100 microsec. Never return less than
* 800 = 80 millisec.
*/
static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
{
s16 devctl2;
u32 pollcnt;
devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
switch (devctl2) {
case IXGBE_PCIDEVCTRL2_65_130ms:
pollcnt = 1300; /* 130 millisec */
break;
case IXGBE_PCIDEVCTRL2_260_520ms:
pollcnt = 5200; /* 520 millisec */
break;
case IXGBE_PCIDEVCTRL2_1_2s:
pollcnt = 20000; /* 2 sec */
break;
case IXGBE_PCIDEVCTRL2_4_8s:
pollcnt = 80000; /* 8 sec */
break;
case IXGBE_PCIDEVCTRL2_17_34s:
pollcnt = 34000; /* 34 sec */
break;
case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
default:
pollcnt = 800; /* 80 millisec minimum */
break;
}
/* add 10% to spec maximum */
return (pollcnt * 11) / 10;
}
/**
* ixgbe_disable_pcie_master - Disable PCI-express master access
* @hw: pointer to hardware structure
@ -2972,14 +3101,14 @@ out:
s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
u32 i;
u32 i, poll;
DEBUGFUNC("ixgbe_disable_pcie_master");
/* Always set this bit to ensure any future transactions are blocked */
IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
/* Exit if master requets are blocked */
/* Exit if master requests are blocked */
if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
goto out;
@ -3005,14 +3134,16 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
* Before proceeding, make sure that the PCIe block does not have
* transactions pending.
*/
for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
poll = ixgbe_pcie_timeout_poll(hw);
for (i = 0; i < poll; i++) {
usec_delay(100);
if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
goto out;
}
DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"PCIe transaction pending bit also did not clear.\n");
status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
out:
@ -3029,44 +3160,41 @@ out:
**/
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
{
u32 gssr;
u32 gssr = 0;
u32 swmask = mask;
u32 fwmask = mask << 5;
s32 timeout = 200;
u32 timeout = 200;
u32 i;
DEBUGFUNC("ixgbe_acquire_swfw_sync");
while (timeout) {
for (i = 0; i < timeout; i++) {
/*
* SW EEPROM semaphore bit is used for access to all
* SW_FW_SYNC/GSSR bits (not just EEPROM)
* SW NVM semaphore bit is used for access to all
* SW_FW_SYNC bits (not just NVM)
*/
if (ixgbe_get_eeprom_semaphore(hw))
return IXGBE_ERR_SWFW_SYNC;
gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
if (!(gssr & (fwmask | swmask)))
break;
/*
* Firmware currently using resource (fwmask) or other software
* thread currently using resource (swmask)
*/
ixgbe_release_eeprom_semaphore(hw);
msec_delay(5);
timeout--;
}
if (!timeout) {
DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
return IXGBE_ERR_SWFW_SYNC;
}
if (!(gssr & (fwmask | swmask))) {
gssr |= swmask;
IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
ixgbe_release_eeprom_semaphore(hw);
return IXGBE_SUCCESS;
} else {
/* Resource is currently in use by FW or SW */
ixgbe_release_eeprom_semaphore(hw);
msec_delay(5);
}
}
/* If time expired clear the bits holding the lock and retry */
if (gssr & (fwmask | swmask))
ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
msec_delay(5);
return IXGBE_ERR_SWFW_SYNC;
}
/**
@ -3283,15 +3411,23 @@ out:
static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
u16 *san_mac_offset)
{
s32 ret_val;
DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
/*
* First read the EEPROM pointer to see if the MAC addresses are
* available.
*/
hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
san_mac_offset);
if (ret_val) {
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom at offset %d failed",
IXGBE_SAN_MAC_ADDR_PTR);
}
return IXGBE_SUCCESS;
return ret_val;
}
/**
@ -3308,6 +3444,7 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
{
u16 san_mac_data, san_mac_offset;
u8 i;
s32 ret_val;
DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
@ -3315,18 +3452,9 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
* First read the EEPROM pointer to see if the MAC addresses are
* available. If they're not, no point in calling set_lan_id() here.
*/
ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
/*
* No addresses available in this EEPROM. It's not an
* error though, so just wipe the local address and return.
*/
for (i = 0; i < 6; i++)
san_mac_addr[i] = 0xFF;
ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
goto san_mac_addr_out;
}
/* make sure we know which port we need to program */
hw->mac.ops.set_lan_id(hw);
@ -3334,13 +3462,27 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
(san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
for (i = 0; i < 3; i++) {
hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
&san_mac_data);
if (ret_val) {
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed",
san_mac_offset);
goto san_mac_addr_out;
}
san_mac_addr[i * 2] = (u8)(san_mac_data);
san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
san_mac_offset++;
}
return IXGBE_SUCCESS;
san_mac_addr_out:
/*
* No addresses available in this EEPROM. It's not an
* error though, so just wipe the local address and return.
*/
for (i = 0; i < 6; i++)
san_mac_addr[i] = 0xFF;
return IXGBE_SUCCESS;
}
@ -3353,19 +3495,16 @@ san_mac_addr_out:
**/
s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
{
s32 status = IXGBE_SUCCESS;
s32 ret_val;
u16 san_mac_data, san_mac_offset;
u8 i;
DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
/* Look for SAN mac address pointer. If not defined, return */
ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
status = IXGBE_ERR_NO_SAN_ADDR_PTR;
goto san_mac_addr_out;
}
ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
return IXGBE_ERR_NO_SAN_ADDR_PTR;
/* Make sure we know which port we need to write */
hw->mac.ops.set_lan_id(hw);
@ -3380,8 +3519,7 @@ s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
san_mac_offset++;
}
san_mac_addr_out:
return status;
return IXGBE_SUCCESS;
}
/**
@ -3508,7 +3646,8 @@ s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
/* Make sure we are using a valid rar index range */
if (rar >= rar_entries) {
DEBUGOUT1("RAR index %d is out of range.\n", rar);
ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
"RAR index %d is out of range.\n", rar);
return IXGBE_ERR_INVALID_ARGUMENT;
}
@ -3557,7 +3696,8 @@ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
/* Make sure we are using a valid rar index range */
if (rar >= rar_entries) {
DEBUGOUT1("RAR index %d is out of range.\n", rar);
ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
"RAR index %d is out of range.\n", rar);
return IXGBE_ERR_INVALID_ARGUMENT;
}
@ -3656,7 +3796,8 @@ s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
if (first_empty_slot)
regindex = first_empty_slot;
else {
DEBUGOUT("No space in VLVF.\n");
ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
"No space in VLVF.\n");
regindex = IXGBE_ERR_NO_SPACE;
}
}
@ -3946,8 +4087,9 @@ s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
*wwpn_prefix = 0xFFFF;
/* check if alternative SAN MAC is supported */
hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
&alt_san_mac_blk_offset);
offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
goto wwn_prefix_err;
if ((alt_san_mac_blk_offset == 0) ||
(alt_san_mac_blk_offset == 0xFFFF))
@ -3955,19 +4097,29 @@ s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
/* check capability in alternative san mac address block */
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
hw->eeprom.ops.read(hw, offset, &caps);
if (hw->eeprom.ops.read(hw, offset, &caps))
goto wwn_prefix_err;
if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
goto wwn_prefix_out;
/* get the corresponding prefix for WWNN/WWPN */
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
hw->eeprom.ops.read(hw, offset, wwnn_prefix);
if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed", offset);
}
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
hw->eeprom.ops.read(hw, offset, wwpn_prefix);
if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
goto wwn_prefix_err;
wwn_prefix_out:
return IXGBE_SUCCESS;
wwn_prefix_err:
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed", offset);
return IXGBE_SUCCESS;
}
/**
@ -4413,3 +4565,21 @@ void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
}
/**
* ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
* @hw: pointer to hardware structure
* @map: pointer to u8 arr for returning map
*
* Read the rtrup2tc HW register and resolve its content into map
**/
void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
{
u32 reg, i;
reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
map[i] = IXGBE_RTRUP2TC_UP_MASK &
(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
return;
}

10
sys/dev/pci/ixgbe/ixgbe_common.h
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.h 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_common.h,v 1.4 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.h 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_common.h,v 1.5 2015/08/05 04:08:44 msaitoh Exp $*/
#ifndef _IXGBE_COMMON_H_
#define _IXGBE_COMMON_H_
@ -49,6 +49,8 @@ struct ixgbe_pba {
};
#endif
void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map);
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
@ -67,6 +69,7 @@ s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
u32 eeprom_buf_size, u16 *pba_block_size);
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status);
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
@ -109,7 +112,7 @@ s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw);
s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw);
s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
s32 ixgbe_validate_mac_addr(u8 *mac_addr);
@ -157,5 +160,6 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
extern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
extern void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
#endif /* IXGBE_COMMON */

11
sys/dev/pci/ixgbe/ixgbe_osdep.h
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.h 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_osdep.h,v 1.8 2015/08/05 03:42:11 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.h 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_osdep.h,v 1.9 2015/08/05 04:08:44 msaitoh Exp $*/
#ifndef _IXGBE_OS_H_
#define _IXGBE_OS_H_
@ -71,6 +71,9 @@
#define DEBUGOUT5(S,A,B,C,D,E) printf(S "\n",A,B,C,D,E)
#define DEBUGOUT6(S,A,B,C,D,E,F) printf(S "\n",A,B,C,D,E,F)
#define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G)
#define ERROR_REPORT1(S,A) printf(S "\n",A)
#define ERROR_REPORT2(S,A,B) printf(S "\n",A,B)
#define ERROR_REPORT3(S,A,B,C) printf(S "\n",A,B,C)
#else
#define DEBUGOUT(S) do { } while (/*CONSTCOND*/false)
#define DEBUGOUT1(S,A) do { } while (/*CONSTCOND*/false)
@ -82,6 +85,9 @@
do { } while (/*CONSTCOND*/false)
#define DEBUGOUT7(S,A,B,C,D,E,F,G) \
do { } while (/*CONSTCOND*/false)
#define ERROR_REPORT1(S,A) do { } while (/*CONSTCOND*/false)
#define ERROR_REPORT2(S,A,B) do { } while (/*CONSTCOND*/false)
#define ERROR_REPORT3(S,A,B,C) do { } while (/*CONSTCOND*/false)
#endif
#define FALSE 0
@ -112,6 +118,7 @@
typedef uint8_t u8;
typedef int8_t s8;
typedef uint16_t u16;
typedef int16_t s16;
typedef uint32_t u32;
typedef int32_t s32;
typedef uint64_t u64;

202
sys/dev/pci/ixgbe/ixgbe_phy.c
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_phy.c,v 1.5 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_phy.c,v 1.6 2015/08/05 04:08:44 msaitoh Exp $*/
#include "ixgbe_api.h"
#include "ixgbe_common.h"
@ -68,6 +68,8 @@ s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
phy->ops.reset = &ixgbe_reset_phy_generic;
phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
phy->ops.check_link = NULL;
@ -126,8 +128,11 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
}
}
/* clear value if nothing found */
if (status != IXGBE_SUCCESS)
if (status != IXGBE_SUCCESS) {
hw->phy.addr = 0;
ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
"Could not identify valid PHY address");
}
} else {
status = IXGBE_SUCCESS;
}
@ -266,7 +271,8 @@ s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
status = IXGBE_ERR_RESET_FAILED;
DEBUGOUT("PHY reset polling failed to complete.\n");
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"PHY reset polling failed to complete.\n");
}
out:
@ -274,31 +280,17 @@ out:
}
/**
* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
* ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
* the SWFW lock
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
* @phy_data: Pointer to read data from PHY register
**/
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data)
s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data)
{
u32 command;
u32 i;
u32 data;
s32 status = IXGBE_SUCCESS;
u16 gssr;
u32 i, data, command;
DEBUGFUNC("ixgbe_read_phy_reg_generic");
if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
gssr = IXGBE_GSSR_PHY1_SM;
else
gssr = IXGBE_GSSR_PHY0_SM;
if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
status = IXGBE_ERR_SWFW_SYNC;
if (status == IXGBE_SUCCESS) {
/* Setup and write the address cycle command */
command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
@ -316,17 +308,16 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
usec_delay(10);
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address command did not complete.\n");
status = IXGBE_ERR_PHY;
ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
return IXGBE_ERR_PHY;
}
if (status == IXGBE_SUCCESS) {
/*
* Address cycle complete, setup and write the read
* command
@ -347,15 +338,15 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
usec_delay(10);
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY read command didn't complete\n");
status = IXGBE_ERR_PHY;
} else {
ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
return IXGBE_ERR_PHY;
}
/*
* Read operation is complete. Get the data
* from MSRWD
@ -363,41 +354,54 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
*phy_data = (u16)(data);
}
}
hw->mac.ops.release_swfw_sync(hw, gssr);
}
return status;
return IXGBE_SUCCESS;
}
/**
* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
* using the SWFW lock - this function is needed in most cases
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @device_type: 5 bit device type
* @phy_data: Data to write to the PHY register
* @reg_addr: 32 bit address of PHY register to read
* @phy_data: Pointer to read data from PHY register
**/
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data)
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data)
{
u32 command;
u32 i;
s32 status = IXGBE_SUCCESS;
s32 status;
u16 gssr;
DEBUGFUNC("ixgbe_write_phy_reg_generic");
DEBUGFUNC("ixgbe_read_phy_reg_generic");
if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
gssr = IXGBE_GSSR_PHY1_SM;
else
gssr = IXGBE_GSSR_PHY0_SM;
if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
phy_data);
hw->mac.ops.release_swfw_sync(hw, gssr);
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
return status;
}
/**
* ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
* without SWFW lock
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @device_type: 5 bit device type
* @phy_data: Data to write to the PHY register
**/
s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data)
{
u32 i, command;
if (status == IXGBE_SUCCESS) {
/* Put the data in the MDI single read and write data register*/
IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
@ -418,17 +422,15 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
usec_delay(10);
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address cmd didn't complete\n");
status = IXGBE_ERR_PHY;
ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
return IXGBE_ERR_PHY;
}
if (status == IXGBE_SUCCESS) {
/*
* Address cycle complete, setup and write the write
* command
@ -449,18 +451,45 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
usec_delay(10);
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address cmd didn't complete\n");
status = IXGBE_ERR_PHY;
}
ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
return IXGBE_ERR_PHY;
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
* using SWFW lock- this function is needed in most cases
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @device_type: 5 bit device type
* @phy_data: Data to write to the PHY register
**/
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data)
{
s32 status;
u16 gssr;
DEBUGFUNC("ixgbe_write_phy_reg_generic");
if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
gssr = IXGBE_GSSR_PHY1_SM;
else
gssr = IXGBE_GSSR_PHY0_SM;
if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
phy_data);
hw->mac.ops.release_swfw_sync(hw, gssr);
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
return status;
@ -557,7 +586,8 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
if (time_out == max_time_out) {
status = IXGBE_ERR_LINK_SETUP;
DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"PHY autonegotiation time out");
}
return status;
@ -864,6 +894,8 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
* Read control word from PHY init contents offset
*/
ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
if (ret_val)
goto err_eeprom;
control = (eword & IXGBE_CONTROL_MASK_NL) >>
IXGBE_CONTROL_SHIFT_NL;
edata = eword & IXGBE_DATA_MASK_NL;
@ -876,10 +908,16 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
case IXGBE_DATA_NL:
DEBUGOUT("DATA:\n");
data_offset++;
hw->eeprom.ops.read(hw, data_offset++,
ret_val = hw->eeprom.ops.read(hw, data_offset,
&phy_offset);
if (ret_val)
goto err_eeprom;
data_offset++;
for (i = 0; i < edata; i++) {
hw->eeprom.ops.read(hw, data_offset, &eword);
ret_val = hw->eeprom.ops.read(hw, data_offset,
&eword);
if (ret_val)
goto err_eeprom;
hw->phy.ops.write_reg(hw, phy_offset,
IXGBE_TWINAX_DEV, eword);
DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
@ -911,6 +949,11 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
out:
return ret_val;
err_eeprom:
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed", data_offset);
return IXGBE_ERR_PHY;
}
/**
@ -1175,10 +1218,10 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
ixgbe_get_device_caps(hw, &enforce_sfp);
if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
!((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
(hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
(hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
/* Make sure we're a supported PHY type */
if (hw->phy.type == ixgbe_phy_sfp_intel) {
status = IXGBE_SUCCESS;
@ -1263,7 +1306,12 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
sfp_type = ixgbe_sfp_type_srlr_core1;
/* Read offset to PHY init contents */
hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed",
IXGBE_PHY_INIT_OFFSET_NL);
return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
}
if ((!*list_offset) || (*list_offset == 0xFFFF))
return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
@ -1275,12 +1323,14 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
* Find the matching SFP ID in the EEPROM
* and program the init sequence
*/
hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
goto err_phy;
while (sfp_id != IXGBE_PHY_INIT_END_NL) {
if (sfp_id == sfp_type) {
(*list_offset)++;
hw->eeprom.ops.read(hw, *list_offset, data_offset);
if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
goto err_phy;
if ((!*data_offset) || (*data_offset == 0xFFFF)) {
DEBUGOUT("SFP+ module not supported\n");
return IXGBE_ERR_SFP_NOT_SUPPORTED;
@ -1290,7 +1340,7 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
} else {
(*list_offset) += 2;
if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
return IXGBE_ERR_PHY;
goto err_phy;
}
}
@ -1300,6 +1350,11 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
}
return IXGBE_SUCCESS;
err_phy:
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"eeprom read at offset %d failed", *list_offset);
return IXGBE_ERR_PHY;
}
/**
@ -1665,7 +1720,8 @@ static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
}
if (ack == 1) {
DEBUGOUT("I2C ack was not received.\n");
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"I2C ack was not received.\n");
status = IXGBE_ERR_I2C;
}
@ -1735,7 +1791,8 @@ static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
usec_delay(IXGBE_I2C_T_LOW);
} else {
status = IXGBE_ERR_I2C;
DEBUGOUT1("I2C data was not set to %X\n", data);
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"I2C data was not set to %X\n", data);
}
return status;
@ -1819,7 +1876,9 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
if (data != ixgbe_get_i2c_data(i2cctl)) {
status = IXGBE_ERR_I2C;
DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"Error - I2C data was not set to %X.\n",
data);
}
return status;
@ -1906,6 +1965,7 @@ s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
goto out;
status = IXGBE_ERR_OVERTEMP;
ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
out:
return status;
}

8
sys/dev/pci/ixgbe/ixgbe_phy.h
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_phy.h,v 1.4 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_phy.h,v 1.5 2015/08/05 04:08:44 msaitoh Exp $*/
#ifndef _IXGBE_PHY_H_
#define _IXGBE_PHY_H_
@ -119,6 +119,10 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data);
s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 phy_data);
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data);
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

101
sys/dev/pci/ixgbe/ixgbe_type.h
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_type.h,v 1.10 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_type.h,v 1.11 2015/08/05 04:08:44 msaitoh Exp $*/
#ifndef _IXGBE_TYPE_H_
#define _IXGBE_TYPE_H_
@ -42,9 +42,50 @@
#include <net/if.h>
#include <net/if_ether.h>
/*
* The following is a brief description of the error categories used by the
* ERROR_REPORT* macros.
*
* - IXGBE_ERROR_INVALID_STATE
* This category is for errors which represent a serious failure state that is
* unexpected, and could be potentially harmful to device operation. It should
* not be used for errors relating to issues that can be worked around or
* ignored.
*
* - IXGBE_ERROR_POLLING
* This category is for errors related to polling/timeout issues and should be
* used in any case where the timeout occured, or a failure to obtain a lock, or
* failure to receive data within the time limit.
*
* - IXGBE_ERROR_CAUTION
* This category should be used for reporting issues that may be the cause of
* other errors, such as temperature warnings. It should indicate an event which
* could be serious, but hasn't necessarily caused problems yet.
*
* - IXGBE_ERROR_SOFTWARE
* This category is intended for errors due to software state preventing
* something. The category is not intended for errors due to bad arguments, or
* due to unsupported features. It should be used when a state occurs which
* prevents action but is not a serious issue.
*
* - IXGBE_ERROR_ARGUMENT
* This category is for when a bad or invalid argument is passed. It should be
* used whenever a function is called and error checking has detected the
* argument is wrong or incorrect.
*
* - IXGBE_ERROR_UNSUPPORTED
* This category is for errors which are due to unsupported circumstances or
* configuration issues. It should not be used when the issue is due to an
* invalid argument, but for when something has occurred that is unsupported
* (Ex: Flow control autonegotiation or an unsupported SFP+ module.)
*/
#include "ixgbe_osdep.h"
/* Vendor ID */
#define IXGBE_INTEL_VENDOR_ID 0x8086
/* Device IDs */
#define IXGBE_DEV_ID_82598 0x10B6
#define IXGBE_DEV_ID_82598_BX 0x1508
@ -69,12 +110,15 @@
#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B
#define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976
#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
#define IXGBE_DEV_ID_82599EN_SFP 0x1557
#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
#define IXGBE_DEV_ID_82599_XAUI_LOM PCI_PRODUCT_INTEL_82599_XAUI_LOM
#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
#define IXGBE_DEV_ID_82599_VF 0x10ED
@ -220,12 +264,12 @@
(((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
(0x0D00C + (((_i) - 64) * 0x40))))
#define IXGBE_RDRXCTL 0x02F00
#define IXGBE_RDRXCTL_RSC_PUSH 0x80
/* 8 of these 0x03C00 - 0x03C1C */
#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
#define IXGBE_RXCTRL 0x03000
#define IXGBE_DROPEN 0x03D04
#define IXGBE_RXPBSIZE_SHIFT 10
#define IXGBE_RXPBSIZE_MASK 0x000FFC00
/* Receive Registers */
#define IXGBE_RXCSUM 0x05000
@ -455,6 +499,7 @@
#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
/* Security Control Registers */
#define IXGBE_SECTXCTRL 0x08800
#define IXGBE_SECTXSTAT 0x08804
@ -599,8 +644,6 @@
#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
@ -897,8 +940,6 @@
#define IXGBE_RDPROBE 0x02F20
#define IXGBE_RDMAM 0x02F30
#define IXGBE_RDMAD 0x02F34
#define IXGBE_TDSTATCTL 0x07C20
#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
#define IXGBE_TDHMPN 0x07F08
#define IXGBE_TDHMPN2 0x082FC
#define IXGBE_TXDESCIC 0x082CC
@ -1047,7 +1088,9 @@
#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */
#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
#define IXGBE_RDRXCTL_MVMEN 0x00000020
#define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020
#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
#define IXGBE_RDRXCTL_RSC_PUSH 0x00000080
#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/
@ -1694,6 +1737,7 @@ enum {
#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
#define IXGBE_MACC_FLU 0x00000001
@ -1867,6 +1911,8 @@ enum {
#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */
#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */
#define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */
#define IXGBE_EEPROM_CCD_BIT 2
#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */
@ -1907,6 +1953,18 @@ enum {
#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */
#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */
/* FW header offset */
#define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
#define IXGBE_X540_FW_MODULE_MASK 0x7FFF
/* 4KB multiplier */
#define IXGBE_X540_FW_MODULE_LENGTH 0x1000
/* version word 2 (month & day) */
#define IXGBE_X540_FW_PATCH_VERSION_2 0x5
/* version word 3 (silicon compatibility & year) */
#define IXGBE_X540_FW_PATCH_VERSION_3 0x6
/* version word 4 (major & minor numbers) */
#define IXGBE_X540_FW_PATCH_VERSION_4 0x7
#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */
#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */
#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */
@ -1929,6 +1987,17 @@ enum {
#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf
#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0
#define IXGBE_PCIDEVCTRL2_50_100us 0x1
#define IXGBE_PCIDEVCTRL2_1_2ms 0x2
#define IXGBE_PCIDEVCTRL2_16_32ms 0x5
#define IXGBE_PCIDEVCTRL2_65_130ms 0x6
#define IXGBE_PCIDEVCTRL2_260_520ms 0x9
#define IXGBE_PCIDEVCTRL2_1_2s 0xa
#define IXGBE_PCIDEVCTRL2_4_8s 0xd
#define IXGBE_PCIDEVCTRL2_17_34s 0xe
/* Number of 100 microseconds we wait for PCI Express master disable */
#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
@ -2358,6 +2427,14 @@ enum ixgbe_fdir_pballoc_type {
#define IXGBE_FDIR_DROP_QUEUE 127
#define IXGBE_STATUS_OVERHEATING_BIT 20 /* STATUS overtemp bit num */
/* iTS sensor related defines*/
#define IXGBE_TEMP_STATUS_ADDR_X540 0xC830
#define IXGBE_TEMP_VALUE_ADDR_X540 0xC820
#define IXGBE_TEMP_PROV_2_ADDR_X540 0xC421
#define IXGBE_TEMP_PROV_4_ADDR_X540 0xC423
#define IXGBE_TEMP_STATUS_PAGE_X540 0x1E
#define IXGBE_TEMP_HIGH_FAILURE_BIT_X540 0xE
#define IXGBE_TEMP_HIGH_WARNING_BIT_X540 0xC
/* Manageablility Host Interface defines */
#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
@ -3050,6 +3127,10 @@ struct ixgbe_mac_operations {
/* Manageability interface */
s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
s32 (*dmac_config)(struct ixgbe_hw *hw);
s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);
};
struct ixgbe_phy_operations {
@ -3059,6 +3140,8 @@ struct ixgbe_phy_operations {
s32 (*reset)(struct ixgbe_hw *);
s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
s32 (*setup_link)(struct ixgbe_hw *);
s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
@ -3180,6 +3263,8 @@ struct ixgbe_hw {
int api_version;
bool force_full_reset;
bool allow_unsupported_sfp;
bool mng_fw_enabled;
bool wol_enabled;
};
#define ixgbe_call_func(hw, func, params, error) \
@ -3222,7 +3307,7 @@ struct ixgbe_hw {
#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
#define IXGBE_ERR_OUT_OF_MEM -34
#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36
#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
#endif /* _IXGBE_TYPE_H_ */

29
sys/dev/pci/ixgbe/ixgbe_vf.c
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_vf.c 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixgbe_vf.c,v 1.4 2015/04/24 07:00:51 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_vf.c 251964 2013-06-18 21:28:19Z jfv $*/
/*$NetBSD: ixgbe_vf.c,v 1.5 2015/08/05 04:08:44 msaitoh Exp $*/
#include "ixgbe_api.h"
@ -158,7 +158,9 @@ s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)
usec_delay(5);
}
if (timeout) {
if (!timeout)
return IXGBE_ERR_RESET_FAILED;
/* mailbox timeout can now become active */
mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;
@ -174,18 +176,15 @@ s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)
*/
ret_val = mbx->ops.read_posted(hw, msgbuf,
IXGBE_VF_PERMADDR_MSG_LEN, 0);
if (!ret_val) {
if (msgbuf[0] == (IXGBE_VF_RESET |
IXGBE_VT_MSGTYPE_ACK)) {
memcpy(hw->mac.perm_addr, addr,
IXGBE_ETH_LENGTH_OF_ADDRESS);
hw->mac.mc_filter_type =
msgbuf[IXGBE_VF_MC_TYPE_WORD];
} else {
ret_val = IXGBE_ERR_INVALID_MAC_ADDR;
}
}
}
if (ret_val)
return ret_val;
if (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK) &&
msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_NACK))
return IXGBE_ERR_INVALID_MAC_ADDR;
memcpy(hw->mac.perm_addr, addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
hw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD];
return ret_val;
}

89
sys/dev/pci/ixgbe/ixgbe_x540.c
View File

@ -30,7 +30,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 247822 2013-03-04 23:07:40Z jfv $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 251964 2013-06-18 21:28:19Z jfv $*/
#include "ixgbe_x540.h"
#include "ixgbe_type.h"
@ -38,7 +38,6 @@
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
@ -142,6 +141,8 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
/* Manageability interface */
mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
return ret_val;
}
@ -226,7 +227,8 @@ mac_reset_top:
if (ctrl & IXGBE_CTRL_RST_MASK) {
status = IXGBE_ERR_RESET_FAILED;
DEBUGOUT("Reset polling failed to complete.\n");
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"Reset polling failed to complete.\n");
}
msec_delay(100);
@ -372,12 +374,13 @@ s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
DEBUGFUNC("ixgbe_read_eerd_X540");
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
IXGBE_SUCCESS)
IXGBE_SUCCESS) {
status = ixgbe_read_eerd_generic(hw, offset, data);
else
status = IXGBE_ERR_SWFW_SYNC;
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
return status;
}
@ -397,13 +400,14 @@ s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
IXGBE_SUCCESS)
IXGBE_SUCCESS) {
status = ixgbe_read_eerd_buffer_generic(hw, offset,
words, data);
else
status = IXGBE_ERR_SWFW_SYNC;
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
return status;
}
@ -421,12 +425,13 @@ s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
DEBUGFUNC("ixgbe_write_eewr_X540");
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
IXGBE_SUCCESS)
IXGBE_SUCCESS) {
status = ixgbe_write_eewr_generic(hw, offset, data);
else
status = IXGBE_ERR_SWFW_SYNC;
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
return status;
}
@ -446,13 +451,14 @@ s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
IXGBE_SUCCESS)
IXGBE_SUCCESS) {
status = ixgbe_write_eewr_buffer_generic(hw, offset,
words, data);
else
status = IXGBE_ERR_SWFW_SYNC;
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
return status;
}
@ -578,17 +584,20 @@ s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
* Verify read checksum from EEPROM is the same as
* calculated checksum
*/
if (read_checksum != checksum)
if (read_checksum != checksum) {
status = IXGBE_ERR_EEPROM_CHECKSUM;
ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
"Invalid EEPROM checksum");
}
/* If the user cares, return the calculated checksum */
if (checksum_val)
*checksum_val = checksum;
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
out:
return status;
}
@ -631,12 +640,11 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
if (status == IXGBE_SUCCESS)
status = ixgbe_update_flash_X540(hw);
else
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
} else {
status = IXGBE_ERR_SWFW_SYNC;
}
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
return status;
}
@ -647,7 +655,7 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
* Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
* EEPROM from shadow RAM to the flash device.
**/
static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
{
u32 flup;
s32 status = IXGBE_ERR_EEPROM;
@ -669,7 +677,7 @@ static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
else
DEBUGOUT("Flash update time out\n");
if (hw->revision_id == 0) {
if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
flup = IXGBE_READ_REG(hw, IXGBE_EEC);
if (flup & IXGBE_EEC_SEC1VAL) {
@ -710,6 +718,11 @@ static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
}
usec_delay(5);
}
if (i == IXGBE_FLUDONE_ATTEMPTS)
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"Flash update status polling timed out");
return status;
}
@ -755,7 +768,6 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
swfw_sync |= swmask;
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
ixgbe_release_swfw_sync_semaphore(hw);
msec_delay(5);
goto out;
} else {
/*
@ -771,11 +783,13 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
/* Failed to get SW only semaphore */
if (swmask == IXGBE_GSSR_SW_MNG_SM) {
ret_val = IXGBE_ERR_SWFW_SYNC;
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"Failed to get SW only semaphore");
goto out;
}
/* If the resource is not released by the FW/HW the SW can assume that
* the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
* the FW/HW malfunctions. In that case the SW should set the SW bit(s)
* of the requested resource(s) while ignoring the corresponding FW/HW
* bits in the SW_FW_SYNC register.
*/
@ -791,6 +805,17 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
ixgbe_release_swfw_sync_semaphore(hw);
msec_delay(5);
}
/* If the resource is not released by other SW the SW can assume that
* the other SW malfunctions. In that case the SW should clear all SW
* flags that it does not own and then repeat the whole process once
* again.
*/
else if (swfw_sync & swmask) {
ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM |
IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM |
IXGBE_GSSR_MAC_CSR_SM);
ret_val = IXGBE_ERR_SWFW_SYNC;
}
out:
return ret_val;
@ -818,7 +843,6 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
ixgbe_release_swfw_sync_semaphore(hw);
msec_delay(5);
}
/**
@ -865,13 +889,14 @@ static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
* was not granted because we don't have access to the EEPROM
*/
if (i >= timeout) {
DEBUGOUT("REGSMP Software NVM semaphore not "
"granted.\n");
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"REGSMP Software NVM semaphore not granted.\n");
ixgbe_release_swfw_sync_semaphore(hw);
status = IXGBE_ERR_EEPROM;
}
} else {
DEBUGOUT("Software semaphore SMBI between device drivers "
ERROR_REPORT1(IXGBE_ERROR_POLLING,
"Software semaphore SMBI between device drivers "
"not granted.\n");
}

4
sys/dev/pci/ixgbe/ixgbe_x540.h
View File

@ -30,7 +30,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.h 247822 2013-03-04 23:07:40Z jfv $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.h 251964 2013-06-18 21:28:19Z jfv $*/
#ifndef _IXGBE_X540_H_
#define _IXGBE_X540_H_
@ -56,6 +56,7 @@ s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,
s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
@ -63,3 +64,4 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);
#endif /* _IXGBE_X540_H_ */

42
sys/dev/pci/ixgbe/ixv.c
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: head/sys/dev/ixgbe/ixv.c 247822 2013-03-04 23:07:40Z jfv $*/
/*$NetBSD: ixv.c,v 1.9 2015/05/21 00:45:27 rtr Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixv.c 275358 2014-12-01 11:45:24Z hselasky $*/
/*$NetBSD: ixv.c,v 1.10 2015/08/05 04:08:44 msaitoh Exp $*/
#include "opt_inet.h"
#include "opt_inet6.h"
@ -401,7 +401,7 @@ ixv_attach(device_t parent, device_t dev, void *aux)
adapter->num_tx_desc = ixv_txd;
if (((ixv_rxd * sizeof(union ixgbe_adv_rx_desc)) % DBA_ALIGN) != 0 ||
ixv_rxd < MIN_TXD || ixv_rxd > MAX_TXD) {
ixv_rxd < MIN_RXD || ixv_rxd > MAX_RXD) {
aprint_error_dev(dev, "RXD config issue, using default!\n");
adapter->num_rx_desc = DEFAULT_RXD;
} else
@ -1630,12 +1630,9 @@ ixv_identify_hardware(struct adapter *adapter)
** KVM it may not be and will break things.
*/
pci_cmd_word = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
if (!((pci_cmd_word & PCI_COMMAND_MASTER_ENABLE) &&
(pci_cmd_word & PCI_COMMAND_MEM_ENABLE))) {
INIT_DEBUGOUT("Memory Access and/or Bus Master "
"bits were not set!\n");
pci_cmd_word |=
(PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE);
if (!(pci_cmd_word & PCI_COMMAND_MASTER_ENABLE)) {
INIT_DEBUGOUT("Bus Master bit was not set!\n");
pci_cmd_word |= PCI_COMMAND_MASTER_ENABLE;
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_cmd_word);
}
@ -1741,7 +1738,7 @@ ixv_allocate_msix(struct adapter *adapter)
*/
if (adapter->hw.mac.type == ixgbe_mac_82599_vf) {
int msix_ctrl;
pci_get_capability(pc, tag, PCI_CAP_MSIX, &rid);
pci_get_capability(pc, tag, PCI_CAP_MSIX, &rid, NULL);
rid += PCI_MSIX_CTL;
msix_ctrl = pci_read_config(pc, tag, rid);
msix_ctrl |= PCI_MSIX_CTL_ENABLE;
@ -1763,37 +1760,37 @@ ixv_setup_msix(struct adapter *adapter)
return 0;
#else
device_t dev = adapter->dev;
int rid, vectors, want = 2;
int rid, want;
/* First try MSI/X */
rid = PCIR_BAR(3);
adapter->msix_mem = bus_alloc_resource_any(dev,
SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (!adapter->msix_mem) {
if (adapter->msix_mem == NULL) {
device_printf(adapter->dev,
"Unable to map MSIX table \n");
goto out;
}
vectors = pci_msix_count(dev);
if (vectors < 2) {
bus_release_resource(dev, SYS_RES_MEMORY,
rid, adapter->msix_mem);
adapter->msix_mem = NULL;
goto out;
}
/*
** Want two vectors: one for a queue,
** plus an additional for mailbox.
*/
if (pci_alloc_msix(dev, &want) == 0) {
want = 2;
if ((pci_alloc_msix(dev, &want) == 0) && (want == 2)) {
device_printf(adapter->dev,
"Using MSIX interrupts with %d vectors\n", want);
return (want);
}
/* Release in case alloc was insufficient */
pci_release_msi(dev);
out:
if (adapter->msix_mem != NULL) {
bus_release_resource(dev, SYS_RES_MEMORY,
rid, adapter->msix_mem);
adapter->msix_mem = NULL;
}
device_printf(adapter->dev,"MSIX config error\n");
return (ENXIO);
#endif
@ -2080,7 +2077,6 @@ fail_2:
fail_1:
ixgbe_dma_tag_destroy(dma->dma_tag);
fail_0:
dma->dma_map = NULL;
dma->dma_tag = NULL;
return (r);
}
@ -3697,7 +3693,7 @@ ixv_rx_checksum(u32 staterr, struct mbuf * mp, u32 ptype,
}
if (status & IXGBE_RXD_STAT_L4CS) {
stats->l4cs.ev_count++;
u16 type = M_CSUM_TCPv4|M_CSUM_TCPv6|M_CSUM_UDPv4|M_CSUM_UDPv6;
int type = M_CSUM_TCPv4|M_CSUM_TCPv6|M_CSUM_UDPv4|M_CSUM_UDPv6;
if (!(errors & IXGBE_RXD_ERR_TCPE)) {
mp->m_pkthdr.csum_flags |= type;
} else {

6
sys/dev/pci/ixgbe/ixv.h
View File

@ -30,8 +30,8 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD: src/sys/dev/ixgbe/ixv.h,v 1.3 2011/01/07 23:39:41 jfv Exp $*/
/*$NetBSD: ixv.h,v 1.5 2015/04/02 09:26:55 msaitoh Exp $*/
/*$FreeBSD: head/sys/dev/ixgbe/ixv.h 257176 2013-10-26 17:58:36Z glebius $*/
/*$NetBSD: ixv.h,v 1.6 2015/08/05 04:08:44 msaitoh Exp $*/
#ifndef _IXV_H_
@ -46,7 +46,9 @@
#include <sys/socket.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/sockio.h>
#include <net/if.h>