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fix SATA controller init

This commit is contained in:
jmcneill 2015-05-14 00:00:44 +00:00
parent ce18844b86
commit 61041e5fe3
3 changed files with 51 additions and 6 deletions
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16
sys/arch/arm/nvidia/tegra_ahcisata.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tegra_ahcisata.c,v 1.3 2015/05/10 15:31:48 jmcneill Exp $ */
/* $NetBSD: tegra_ahcisata.c,v 1.4 2015/05/14 00:00:44 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.3 2015/05/10 15:31:48 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.4 2015/05/14 00:00:44 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -54,6 +54,8 @@ struct tegra_ahcisata_softc {
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
void *sc_ih;
struct tegra_gpio_pin *sc_pin_power;
};
static void tegra_ahcisata_init(struct tegra_ahcisata_softc *);
@ -73,6 +75,8 @@ tegra_ahcisata_attach(device_t parent, device_t self, void *aux)
struct tegra_ahcisata_softc * const sc = device_private(self);
struct tegraio_attach_args * const tio = aux;
const struct tegra_locators * const loc = &tio->tio_loc;
prop_dictionary_t prop = device_properties(self);
const char *pin;
sc->sc_bst = tio->tio_bst;
bus_space_subregion(tio->tio_bst, tio->tio_bsh,
@ -81,7 +85,7 @@ tegra_ahcisata_attach(device_t parent, device_t self, void *aux)
sc->sc.sc_atac.atac_dev = self;
sc->sc.sc_dmat = tio->tio_dmat;
sc->sc.sc_ahcit = tio->tio_bst;
sc->sc.sc_ahcis = loc->loc_size;
sc->sc.sc_ahcis = loc->loc_size - TEGRA_AHCISATA_OFFSET;
bus_space_subregion(tio->tio_bst, tio->tio_bsh,
loc->loc_offset + TEGRA_AHCISATA_OFFSET,
loc->loc_size - TEGRA_AHCISATA_OFFSET, &sc->sc.sc_ahcih);
@ -90,6 +94,12 @@ tegra_ahcisata_attach(device_t parent, device_t self, void *aux)
aprint_naive("\n");
aprint_normal(": SATA\n");
if (prop_dictionary_get_cstring_nocopy(prop, "power-gpio", &pin)) {
sc->sc_pin_power = tegra_gpio_acquire(pin, GPIO_PIN_OUTPUT);
if (sc->sc_pin_power)
tegra_gpio_write(sc->sc_pin_power, 1);
}
tegra_car_periph_sata_enable();
tegra_ahcisata_init(sc);

22
sys/arch/arm/nvidia/tegra_car.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tegra_car.c,v 1.11 2015/05/13 11:06:13 jmcneill Exp $ */
/* $NetBSD: tegra_car.c,v 1.12 2015/05/14 00:00:44 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.11 2015/05/13 11:06:13 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.12 2015/05/14 00:00:44 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -462,6 +462,23 @@ tegra_car_periph_sata_enable(void)
tegra_car_get_bs(&bst, &bsh);
const u_int pllp_rate = tegra_car_pllp0_rate();
/* Set SATA_OOB clock source to PLLP, 204MHz */
const u_int sataoob_div = pllp_rate / 200000000;
bus_space_write_4(bst, bsh, CAR_CLKSRC_SATA_OOB_REG,
__SHIFTIN(CAR_CLKSRC_SATA_SRC_PLLP_OUT0,
CAR_CLKSRC_SATA_SRC) |
__SHIFTIN(sataoob_div - 1, CAR_CLKSRC_SATA_OOB_DIV));
/* Set SATA clock source to PLLP, 102MHz */
const u_int sata_div = pllp_rate / 100000000;
bus_space_write_4(bst, bsh, CAR_CLKSRC_SATA_REG,
CAR_CLKSRC_SATA_AUX_CLK_ENB |
__SHIFTIN(CAR_CLKSRC_SATA_SRC_PLLP_OUT0,
CAR_CLKSRC_SATA_SRC) |
__SHIFTIN(sata_div - 1, CAR_CLKSRC_SATA_DIV));
/* Enable CML clock for SATA */
tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG,
CAR_PLLE_AUX_CML1_OEN, 0);
@ -475,6 +492,7 @@ tegra_car_periph_sata_enable(void)
tegra_pmc_power(PMC_PARTID_SAX, true);
/* Turn on the clocks to SATA and de-assert resets */
bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_SATACOLD);
bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_SATA);
bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_SATACOLD);
bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_SATA);

19
sys/arch/arm/nvidia/tegra_carreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: tegra_carreg.h,v 1.12 2015/05/13 11:06:13 jmcneill Exp $ */
/* $NetBSD: tegra_carreg.h,v 1.13 2015/05/14 00:00:44 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -308,6 +308,23 @@
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM 0
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ 8
#define CAR_CLKSRC_SATA_OOB_REG 0x420
#define CAR_CLKSRC_SATA_OOB_SRC __BITS(31,29)
#define CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0 0
#define CAR_CLKSRC_SATA_OOB_SRC_PLLC_OUT0 2
#define CAR_CLKSRC_SATA_OOB_SRC_PLLM_OUT0 4
#define CAR_CLKSRC_SATA_OOB_SRC_CLKM 6
#define CAR_CLKSRC_SATA_OOB_DIV __BITS(7,0)
#define CAR_CLKSRC_SATA_REG 0x424
#define CAR_CLKSRC_SATA_SRC __BITS(31,29)
#define CAR_CLKSRC_SATA_SRC_PLLP_OUT0 0
#define CAR_CLKSRC_SATA_SRC_PLLC_OUT0 2
#define CAR_CLKSRC_SATA_SRC_PLLM_OUT0 4
#define CAR_CLKSRC_SATA_SRC_CLKM 6
#define CAR_CLKSRC_SATA_AUX_CLK_ENB __BIT(24)
#define CAR_CLKSRC_SATA_DIV __BITS(7,0)
#define CAR_UTMIP_PLL_CFG0_REG 0x480
#define CAR_UTMIP_PLL_CFG1_REG 0x484