sync with FSF binutils:

- also accept "-maltivec"
	- enable altivec by default
	- add mtvrsave and mfvrsave

the latter two are required for an "altivec" GCC.
This commit is contained in:
mrg 2002-03-04 13:35:42 +00:00
parent 3406f0a3dd
commit 60e3a276af
2 changed files with 5 additions and 2 deletions

View File

@ -849,7 +849,8 @@ md_parse_option (c, arg)
|| strcmp (arg, "603") == 0
|| strcmp (arg, "604") == 0)
ppc_cpu = PPC_OPCODE_PPC;
else if (strcmp (arg, "7400") == 0 || strcmp (arg, "vec") == 0)
else if (strcmp (arg, "7400") == 0 || strcmp (arg, "vec")
|| strcmp (arg, "altivec") == 0)
ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;
/* -mppc64 and -m620 mean to assemble for the 64-bit PowerPC
620. */

View File

@ -1340,7 +1340,7 @@ extract_tbr (insn, invalid)
#define PPC405 PPC403
#define PPC750 PPC
#define PPC860 PPC
#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
@ -1502,6 +1502,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
{ "mfvrsave", VX(4, 256), VX_MASK, PPCVEC, { VD } },
{ "mtvrsave", VX(4, 256), VX_MASK, PPCVEC, { VD } },
{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },