sync with FSF binutils:
- also accept "-maltivec" - enable altivec by default - add mtvrsave and mfvrsave the latter two are required for an "altivec" GCC.
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3
gnu/dist/toolchain/gas/config/tc-ppc.c
vendored
3
gnu/dist/toolchain/gas/config/tc-ppc.c
vendored
@ -849,7 +849,8 @@ md_parse_option (c, arg)
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|| strcmp (arg, "603") == 0
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|| strcmp (arg, "604") == 0)
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ppc_cpu = PPC_OPCODE_PPC;
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else if (strcmp (arg, "7400") == 0 || strcmp (arg, "vec") == 0)
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else if (strcmp (arg, "7400") == 0 || strcmp (arg, "vec")
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|| strcmp (arg, "altivec") == 0)
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ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;
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/* -mppc64 and -m620 mean to assemble for the 64-bit PowerPC
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620. */
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4
gnu/dist/toolchain/opcodes/ppc-opc.c
vendored
4
gnu/dist/toolchain/opcodes/ppc-opc.c
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@ -1340,7 +1340,7 @@ extract_tbr (insn, invalid)
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#define PPC405 PPC403
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#define PPC750 PPC
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#define PPC860 PPC
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#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
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#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
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#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
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#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
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#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
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@ -1502,6 +1502,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "mfvrsave", VX(4, 256), VX_MASK, PPCVEC, { VD } },
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{ "mtvrsave", VX(4, 256), VX_MASK, PPCVEC, { VD } },
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{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
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{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
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{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
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