Rather than having long complicated asm statements, use inlines for
ldrex/strex and let the compiler arrange the code how it wants.
This commit is contained in:
matt
parent
30baf09a3c
commit
60acbcdacb
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@ -1,4 +1,4 @@
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/* $NetBSD: lock.h,v 1.25 2013/08/18 04:31:08 matt Exp $ */
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/* $NetBSD: lock.h,v 1.26 2014/03/12 17:55:02 matt Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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@ -73,116 +73,115 @@ __cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
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#define mb_memory drain_writebuf /* in cpufunc.h */
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#endif
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#if defined(_KERNEL)
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static __inline unsigned char
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__swp(__cpu_simple_lock_t __val, volatile __cpu_simple_lock_t *__ptr)
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{
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#ifdef _ARM_ARCH_6
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uint32_t __rv, __tmp;
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if (sizeof(*__ptr) == 1) {
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__asm volatile(
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"1:\t"
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"ldrexb\t%[__rv], [%[__ptr]]" "\n\t"
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"cmp\t%[__rv],%[__val]" "\n\t"
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#ifdef __thumb__
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"itt\tne" "\n\t"
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#endif
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"strexbne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
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"cmpne\t%[__tmp], #0" "\n\t"
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"bne\t1b" "\n\t"
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#ifdef _ARM_ARCH_7
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"dmb"
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#else
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"mcr\tp15, 0, %[__tmp], c7, c10, 5"
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#endif
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: [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
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: [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
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static __inline unsigned int
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__arm_load_exclusive(__cpu_simple_lock_t *__alp)
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{
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unsigned int __rv;
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if (sizeof(*__alp) == 1) {
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__asm __volatile("ldrexb\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
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} else {
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__asm volatile(
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"1:\t"
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"ldrex\t%[__rv], [%[__ptr]]" "\n\t"
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"cmp\t%[__rv],%[__val]" "\n\t"
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#ifdef __thumb__
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"itt\tne" "\n\t"
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#endif
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"strexne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
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"cmpne\t%[__tmp], #0" "\n\t"
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"bne\t1b" "\n\t"
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#ifdef _ARM_ARCH_7
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"nop"
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#else
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"mcr\tp15, 0, %[__tmp], c7, c10, 5"
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#endif
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: [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
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: [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
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__asm __volatile("ldrex\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
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}
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return __rv;
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#else
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}
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/* returns 0 on success and 1 on failure */
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static __inline unsigned int
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__arm_store_exclusive(__cpu_simple_lock_t *__alp, unsigned int __val)
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{
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unsigned int __rv;
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if (sizeof(*__alp) == 1) {
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__asm __volatile("strexb\t%0,%1,[%2]"
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: "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
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} else {
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__asm __volatile("strex\t%0,%1,[%2]"
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: "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
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}
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return __rv;
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}
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#elif defined(_KERNEL)
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static __inline unsigned char
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__swp(unsigned char __val, __cpu_simple_lock_t *__ptr)
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{
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uint32_t __val32;
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__asm volatile("swpb %0, %1, [%2]"
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__asm volatile("swpb %0, %1, [%2]"
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: "=&r" (__val32) : "r" (__val), "r" (__ptr) : "memory");
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return __val32;
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#endif
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}
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#else
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/*
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* On Cortex-A9 (SMP), SWP no longer guarantees atomic results. Thus we pad
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* out SWP so that when the A9 generates an undefined exception we can replace
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* On MP Cortex, SWP no longer guarantees atomic results. Thus we pad
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* out SWP so that when the cpu generates an undefined exception we can replace
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* the SWP/MOV instructions with the right LDREX/STREX instructions.
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*
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* This is why we force the SWP into the template needed for LDREX/STREX
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* including the extra instructions and extra register for testing the result.
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*/
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static __inline int
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__swp(int __val, volatile int *__ptr)
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__swp(int __val, __cpu_simple_lock_t *__ptr)
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{
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int __rv, __tmp;
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int __tmp;
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__asm volatile(
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"1:\t"
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#ifdef _ARM_ARCH_6
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"ldrex\t%[__rv], [%[__ptr]]" "\n\t"
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"cmp\t%[__rv],%[__val]" "\n\t"
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#ifdef __thumb__
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"it\tne" "\n\t"
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#endif
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"strexne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
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#if 1
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"1:\t" "swp %[__rv], %[__val], [%[__ptr]]"
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"\n\t" "b 2f"
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#else
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"swp\t%[__rv], %[__val], [%[__ptr]]" "\n\t"
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"mov\t%[__tmp], #0" "\n\t"
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"cmp\t%[__rv],%[__val]" "\n\t"
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"1:\t" "ldrex %[__rv],[%[__ptr]]"
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"\n\t" "strex %[__tmp],%[__val],[%[__ptr]]"
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#endif
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"cmpne\t%[__tmp], #0" "\n\t"
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"bne\t1b" "\n\t"
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#ifdef _ARM_ARCH_7
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"dmb"
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#elif defined(_ARM_ARCH_6)
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"mcr\tp15, 0, %[__tmp], c7, c10, 5"
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#else
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"nop"
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#endif
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: [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
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"\n\t" "cmp %[__tmp],#0"
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"\n\t" "bne 1b"
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"\n" "2:"
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: [__rv] "=&r" (__rv), [__tmp] "=&r" (__tmp__)
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: [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
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return __rv;
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}
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#endif /* _KERNEL */
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#endif /* !_ARM_ARCH_6 */
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static inline void
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__arm_membar_producer(void)
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{
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#ifdef _ARM_ARCH_7
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__asm __volatile("dsb");
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#elif defined(_ARM_ARCH_6)
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__asm __volatile("mcr\tp15,0,%0,c7,c10,4" :: "r"(0));
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#endif
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}
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static inline void
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__arm_membar_consumer(void)
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{
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#ifdef _ARM_ARCH_7
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__asm __volatile("dmb");
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#elif defined(_ARM_ARCH_6)
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__asm __volatile("mcr\tp15,0,%0,c7,c10,5" :: "r"(0));
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#endif
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}
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static __inline void __unused
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__cpu_simple_lock_init(__cpu_simple_lock_t *alp)
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__cpu_simple_lock_init(__cpu_simple_lock_t *__alp)
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{
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*alp = __SIMPLELOCK_UNLOCKED;
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#ifdef _ARM_ARCH_7
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__asm __volatile("dsb");
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#endif
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*__alp = __SIMPLELOCK_UNLOCKED;
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__arm_membar_producer();
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}
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#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
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static __inline void __unused
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__cpu_simple_lock(__cpu_simple_lock_t *alp)
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__cpu_simple_lock(__cpu_simple_lock_t *__alp)
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{
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while (__swp(__SIMPLELOCK_LOCKED, alp) != __SIMPLELOCK_UNLOCKED)
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#ifdef _ARM_ARCH_6
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__arm_membar_consumer();
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do {
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/* spin */
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} while (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED
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|| __arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
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__arm_membar_producer();
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#else
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while (__swp(__SIMPLELOCK_LOCKED, __alp) != __SIMPLELOCK_UNLOCKED)
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continue;
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#endif
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}
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#else
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void __cpu_simple_lock(__cpu_simple_lock_t *);
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@ -190,25 +189,41 @@ void __cpu_simple_lock(__cpu_simple_lock_t *);
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#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
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static __inline int __unused
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__cpu_simple_lock_try(__cpu_simple_lock_t *alp)
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__cpu_simple_lock_try(__cpu_simple_lock_t *__alp)
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{
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return (__swp(__SIMPLELOCK_LOCKED, alp) == __SIMPLELOCK_UNLOCKED);
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#ifdef _ARM_ARCH_6
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__arm_membar_consumer();
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do {
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if (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED) {
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return 0;
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}
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} while (__arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
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__arm_membar_producer();
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return 1;
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#else
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return (__swp(__SIMPLELOCK_LOCKED, __alp) == __SIMPLELOCK_UNLOCKED);
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#endif
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}
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#else
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int __cpu_simple_lock_try(__cpu_simple_lock_t *);
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#endif
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static __inline void __unused
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__cpu_simple_unlock(__cpu_simple_lock_t *alp)
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__cpu_simple_unlock(__cpu_simple_lock_t *__alp)
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{
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#ifdef _ARM_ARCH_7
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__asm __volatile("dmb");
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#endif
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*alp = __SIMPLELOCK_UNLOCKED;
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#ifdef _ARM_ARCH_7
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__asm __volatile("dsb");
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#ifdef _ARM_ARCH_8
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if (sizeof(*__alp) == 1) {
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__asm __volatile("stab\t%0, [%1]"
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:: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
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} else {
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__asm __volatile("sta\t%0, [%1]"
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:: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
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}
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#else
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__arm_membar_consumer();
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*__alp = __SIMPLELOCK_UNLOCKED;
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__arm_membar_producer();
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#endif
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}
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