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Hard-align the fields of the structures with __aligned(32), and pass ioff=0 

in the pool cache.
This commit is contained in:
maxv 2019-03-17 06:36:22 +00:00
parent f891e0b1ab
commit 5f9a3f3245
2 changed files with 10 additions and 10 deletions
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10
sys/arch/arm/xscale/iopaau.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: iopaau.c,v 1.17 2012/02/12 16:31:01 matt Exp $ */
/* $NetBSD: iopaau.c,v 1.18 2019/03/17 06:36:22 maxv Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: iopaau.c,v 1.17 2012/02/12 16:31:01 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: iopaau.c,v 1.18 2019/03/17 06:36:22 maxv Exp $");
#include <sys/param.h>
#include <sys/pool.h>
@ -647,13 +647,13 @@ iopaau_attach(struct iopaau_softc *sc)
/*
* Initialize global resources. Ok to do here, since there's
* only one AAU.
* only one AAU. The structures are 32-byte aligned.
*/
iopaau_desc_4_cache = pool_cache_init(sizeof(struct aau_desc_4),
8 * 4, offsetof(struct aau_desc_4, d_nda), 0, "aaud4pl",
8 * 4, 0, 0, "aaud4pl",
NULL, IPL_VM, iopaau_desc_ctor, NULL, NULL);
iopaau_desc_8_cache = pool_cache_init(sizeof(struct aau_desc_8),
8 * 4, offsetof(struct aau_desc_8, d_nda), 0, "aaud8pl",
8 * 4, 0, 0, "aaud8pl",
NULL, IPL_VM, iopaau_desc_ctor, NULL, NULL);
/* Register us with dmover. */

10
sys/arch/arm/xscale/iopaaureg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: iopaaureg.h,v 1.3 2002/08/03 21:58:56 thorpej Exp $ */
/* $NetBSD: iopaaureg.h,v 1.4 2019/03/17 06:36:22 maxv Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@ -61,7 +61,7 @@ struct aau_desc_4 {
uint32_t d_pa; /* our physical address */
/* Hardware portion -- must be 32-byte aligned. */
uint32_t d_nda; /* next descriptor address */
uint32_t d_nda __aligned(32); /* next descriptor address */
uint32_t d_sar[4]; /* source address */
uint32_t d_dar; /* destination address */
uint32_t d_bc; /* byte count */
@ -73,7 +73,7 @@ struct aau_desc_8 {
uint32_t d_pa; /* our physical address */
/* Hardware portion -- must be 32-byte aligned. */
uint32_t d_nda; /* next descriptor address */
uint32_t d_nda __aligned(32); /* next descriptor address */
uint32_t d_sar[4]; /* source address */
uint32_t d_dar; /* destination address */
uint32_t d_bc; /* byte count */
@ -87,7 +87,7 @@ struct aau_desc_16 {
uint32_t d_pa; /* our physical address */
/* Hardware portion -- must be 32-byte aligned. */
uint32_t d_nda; /* next descriptor address */
uint32_t d_nda __aligned(32); /* next descriptor address */
uint32_t d_sar[4]; /* source address */
uint32_t d_dar; /* destination address */
uint32_t d_bc; /* byte count */
@ -104,7 +104,7 @@ struct aau_desc_32 {
uint32_t d_pa; /* our physical address */
/* Hardware portion -- must be 32-byte aligned. */
uint32_t d_nda; /* next descriptor address */
uint32_t d_nda __aligned(32); /* next descriptor address */
uint32_t d_sar[4]; /* source address */
uint32_t d_dar; /* destination address */
uint32_t d_bc; /* byte count */