Shuffle the code to be more readable. Simplify.
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uwe
parent
7ef52537c9
commit
5f93873eda
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@ -1,4 +1,4 @@
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/* $NetBSD: timer_msiiep.c,v 1.15 2005/09/23 23:22:57 uwe Exp $ */
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/* $NetBSD: timer_msiiep.c,v 1.16 2005/09/24 00:35:08 uwe Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -58,7 +58,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: timer_msiiep.c,v 1.15 2005/09/23 23:22:57 uwe Exp $");
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__KERNEL_RCSID(0, "$NetBSD: timer_msiiep.c,v 1.16 2005/09/24 00:35:08 uwe Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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@ -67,21 +67,98 @@ __KERNEL_RCSID(0, "$NetBSD: timer_msiiep.c,v 1.15 2005/09/23 23:22:57 uwe Exp $"
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#include <machine/bus.h>
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#include <sparc/sparc/timerreg.h>
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#include <sparc/sparc/timervar.h>
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#include <sparc/sparc/msiiepreg.h>
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#include <sparc/sparc/msiiepvar.h>
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static struct intrhand level10;
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static struct intrhand level14;
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#include <sparc/sparc/timervar.h>
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static int timermatch_msiiep(struct device *, struct cfdata *, void *);
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static void timerattach_msiiep(struct device *, struct device *, void *);
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CFATTACH_DECL(timer_msiiep, sizeof(struct device),
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timermatch_msiiep, timerattach_msiiep, NULL, NULL);
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static void timer_init_msiiep(void);
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static int clockintr_msiiep(void *);
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static int statintr_msiiep(void *);
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static struct intrhand level10 = { .ih_fun = clockintr_msiiep };
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static struct intrhand level14 = { .ih_fun = statintr_msiiep };
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/*
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* ms-IIep counters tick every 4 CPU clock @100MHz.
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* ms-IIep counters tick every 4 CPU clocks @100MHz.
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* counter is reset to 1 when new limit is written.
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*/
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#define tmr_ustolimIIep(n) ((n) * 25 + 1)
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static int
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timermatch_msiiep(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct msiiep_attach_args *msa = aux;
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return (strcmp(msa->msa_name, "timer") == 0);
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}
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/*
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* Attach system and processor counters (kernel hard and stat clocks)
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* for ms-IIep. Counters are part of the PCIC and there's no PROM
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* node for them.
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*/
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static void
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timerattach_msiiep(struct device *parent, struct device *self, void *aux)
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{
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/* Put processor counter in "counter" mode */
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mspcic_write_1(pcic_pc_ctl, 0); /* stop user timer (just in case) */
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mspcic_write_1(pcic_pc_cfg, 0); /* timer mode disabled */
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/*
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* Calibrate delay() by tweaking the magic constant until
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* delay(100) actually reads (at least) 100 us on the clock.
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*/
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for (timerblurb = 1; ; ++timerblurb) {
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int t;
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mspcic_read_4(pcic_pclr); /* clear the limit bit */
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mspcic_write_4(pcic_pclr, 0); /* reset to 1, free run */
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delay(100);
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t = mspcic_read_4(pcic_pccr);
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if (t < 0) /* limit bit set, cannot happen */
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panic("delay calibration");
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if (t >= 2501) /* (t - 1) / 25 >= 100 us */
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break;
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}
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printf(": delay constant %d\n", timerblurb);
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timer_init = timer_init_msiiep;
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/*
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* Set counter interrupt priority assignment:
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* upper 4 bits are for system counter: level 10
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* lower 4 bits are for processor counter: level 14
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*
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* XXX: ensure that interrupt target mask doesn't mask them?
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*/
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mspcic_write_1(pcic_cipar, 0xae);
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/* link interrupt handlers */
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intr_establish(10, 0, &level10, NULL);
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intr_establish(14, 0, &level14, NULL);
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/* Establish a soft interrupt at a lower level for schedclock */
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sched_cookie = softintr_establish(IPL_SCHED, schedintr, NULL);
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if (sched_cookie == NULL)
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panic("timerattach: cannot establish schedintr");
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}
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/*
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* Set up the real-time and statistics clocks.
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* Leave stathz 0 only if no alternative timer is available.
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@ -92,12 +169,11 @@ static void
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timer_init_msiiep(void)
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{
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/* ms-IIep kernels support *only* IIep */
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mspcic_write_4(pcic_sclr, tmr_ustolimIIep(tick));
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mspcic_write_4(pcic_pclr, tmr_ustolimIIep(statint));
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/* XXX: ensure interrupt target mask doesn't masks them? */
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}
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/*
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* Level 10 (clock) interrupts from system counter.
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*/
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@ -105,12 +181,12 @@ static int
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clockintr_msiiep(void *cap)
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{
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/* read the limit register to clear the interrupt */
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mspcic_read_4(pcic_sclr);
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mspcic_read_4(pcic_sclr); /* clear the interrupt */
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hardclock((struct clockframe *)cap);
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return (1);
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}
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/*
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* Level 14 (stat clock) interrupts from processor counter.
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*/
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@ -120,8 +196,7 @@ statintr_msiiep(void *cap)
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struct clockframe *frame = cap;
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u_long newint;
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/* read the limit register to clear the interrupt */
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mspcic_read_4(pcic_pclr);
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mspcic_read_4(pcic_pclr); /* clear the interrupt */
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statclock(frame);
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@ -131,9 +206,9 @@ statintr_msiiep(void *cap)
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newint = new_interval();
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/*
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* Use the `non-resetting' limit register, so we don't
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* loose the counter ticks that happened since this
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* interrupt was raised.
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* Use the `non-resetting' limit register, so that we don't
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* lose the counter ticks that happened since this interrupt
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* has been raised.
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*/
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mspcic_write_4(pcic_pclr_nr, tmr_ustolimIIep(newint));
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@ -157,73 +232,3 @@ statintr_msiiep(void *cap)
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return (1);
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}
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static int
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timermatch_msiiep(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct msiiep_attach_args *msa = aux;
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return (strcmp(msa->msa_name, "timer") == 0);
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}
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static void
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timerattach_msiiep(struct device *parent, struct device *self, void *aux)
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{
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/*
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* Attach system and CPU counters (kernel hard and stat clocks)
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* for ms-IIep. Counters are part of the PCIC and there's no
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* PROM node for them.
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*/
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/* Put processor counter in "counter" mode */
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mspcic_write_1(pcic_pc_ctl, 0); /* stop user timer (just in case) */
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mspcic_write_1(pcic_pc_cfg, 0); /* timer mode disabled (processor counter) */
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/*
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* Calibrate delay() by tweaking the magic constant
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* until a delay(100) actually reads (at least) 100 us on the clock.
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* Note: ms-IIep clocks ticks every 4 processor cycles.
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*/
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for (timerblurb = 1; ; ++timerblurb) {
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volatile int t;
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/* clear the limit bit */
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mspcic_read_4(pcic_pclr);
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mspcic_write_4(pcic_pclr, 0); /* reset counter to 1, free run */
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delay(100);
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t = mspcic_read_4(pcic_pccr);
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if (t & TMR_LIMIT) /* cannot happen */
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panic("delay calibration");
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/* counter ticks -> usec, inverse of tmr_ustolimIIep */
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t = (t - 1) / 25;
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if (t >= 100)
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break;
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}
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printf(": delay constant %d\n", timerblurb);
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/*
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* Set counter interrupt priority assignment:
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* upper 4 bits are for system counter: level 10
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* lower 4 bits are for processor counter: level 14
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*/
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mspcic_write_1(pcic_cipar, 0xae);
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timer_init = timer_init_msiiep;
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level10.ih_fun = clockintr_msiiep;
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level14.ih_fun = statintr_msiiep;
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/* link interrupt handlers */
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intr_establish(10, 0, &level10, NULL);
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intr_establish(14, 0, &level14, NULL);
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/* Establish a soft interrupt at a lower level for schedclock */
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sched_cookie = softintr_establish(IPL_SCHED, schedintr, NULL);
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if (sched_cookie == NULL)
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panic("timerattach: cannot establish schedintr");
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}
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CFATTACH_DECL(timer_msiiep, sizeof(struct device),
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timermatch_msiiep, timerattach_msiiep, NULL, NULL);
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