parent
cf241ff9b0
commit
5f6b90ba37
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@ -1,4 +1,4 @@
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/* $NetBSD: igphyreg.h,v 1.8 2015/10/26 02:31:31 msaitoh Exp $ */
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/* $NetBSD: igphyreg.h,v 1.9 2016/10/28 05:50:18 msaitoh Exp $ */
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/*******************************************************************************
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/*******************************************************************************
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@ -165,9 +165,8 @@
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* IGP3 regs
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* IGP3 regs
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*/
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*/
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#define IGP3_PAGE_SHIFT 5
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#define IGP3_PAGE_SHIFT 5
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#define IGP3_MAX_REG_ADDRESS 0x1f /* 5 bit address bus (0-0x1f) */
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#define IGP3_REG(page, reg) \
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#define IGP3_REG(page, reg) \
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(((page) << IGP3_PAGE_SHIFT) | ((reg) & IGP3_MAX_REG_ADDRESS))
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(((page) << IGP3_PAGE_SHIFT) | ((reg) & MII_MAXREGADDR))
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#define IGP3_VR_CTRL IGP3_REG(776, 18)
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#define IGP3_VR_CTRL IGP3_REG(776, 18)
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#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
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#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
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@ -1,4 +1,4 @@
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/* $NetBSD: ikphyreg.h,v 1.2 2010/11/29 23:04:42 jym Exp $ */
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/* $NetBSD: ikphyreg.h,v 1.3 2016/10/28 05:50:18 msaitoh Exp $ */
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/*******************************************************************************
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/*******************************************************************************
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Copyright (c) 2001-2005, Intel Corporation
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Copyright (c) 2001-2005, Intel Corporation
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All rights reserved.
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All rights reserved.
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@ -41,10 +41,9 @@ POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#define GG82563_PAGE_SHIFT 5
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#define GG82563_PAGE_SHIFT 5
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#define GG82563_REG(page, reg) \
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#define GG82563_REG(page, reg) \
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(((page) << GG82563_PAGE_SHIFT) | ((reg) & GG82563_MAX_REG_ADDRESS))
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(((page) << GG82563_PAGE_SHIFT) | ((reg) & MII_ADDRMASK))
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#define GG82563_MIN_ALT_REG 30
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#define GG82563_MIN_ALT_REG 30
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#define GG82563_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
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#define GG82563_MAX_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
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#define GG82563_MAX_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
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@ -1,4 +1,4 @@
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/* $NetBSD: inbmphyreg.h,v 1.6 2016/10/19 08:22:57 msaitoh Exp $ */
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/* $NetBSD: inbmphyreg.h,v 1.7 2016/10/28 05:50:18 msaitoh Exp $ */
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/*******************************************************************************
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/*******************************************************************************
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Copyright (c) 2001-2005, Intel Corporation
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Copyright (c) 2001-2005, Intel Corporation
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All rights reserved.
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All rights reserved.
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@ -44,16 +44,15 @@ POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#define BME1000_PAGE_SHIFT 5
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#define BME1000_PAGE_SHIFT 5
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#define BME1000_REG(page, reg) \
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#define BME1000_REG(page, reg) \
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(((page) << BME1000_PAGE_SHIFT) | ((reg) & BME1000_MAX_REG_ADDRESS))
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(((page) << BME1000_PAGE_SHIFT) | ((reg) & MII_ADDRMASK))
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#define BME1000_MAX_REG_ADDRESS 0x1f /* 5 bit address bus (0-0x1f) */
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#define BME1000_MAX_MULTI_PAGE_REG 0xf /* Registers equal on all pages */
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#define BME1000_MAX_MULTI_PAGE_REG 0xf /* Registers equal on all pages */
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#define BM_PHY_REG_PAGE(offset) \
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#define BM_PHY_REG_PAGE(offset) \
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((uint16_t)(((offset) >> BME1000_PAGE_SHIFT) & 0xffff))
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((uint16_t)(((offset) >> BME1000_PAGE_SHIFT) & 0xffff))
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#define BM_PHY_REG_NUM(offset) \
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#define BM_PHY_REG_NUM(offset) \
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((uint16_t)((offset) & BME1000_MAX_REG_ADDRESS) \
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((uint16_t)((offset) & MII_ADDRMASK) \
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| (((offset) >> (21 - BME1000_PAGE_SHIFT)) & ~BME1000_MAX_REG_ADDRESS))
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| (((offset) >> (21 - BME1000_PAGE_SHIFT)) & ~MII_ADDRMASK))
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/* BME1000 Specific Registers */
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/* BME1000 Specific Registers */
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#define BME1000_PHY_SPEC_CTRL BME1000_REG(0, 16) /* PHY Specific Control */
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#define BME1000_PHY_SPEC_CTRL BME1000_REG(0, 16) /* PHY Specific Control */
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/* $NetBSD: if_wm.c,v 1.431 2016/10/28 05:29:11 knakahara Exp $ */
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/* $NetBSD: if_wm.c,v 1.432 2016/10/28 05:50:18 msaitoh Exp $ */
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/*
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -84,7 +84,7 @@
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*/
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*/
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#include <sys/cdefs.h>
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.431 2016/10/28 05:29:11 knakahara Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.432 2016/10/28 05:50:18 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#ifdef _KERNEL_OPT
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#include "opt_net_mpsafe.h"
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#include "opt_net_mpsafe.h"
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return 0;
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return 0;
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}
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}
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if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
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if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG) {
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wm_gmii_mdic_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
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wm_gmii_mdic_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
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reg >> GG82563_PAGE_SHIFT);
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reg >> GG82563_PAGE_SHIFT);
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} else {
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} else {
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}
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}
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/* Wait more 200us for a bug of the ready bit in the MDIC register */
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/* Wait more 200us for a bug of the ready bit in the MDIC register */
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delay(200);
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delay(200);
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rv = wm_gmii_mdic_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS);
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rv = wm_gmii_mdic_readreg(self, phy, reg & MII_ADDRMASK);
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delay(200);
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delay(200);
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sc->phy.release(sc);
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sc->phy.release(sc);
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return;
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return;
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}
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}
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if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
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if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG) {
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wm_gmii_mdic_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
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wm_gmii_mdic_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
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reg >> GG82563_PAGE_SHIFT);
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reg >> GG82563_PAGE_SHIFT);
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} else {
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} else {
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}
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}
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/* Wait more 200us for a bug of the ready bit in the MDIC register */
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/* Wait more 200us for a bug of the ready bit in the MDIC register */
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delay(200);
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delay(200);
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wm_gmii_mdic_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val);
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wm_gmii_mdic_writereg(self, phy, reg & MII_ADDRMASK, val);
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delay(200);
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delay(200);
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sc->phy.release(sc);
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sc->phy.release(sc);
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reg >> GG82563_PAGE_SHIFT);
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reg >> GG82563_PAGE_SHIFT);
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}
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}
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rv = wm_gmii_mdic_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS);
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rv = wm_gmii_mdic_readreg(self, phy, reg & MII_ADDRMASK);
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sc->phy.release(sc);
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sc->phy.release(sc);
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return rv;
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return rv;
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}
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}
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reg >> GG82563_PAGE_SHIFT);
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reg >> GG82563_PAGE_SHIFT);
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}
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}
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wm_gmii_mdic_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val);
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wm_gmii_mdic_writereg(self, phy, reg & MII_ADDRMASK, val);
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sc->phy.release(sc);
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sc->phy.release(sc);
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}
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}
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page << BME1000_PAGE_SHIFT);
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page << BME1000_PAGE_SHIFT);
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}
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}
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rv = wm_gmii_mdic_readreg(self, phy, regnum & IGPHY_MAXREGADDR);
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rv = wm_gmii_mdic_readreg(self, phy, regnum & MII_ADDRMASK);
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return rv;
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return rv;
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}
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}
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page << BME1000_PAGE_SHIFT);
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page << BME1000_PAGE_SHIFT);
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}
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}
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wm_gmii_mdic_writereg(self, phy, regnum & IGPHY_MAXREGADDR, val);
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wm_gmii_mdic_writereg(self, phy, regnum & MII_ADDRMASK, val);
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}
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}
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/*
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/*
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*/
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*/
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child = LIST_FIRST(&sc->sc_mii.mii_phys);
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child = LIST_FIRST(&sc->sc_mii.mii_phys);
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if ((child != NULL) && (child->mii_mpd_rev < 2)) {
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if ((child != NULL) && (child->mii_mpd_rev < 2)) {
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printf("XXX 82578 rev < 2\n");
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PHY_RESET(child);
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PHY_RESET(child);
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sc->sc_mii.mii_writereg(sc->sc_dev, 2, MII_BMCR,
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sc->sc_mii.mii_writereg(sc->sc_dev, 2, MII_BMCR,
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0x3140);
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0x3140);
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Loading…
Reference in New Issue