Add nside(4) - a driver for the National Semiconductor PC87415 IDE
controller as found in many HP PA-RISC machines. From OpenBSD. Reviewed by Manuel Bouyer.
This commit is contained in:
skrll
parent
d7b55f9d71
commit
5f5029c482
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@ -1,4 +1,4 @@
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# $NetBSD: GENERIC,v 1.103 2010/11/09 12:24:47 skrll Exp $
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# $NetBSD: GENERIC,v 1.104 2010/11/10 22:34:24 skrll Exp $
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#
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# GENERIC machine description file
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#
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@ -23,7 +23,7 @@ include "arch/hp700/conf/std.hp700"
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options INCLUDE_CONFIG_FILE # embed config file in kernel binary
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options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
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#ident "GENERIC-$Revision: 1.103 $"
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#ident "GENERIC-$Revision: 1.104 $"
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maxusers 32 # estimated number of users
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@ -416,6 +416,7 @@ cmdide* at pci? dev ? function ? # CMD tech IDE controllers
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cypide* at pci? dev ? function ? # Cypress IDE controllers
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geodeide* at pci? dev ? function ? # AMD Geode IDE controllers
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hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers
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nside* at pci? dev ? function ? # National Semiconductor IDE controllers
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optiide* at pci? dev ? function ? # Opti IDE controllers
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pdcide* at pci? dev ? function ? # Promise IDE controllers
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pdcsata* at pci? dev ? function ? # Promise SATA150 controllers
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@ -1,4 +1,4 @@
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# $NetBSD: files.pci,v 1.332 2010/11/09 12:24:48 skrll Exp $
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# $NetBSD: files.pci,v 1.333 2010/11/10 22:34:24 skrll Exp $
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#
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# Config file and device description for machine-independent PCI code.
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# Included by ports that need it. Requires that the SCSI files be
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@ -274,6 +274,11 @@ attach jmide at pci
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attach ahcisata at jmide_hl with jmahci
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file dev/pci/jmide.c jmide | jmahci needs-flag
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# National Semiconductor IDE controllers
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device nside: ata, ata_dma, ata_udma, pciide_common, wdc_common
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attach nside at pci
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file dev/pci/nside.c nside
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# Opti IDE controllers
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device optiide: ata, ata_dma, pciide_common, wdc_common
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attach optiide at pci
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@ -0,0 +1,260 @@
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/* $NetBSD: nside.c,v 1.1 2010/11/10 22:34:24 skrll Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: nside.c,v 1.1 2010/11/10 22:34:24 skrll Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_natsemi_reg.h>
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static void natsemi_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void natsemi_setup_channel(struct ata_channel*);
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static int natsemi_pci_intr(void *);
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static void natsemi_irqack(struct ata_channel *);
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static int nside_match(device_t, cfdata_t, void *);
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static void nside_attach(device_t, device_t, void *);
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struct nside_softc {
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struct pciide_softc pciide_sc;
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struct pci_attach_args pcib_pa;
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};
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CFATTACH_DECL_NEW(nside, sizeof(struct nside_softc),
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nside_match, nside_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_natsemi_products[] = {
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{ PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */
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0,
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"National Semiconductor PC87415 IDE Controller",
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natsemi_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static int
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nside_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
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PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
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if (pciide_lookup_product(pa->pa_id, pciide_natsemi_products))
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return 2;
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}
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return 0;
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}
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static void
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nside_attach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = device_private(self);
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_natsemi_products));
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}
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static void
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natsemi_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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int channel;
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pcireg_t interface, ctl;
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"bus-master DMA support present");
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pciide_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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sc->sc_wdcdev.irqack = natsemi_irqack;
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}
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pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7);
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/*
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* Mask off interrupts from both channels, appropriate channel(s)
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* will be unmasked later.
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*/
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pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) |
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NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1));
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_set_modes = natsemi_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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interface = PCI_INTERFACE(pa->pa_class);
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interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */
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/* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */
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ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1);
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if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1)))
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ctl &= ~NATSEMI_CTRL1_INTAMASK;
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else
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ctl |= NATSEMI_CTRL1_INTAMASK;
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pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl);
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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pciide_mapchan(pa, cp, interface, natsemi_pci_intr);
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pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) &
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~(NATSEMI_CHMASK(channel)));
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}
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}
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void
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natsemi_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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int drive, ndrives = 0;
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uint32_t idedma_ctl = 0;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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uint8_t tim;
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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ndrives++;
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/* add timing values, setup DMA if needed */
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if ((drvp->drive_flags & DRIVE_DMA) == 0) {
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tim = natsemi_pio_pulse[drvp->PIO_mode] |
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(natsemi_pio_recover[drvp->PIO_mode] << 4);
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} else {
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/*
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* use Multiword DMA
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* Timings will be used for both PIO and DMA,
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* so adjust DMA mode if needed
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*/
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if (drvp->PIO_mode >= 3 &&
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(drvp->DMA_mode + 2) > drvp->PIO_mode) {
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drvp->DMA_mode = drvp->PIO_mode - 2;
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}
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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tim = natsemi_dma_pulse[drvp->DMA_mode] |
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(natsemi_dma_recover[drvp->DMA_mode] << 4);
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}
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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NATSEMI_RTREG(chp->ch_channel, drive), tim);
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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NATSEMI_WTREG(chp->ch_channel, drive), tim);
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}
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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idedma_ctl);
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}
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/* Go ahead and ack interrupts generated during probe. */
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natsemi_irqack(chp);
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}
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void
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natsemi_irqack(struct ata_channel *chp)
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{
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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uint8_t clr;
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/* Errata: The "clear" bits are in the wrong register *sigh* */
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clr = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0);
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clr |= bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0) &
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(IDEDMA_CTL_ERR | IDEDMA_CTL_INTR);
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, clr);
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}
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int
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natsemi_pci_intr(void *arg)
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{
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struct pciide_softc *sc = arg;
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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int i, rv, crv;
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uint8_t msk;
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rv = 0;
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msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2);
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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cp = &sc->pciide_channels[i];
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wdc_cp = &cp->ata_channel;
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/* If a compat channel skip. */
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if (cp->compat)
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continue;
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/* If this channel is masked, skip it. */
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if (msk & NATSEMI_CHMASK(i))
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continue;
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crv = wdcintr(wdc_cp);
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if (crv == 0)
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; /* leave alone */
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else if (crv == 1)
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rv = 1; /* claim the intr */
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else if (rv == 0) /* crv should be -1 in this case */
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rv = crv; /* if we've done no better, take it */
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}
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return (rv);
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}
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@ -0,0 +1,107 @@
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/* $NetBSD: pciide_natsemi_reg.h,v 1.1 2010/11/10 22:34:24 skrll Exp $ */
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/* $OpenBSD: pciide_natsemi_reg.h,v 1.7 2007/06/24 12:41:19 kettenis Exp $ */
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/*
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* Copyright (c) 2001 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_PCIIDE_NATSEMI_REG_H_
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#define _DEV_PCI_PCIIDE_NATSEMI_REG_H_
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/*
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* Register definitions for National Semiconductor PC87415. Definitions
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* based on "PC87415: PCI-IDE DMA Master Mode Interface Controller"
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* (March 1996) datasheet from their website.
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*/
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#define NATSEMI_CTRL1 0x40 /* Control register1 */
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#define NATSEMI_CTRL1_SWRST 0x04 /* sw rst to ch1/ch2 on */
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#define NATSEMI_CTRL1_IDEPWR 0x08
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#define NATSEMI_CTRL1_CH1INTMAP 0x10
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#define NATSEMI_CTRL1_CH2INTMAP 0x20
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#define NATSEMI_CTRL1_INTAMASK 0x40
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#define NATSEMI_CTRL1_IDWR 0x80 /* write to did/vid enable */
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#define NATSEMI_CTRL2 0x41 /* Control register2 */
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#define NATSEMI_CTRL2_CH1MASK 0x01 /* channel 1 intr masked */
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#define NATSEMI_CTRL2_CH2MASK 0x02 /* channel 2 intr masked */
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#define NATSEMI_CTRL2_BARDIS 0x04 /* PCI BAR 2/3 disable */
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#define NATSEMI_CTRL2_WATCHDOG 0x08 /* enable watchdog timer */
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#define NATSEMI_CTRL2_BUF1BYP 0x10 /* bypass buffer 1 */
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#define NATSEMI_CTRL2_BUF2BYP 0x20 /* bypass buffer 2 */
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#define NATSEMI_CTRL2_IDE1MAP 0x40 /* IDE at bar 1 */
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#define NATSEMI_CTRL2_IDE2MAP 0x80 /* IDE at bar 2 */
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#define NATSEMI_CHMASK(chn) (NATSEMI_CTRL2_CH1MASK << (chn))
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#define NATSEMI_CTRL3 0x42 /* Control register3 */
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#define NATSEMI_CTRL3_CH1PREDIS 0x01 /* channel 1 prefetch disable */
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#define NATSEMI_CTRL3_CH2PREDIS 0x02 /* channel 2 prefetch disable */
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#define NATSEMI_CTRL3_RSTIDLE 0x04 /* reset idle state */
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#define NATSEMI_CTRL3_C1D1DMARQ 0x10 /* c1d1 dmarq handshaking */
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#define NATSEMI_CTRL3_C1D2DMARQ 0x20 /* c1d2 dmarq handshaking */
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#define NATSEMI_CTRL3_C2D1DMARQ 0x40 /* c2d1 dmarq handshaking */
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#define NATSEMI_CTRL3_C2D2DMARQ 0x80 /* c2d2 dmarq handshaking */
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#define NATSEMI_WBS 0x43 /* Write buffer status */
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#define NATSEMI_WBS_WB1NMPTY 0x01 /* chan 1 write buf not empty */
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#define NATSEMI_WBS_WB2NMPTY 0x02 /* chan 2 write buf not empty */
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#define NATSEMI_C1D1DRT 0x44 /* Channel 1/device 1 data read timing */
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#define NATSEMI_C1D1DWT 0x45 /* Channel 1/device 1 data write timing */
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#define NATSEMI_C1D2DRT 0x48 /* Channel 1/device 2 data read timing */
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#define NATSEMI_C1D2DWT 0x49 /* Channel 1/device 2 data write timing */
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#define NATSEMI_C2D1DRT 0x4c /* Channel 2/device 1 data read timing */
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#define NATSEMI_C2D1DWT 0x4d /* Channel 2/device 1 data write timing */
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#define NATSEMI_C2D2DRT 0x50 /* Channel 2/device 2 data read timing */
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#define NATSEMI_C2D2DWT 0x51 /* Channel 2/device 2 data write timing */
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#define NATSEMI_CCBT 0x54 /* Command and control block timing */
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#define NATSEMI_SECT 0x55 /* Sector size */
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#define NATSEMI_SECT_C1UNUSED 0x0f /* not used */
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#define NATSEMI_SECT_C1_512 0x0e /* 512 bytes */
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#define NATSEMI_SECT_C1_1024 0x0c /* 1024 bytes */
|
||||
#define NATSEMI_SECT_C1_2048 0x08 /* 2048 bytes */
|
||||
#define NATSEMI_SECT_C1_4096 0x00 /* 4096 bytes */
|
||||
#define NATSEMI_SECT_C2UNUSED 0xf0 /* not used */
|
||||
#define NATSEMI_SECT_C2_512 0xe0 /* 512 bytes */
|
||||
#define NATSEMI_SECT_C2_1024 0xc0 /* 1024 bytes */
|
||||
#define NATSEMI_SECT_C2_2048 0x80 /* 2048 bytes */
|
||||
#define NATSEMI_SECT_C2_4096 0x00 /* 4096 bytes */
|
||||
|
||||
#define NATSEMI_RTREG(c,d) (0x44 + (c * 8) + (d * 4) + 0)
|
||||
#define NATSEMI_WTREG(c,d) (0x44 + (c * 8) + (d * 4) + 1)
|
||||
|
||||
/* 17 - N = number of clocks */
|
||||
static u_int8_t natsemi_pio_pulse[] = { 7, 12, 13, 14, 14 };
|
||||
static u_int8_t natsemi_dma_pulse[] = { 7, 10, 10 };
|
||||
/* 16 - N = number of clocks */
|
||||
static u_int8_t natsemi_pio_recover[] = { 6, 8, 11, 13, 15 };
|
||||
static u_int8_t natsemi_dma_recover[] = { 6, 8, 9 };
|
||||
|
||||
#endif /* !_DEV_PCI_PCIIDE_NATSEMI_REG_H_ */
|
||||
Loading…
Reference in New Issue