re-implement blast_dcache() and blast_icache() via function pointers so that
we can set these to functions that simply return on sun4us/sun4v systems. also include some work-in-progress #if 0'ed code to do the same for the dcache_flush*() functions. (some of these could probably move into the cpuinfo except that sparc64 systems don't really ever work with mismatches AFAICT.)
This commit is contained in:
mrg
parent
5bf0fb60b1
commit
5f30cba72a
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@ -1,4 +1,4 @@
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# $NetBSD: files.sparc64,v 1.130 2011/04/09 19:31:14 jdc Exp $
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# $NetBSD: files.sparc64,v 1.131 2011/06/06 01:16:48 mrg Exp $
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# @(#)files.sparc64 8.1 (Berkeley) 7/19/93
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# sparc64-specific configuration info
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@ -206,6 +206,7 @@ file arch/sparc/fpu/fpu_subr.c
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file arch/sparc/sparc/promlib.c
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file arch/sparc64/sparc64/autoconf.c
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file arch/sparc64/sparc64/clock.c
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file arch/sparc64/sparc64/cache.c
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file arch/sparc64/sparc64/core_machdep.c coredump
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file arch/sparc64/sparc64/emul.c
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file arch/sparc64/sparc64/intr.c
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@ -0,0 +1,105 @@
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/* $NetBSD: cache.c,v 1.7 2011/06/06 01:16:48 mrg Exp $ */
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/*
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* Copyright (c) 2011 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Handle picking the right types of the different cache call.
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*
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* This module could take on a larger role.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.7 2011/06/06 01:16:48 mrg Exp $");
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#include "opt_multiprocessor.h"
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#include <sys/param.h>
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#include <sys/reboot.h>
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#include <machine/cpu.h>
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#include <sparc64/sparc64/cache.h>
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static void
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cache_nop(void)
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{
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}
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static void
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blast_dcache_real(void)
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{
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sp_blast_dcache(dcache_size, dcache_line_size);
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}
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#if 0
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static void
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sp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t cs)
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{
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dcache_flush_page(pa);
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}
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void (*dcache_flush_page)(paddr_t) = dcache_flush_page_us;
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void (*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t) =
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sp_dcache_flush_page_cpuset;
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#endif
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void (*blast_dcache)(void) = blast_dcache_real;
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void (*blast_icache)(void) = blast_icache_us;
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void
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cache_setup_funcs(void)
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{
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if (CPU_ISSUN4US || CPU_ISSUN4V) {
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#if 0
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dcache_flush_page = (void (*)(paddr_t)) cache_nop;
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#endif
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blast_dcache = cache_nop;
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blast_icache = cache_nop;
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} else {
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if (CPU_IS_USIII_UP()) {
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#if 0
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dcache_flush_page = dcache_flush_page_usiii;
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#endif
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blast_icache = blast_icache_usiii;
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printf("set usIII dcache/icache funcs\n");
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}
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#ifdef MULTIPROCESSOR
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if (sparc_ncpus > 1 && (boothowto & RB_MD1) == 0) {
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printf("set MP dcache funcs\n");
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#if 0
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dcache_flush_page = smp_dcache_flush_page_allcpu;
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dcache_flush_page_cpuset = smp_dcache_flush_page_cpuset;
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#endif
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blast_dcache = smp_blast_dcache;
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}
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#endif
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}
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}
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@ -1,14 +1,8 @@
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/* $NetBSD: cache.h,v 1.20 2011/05/25 12:01:31 mrg Exp $ */
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/* $NetBSD: cache.h,v 1.21 2011/06/06 01:16:48 mrg Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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* Copyright (c) 2011 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -18,20 +12,36 @@
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Aaron Brown and
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* Harvard University.
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (C) 1996-1999 Eduardo Horvath.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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@ -40,7 +50,6 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cache.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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@ -112,17 +121,6 @@ cache_flush_phys(paddr_t pa, psize_t size, int ecache)
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cache_flush_phys_us(pa, size, ecache);
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}
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static __inline__ void
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blast_icache(void)
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{
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if (CPU_ISSUN4US || CPU_ISSUN4V)
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return;
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if (CPU_IS_USIII_UP())
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blast_icache_usiii();
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else
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blast_icache_us();
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}
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/* SPARC64 specific */
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/* Assembly routines to flush TLB mappings */
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void sp_tlb_flush_pte_us(vaddr_t, int);
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@ -148,24 +146,25 @@ sp_tlb_flush_all(void)
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sp_tlb_flush_all_us();
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}
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#if 0
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extern void (*dcache_flush_page)(paddr_t);
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extern void (*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t);
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#endif
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extern void (*blast_dcache)(void);
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extern void (*blast_icache)(void);
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void cache_setup_funcs(void);
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#ifdef MULTIPROCESSOR
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void smp_tlb_flush_pte(vaddr_t, struct pmap *);
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void smp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t);
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void smp_blast_dcache(sparc64_cpuset_t);
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void smp_blast_dcache(void);
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#define tlb_flush_pte(va,pm ) smp_tlb_flush_pte(va, pm)
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#define dcache_flush_page_all(pa) smp_dcache_flush_page_cpuset(pa, cpus_active)
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#define dcache_flush_page_cpuset(pa,cs) smp_dcache_flush_page_cpuset(pa, cs)
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#define blast_dcache() smp_blast_dcache(cpus_active)
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#else
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#define tlb_flush_pte(va,pm) sp_tlb_flush_pte(va, (pm)->pm_ctx[0])
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#define dcache_flush_page_all(pa) dcache_flush_page(pa)
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#define dcache_flush_page_cpuset(pa,cs) dcache_flush_page(pa)
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static __inline__ void
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blast_dcache(void)
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{
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if (CPU_ISSUN4US || CPU_ISSUN4V)
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return;
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sp_blast_dcache(dcache_size, dcache_line_size);
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}
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: ipifuncs.c,v 1.40 2011/05/12 05:43:40 mrg Exp $ */
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/* $NetBSD: ipifuncs.c,v 1.41 2011/06/06 01:16:48 mrg Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.40 2011/05/12 05:43:40 mrg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.41 2011/06/06 01:16:48 mrg Exp $");
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#include "opt_ddb.h"
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@ -434,17 +434,26 @@ smp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t activecpus)
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dcache_flush_page(pa);
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}
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#if 0
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void
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smp_dcache_flush_page_allcpu(paddr_t pa)
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{
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smp_dcache_flush_page_cpuset(pa, cpus_active);
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}
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#endif
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/*
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* Flush the D$ on this set of CPUs.
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* Flush the D$ on all CPUs.
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*/
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void
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smp_blast_dcache(sparc64_cpuset_t activecpus)
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smp_blast_dcache(void)
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{
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if (CPU_ISSUN4US || CPU_ISSUN4V)
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return;
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sparc64_multicast_ipi(activecpus, sparc64_ipi_blast_dcache,
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sparc64_multicast_ipi(cpus_active, sparc64_ipi_blast_dcache,
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dcache_size, dcache_line_size);
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sp_blast_dcache(dcache_size, dcache_line_size);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.271 2011/05/12 05:44:09 mrg Exp $ */
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/* $NetBSD: pmap.c,v 1.272 2011/06/06 01:16:48 mrg Exp $ */
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/*
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*
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* Copyright (C) 1996-1999 Eduardo Horvath.
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@ -26,7 +26,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.271 2011/05/12 05:44:09 mrg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.272 2011/06/06 01:16:48 mrg Exp $");
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#undef NO_VCACHE /* Don't forget the locked TLB in dostart */
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#define HWREF
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@ -292,7 +292,7 @@ struct {
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#define PDB_REMOVE 0x000004
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#define PDB_CHANGEPROT 0x000008
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#define PDB_ENTER 0x000010
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#define PDB_DEMAP 0x000020
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#define PDB_DEMAP 0x000020 /* used in locore */
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#define PDB_REF 0x000040
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#define PDB_COPY 0x000080
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#define PDB_MMU_ALLOC 0x000100
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@ -684,6 +684,8 @@ pmap_bootstrap(u_long kernelstart, u_long kernelend)
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BDPRINTF(PDB_BOOT, ("Entered pmap_bootstrap.\n"));
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cache_setup_funcs();
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/*
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* Calculate kernel size.
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*/
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Reference in New Issue