Adjust egister usage so that r4 and r5 are preserved as cur{cpu,lwp}
respectively as required by the change to make ASTs operate per-LWP rather than per-CPU. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS expects this. Remove the call to dosoftints while I'm here as it's dont in DO_AST... XXX untested
This commit is contained in:
skrll
parent
3d0ba503ae
commit
5e6a531eb4
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@ -1,4 +1,4 @@
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/* $NetBSD: ofw_irq.S,v 1.16 2020/11/21 09:36:27 skrll Exp $ */
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/* $NetBSD: ofw_irq.S,v 1.17 2020/11/21 19:57:35 skrll Exp $ */
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/*
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* Copyright (c) 1994-1998 Mark Brinicombe.
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@ -95,12 +95,13 @@ AST_ALIGNMENT_FAULT_LOCALS
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* Regsister usage
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*
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* r4 - Address of cpu_info (on entry)
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* r5 - Pointer to handler pointer list
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* r5 - Address of curlwp
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* r6 - Address of current handler
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* r7 - pspr mode (must be preserved)
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* r8 - Current IRQ requests.
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* r9 - Used to count through possible IRQ bits.
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* r10 - Base address of IOMD
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* r11 - Pointer to handler pointer list
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*/
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ASENTRY_NP(irq_entry)
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@ -188,7 +189,7 @@ ofwtakeint:
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#ifdef EXEC_AOUT
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ldr r0, [sp] /* Fetch SPSR */
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#endif
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ENABLE_ALIGNMENT_FAULTS
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ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
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mov r8, #0x00000001 /* timer interrupt pending! */
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mov r8, r8, lsl #IRQ_TIMER0
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@ -224,17 +225,17 @@ ofwtakeint:
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*/
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mov r9, #(NIPL - 1)
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ldr r5, Lspl_masks
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ldr r11, Lspl_masks
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Lfind_highest_ipl:
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ldr r2, [r5, r9, lsl #2]
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ldr r2, [r11, r9, lsl #2]
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tst r8, r2
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subeq r9, r9, #1
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beq Lfind_highest_ipl
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/* r9 = SPL level of highest priority interrupt */
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add r9, r9, #1
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ldr r2, [r5, r9, lsl #2]
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ldr r2, [r11, r9, lsl #2]
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mvn r2, r2
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orr r0, r0, r2
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@ -252,7 +253,7 @@ Lfind_highest_ipl:
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bic r0, r0, #I32_bit
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msr cpsr_all, r0
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ldr r5, Lirqhandlers
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ldr r11, Lirqhandlers
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mov r9, #0x00000001
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irqloop:
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@ -260,7 +261,7 @@ irqloop:
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tst r8, r9 /* Is a bit set ? */
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beq nextirq /* No ? try next bit */
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ldr r6, [r5] /* Get address of first handler structure */
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ldr r6, [r11] /* Get address of first handler structure */
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teq r6, #0x00000000 /* Do we have a handler */
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moveq r0, r8 /* IRQ requests as arg 0 */
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@ -301,7 +302,7 @@ irqdone:
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stmia r3, {r1-r2} /* store ev_count */
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nextirq:
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add r5, r5, #0x00000004 /* update pointer to handlers */
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add r11, r11, #0x00000004 /* update pointer to handlers */
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mov r9, r9, lsl #1 /* move on to next bit */
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teq r9, #(1 << 24) /* done the last bit ? */
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bne irqloop /* no - loop back. */
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@ -315,8 +316,6 @@ nextirq:
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str r2, [r1]
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bl _C_LABEL(irq_setmasks)
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bl _C_LABEL(dosoftints) /* Handle the soft interrupts */
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr
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orr r0, r0, #(I32_bit)
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@ -1,4 +1,4 @@
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/* $NetBSD: sa11x0_irq.S,v 1.19 2020/11/21 09:36:27 skrll Exp $ */
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/* $NetBSD: sa11x0_irq.S,v 1.20 2020/11/21 19:59:10 skrll Exp $ */
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/*
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* Copyright (c) 1998 Mark Brinicombe.
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@ -72,20 +72,21 @@ AST_ALIGNMENT_FAULT_LOCALS
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/*
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* Register usage
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*
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* r4 - Pointer to cpu_info
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* r5 - Pointer to handler pointer list
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* r4 - Pointer to curcpu
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* r5 - pointer to curlwp
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* r6 - Address of current handler
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* r7 - pspr mode
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* r8 - Current IRQ requests.
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* r9 - Used to count through possible IRQ bits.
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* r10 - Base address of SAIP
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* r11 - Pointer to handler pointer list
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*/
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ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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ENABLE_ALIGNMENT_FAULTS
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ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
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/* Load r8 with the SAIPIC interrupt requests */
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@ -123,17 +124,17 @@ ASENTRY_NP(irq_entry)
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*/
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mov r9, #(NIPL - 1)
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ldr r5, Lspl_masks
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ldr r11, Lspl_masks
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Lfind_highest_ipl:
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ldr r2, [r5, r9, lsl #2]
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ldr r2, [r11, r9, lsl #2]
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tst r8, r2
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subeq r9, r9, #1
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beq Lfind_highest_ipl
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/* r9 = SPL level of highest priority interrupt */
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add r9, r9, #1
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ldr r2, [r5, r9, lsl #2]
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ldr r2, [r11, r9, lsl #2]
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ldr r1, [r4, #CI_CPL]
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str r9, [r4, #CI_CPL]
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@ -154,7 +155,7 @@ Lfind_highest_ipl:
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bic r0, r0, #I32_bit
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msr cpsr_all, r0
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ldr r5, Lirqhandlers
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ldr r11, Lirqhandlers
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mov r9, #0x00000001
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irqloop:
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@ -162,7 +163,7 @@ irqloop:
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tst r8, r9 /* Is a bit set ? */
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beq nextirq /* No ? try next bit */
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ldr r6, [r5] /* Get address of first handler structure */
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ldr r6, [r11] /* Get address of first handler structure */
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teq r6, #0x00000000 /* Do we have a handler */
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moveq r0, r8 /* IRQ requests as arg 0 */
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@ -218,7 +219,7 @@ irqchainloop:
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irqdone:
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nextirq:
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add r5, r5, #0x00000004 /* update pointer to handlers */
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add r11, r11, #0x00000004 /* update pointer to handlers */
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mov r9, r9, lsl #1 /* move on to next bit */
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teq r9, #(1 << 31) /* done the last bit ? */
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bne irqloop /* no - loop back. */
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@ -229,10 +230,6 @@ nextirq:
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/* Restore previous disabled mask */
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bl _C_LABEL(irq_setmasks)
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#ifdef __HAVE_FAST_SOFTINTS
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bl _C_LABEL(dosoftints) /* Handle the soft interrupts */
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#endif
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr
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orr r0, r0, #(I32_bit)
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@ -1,4 +1,4 @@
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/* $NetBSD: isa_irq.S,v 1.17 2018/01/30 19:22:28 skrll Exp $ */
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/* $NetBSD: isa_irq.S,v 1.18 2020/11/21 19:58:11 skrll Exp $ */
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/*
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* Copyright 1997
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@ -113,8 +113,8 @@
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/*
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* Register usage
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*
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* r5 - Pointer to handler pointer list
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* r6 - Address of current handler
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* r7 - Pointer to handler pointer list
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* r8 - Current IRQ requests.
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* r9 - Used to count through possible IRQ bits.
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* r10 - Base address of IOMD
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@ -125,7 +125,7 @@ ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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ENABLE_ALIGNMENT_FAULTS /* cpuinfo is in r4 after execution */
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ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
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/* Load r8 with the ISA 8259 irqs */
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/* r8 <- irq's pending [15:0] */
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@ -183,17 +183,17 @@ ASENTRY_NP(irq_entry)
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*/
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mov r9, #(NIPL - 1)
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ldr r5, .Lspl_masks
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ldr r7, .Lspl_masks
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.Lfind_highest_ipl:
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ldr r2, [r5, r9, lsl #2]
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ldr r2, [r7, r9, lsl #2]
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tst r8, r2
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subeq r9, r9, #1
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beq .Lfind_highest_ipl
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/* r9 = SPL level of highest priority interrupt */
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add r9, r9, #1
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ldr r2, [r5, r9, lsl #2]
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ldr r2, [r7, r9, lsl #2]
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mvn r2, r2
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orr r0, r0, r2
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@ -210,7 +210,7 @@ ASENTRY_NP(irq_entry)
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bic r0, r0, #I32_bit
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msr cpsr_all, r0
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ldr r5, .Lirqhandlers
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ldr r7, .Lirqhandlers
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mov r9, #0x00000001
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irqloop:
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@ -218,7 +218,7 @@ irqloop:
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tst r8, r9 /* Is a bit set ? */
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beq nextirq /* No ? try next bit */
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ldr r6, [r5] /* Get address of first handler structure */
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ldr r6, [r7] /* Get address of first handler structure */
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teq r6, #0x00000000 /* Do we have a handler */
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moveq r0, r8 /* IRQ requests as arg 0 */
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@ -255,7 +255,7 @@ irqdone:
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stmia r3, {r1-r2} /* store ev_count */
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nextirq:
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add r5, r5, #0x00000004 /* update pointer to handlers */
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add r7, r7, #0x00000004 /* update pointer to handlers */
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mov r9, r9, lsl #1 /* move on to next bit */
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teq r9, #(1 << 16) /* done the last bit ? */
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bne irqloop /* no - loop back. */
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@ -269,10 +269,6 @@ nextirq:
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str r2, [r1]
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bl _C_LABEL(irq_setmasks)
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#ifdef __HAVE_FAST_SOFTINTS
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bl _C_LABEL(dosoftints) /* Handle the soft interrupts */
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#endif
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr
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orr r0, r0, #(I32_bit)
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