Add some code to support 82580[ER]. Tested on my own I340-T4.
- Fix CTRL_EXT_SWDPIN() and CTRL_EXT_SWDPIO() macros. The bit order of the SW definable pin is not 6543 but 3654!!! - Rewrite the code to read MAC address from eeprom. - Add some code to support 82580. TODO: - ukphy -> somephy
This commit is contained in:
msaitoh
parent
d6d8c40941
commit
5e478d2ed7
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.207 2010/05/25 01:17:55 msaitoh Exp $ */
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/* $NetBSD: if_wm.c,v 1.208 2010/06/25 04:03:14 msaitoh Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -76,7 +76,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.207 2010/05/25 01:17:55 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.208 2010/06/25 04:03:14 msaitoh Exp $");
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#include "rnd.h"
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@ -510,6 +510,7 @@ static int wm_add_rxbuf(struct wm_softc *, int);
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static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *);
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static int wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *);
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static int wm_validate_eeprom_checksum(struct wm_softc *);
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static int wm_read_mac_addr(struct wm_softc *, uint8_t *);
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static void wm_tick(void *);
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static void wm_set_filter(struct wm_softc *);
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@ -1098,7 +1099,7 @@ wm_attach(device_t parent, device_t self, void *aux)
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prop_data_t ea;
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prop_number_t pn;
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uint8_t enaddr[ETHER_ADDR_LEN];
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uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin, io3;
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uint16_t cfg1, cfg2, swdpin, io3;
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pcireg_t preg, memtype;
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uint16_t eeprom_data, apme_mask;
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uint32_t reg;
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@ -1246,7 +1247,8 @@ wm_attach(device_t parent, device_t self, void *aux)
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*/
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if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
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|| (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003)
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|| (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576))
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|| (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
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|| (sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER))
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sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
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>> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;
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else
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@ -1605,29 +1607,10 @@ wm_attach(device_t parent, device_t self, void *aux)
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KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
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memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
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} else {
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if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
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sizeof(myea) / sizeof(myea[0]), myea)) {
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if (wm_read_mac_addr(sc, enaddr) != 0)
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aprint_error_dev(sc->sc_dev,
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"unable to read Ethernet address\n");
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return;
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}
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enaddr[0] = myea[0] & 0xff;
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enaddr[1] = myea[0] >> 8;
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enaddr[2] = myea[1] & 0xff;
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enaddr[3] = myea[1] >> 8;
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enaddr[4] = myea[2] & 0xff;
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enaddr[5] = myea[2] >> 8;
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}
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/*
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* Toggle the LSB of the MAC address on the second port
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* of the dual port controller.
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*/
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if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
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|| (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003)
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|| (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) {
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if (sc->sc_funcid == 1)
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enaddr[5] ^= 1;
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return;
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}
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aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
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@ -3595,6 +3578,8 @@ wm_reset(struct wm_softc *sc)
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case WM_T_82574:
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case WM_T_82575:
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case WM_T_82576:
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case WM_T_82580:
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case WM_T_82580ER:
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case WM_T_82583:
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default:
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/* Everything else can safely use the documented method. */
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@ -3653,6 +3638,8 @@ wm_reset(struct wm_softc *sc)
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break;
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case WM_T_82575:
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case WM_T_82576:
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case WM_T_82580:
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case WM_T_82580ER:
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case WM_T_80003:
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case WM_T_ICH8:
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case WM_T_ICH9:
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@ -3671,13 +3658,19 @@ wm_reset(struct wm_softc *sc)
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switch (sc->sc_type) {
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case WM_T_82575:
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case WM_T_82576:
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#if 0 /* XXX */
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case WM_T_82580:
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case WM_T_82580ER:
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#endif
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case WM_T_ICH8:
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case WM_T_ICH9:
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if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
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/* Not found */
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sc->sc_flags |= WM_F_EEPROM_INVALID;
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if (sc->sc_type == WM_T_82575) /* 82575 only */
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if ((sc->sc_type == WM_T_82575)
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|| (sc->sc_type == WM_T_82576)
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|| (sc->sc_type == WM_T_82580)
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|| (sc->sc_type == WM_T_82580ER))
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wm_reset_init_script_82575(sc);
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}
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break;
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@ -3685,6 +3678,11 @@ wm_reset(struct wm_softc *sc)
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break;
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}
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if ((sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)) {
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/* clear global device reset status bit */
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CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
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}
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/* Clear any pending interrupt events. */
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CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
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reg = CSR_READ(sc, WMREG_ICR);
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@ -4224,6 +4222,8 @@ wm_get_auto_rd_done(struct wm_softc *sc)
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case WM_T_82583:
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case WM_T_82575:
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case WM_T_82576:
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case WM_T_82580:
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case WM_T_82580ER:
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case WM_T_80003:
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case WM_T_ICH8:
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case WM_T_ICH9:
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@ -4309,6 +4309,7 @@ wm_get_cfg_done(struct wm_softc *sc)
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case WM_T_82575:
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case WM_T_82576:
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case WM_T_82580:
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case WM_T_82580ER:
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mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid;
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for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) {
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if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
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@ -4692,6 +4693,101 @@ wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
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return done;
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}
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static int
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wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)
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{
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uint16_t myea[ETHER_ADDR_LEN / 2];
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uint16_t offset;
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int do_invert = 0;
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if (sc->sc_funcid == 0)
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offset = EEPROM_OFF_MACADDR;
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else {
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switch (sc->sc_type) {
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case WM_T_82580:
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case WM_T_82580ER:
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switch (sc->sc_funcid) {
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case 1:
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offset = EEPROM_OFF_LAN1;
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break;
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case 2:
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offset = EEPROM_OFF_LAN2;
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break;
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case 3:
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offset = EEPROM_OFF_LAN3;
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break;
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default:
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goto bad;
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/* NOTREACHED */
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break;
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}
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break;
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case WM_T_82571:
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case WM_T_82575:
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case WM_T_82576:
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case WM_T_80003:
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if (wm_read_eeprom(sc, EEPROM_ALT_MAC_ADDR_PTR, 1,
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&offset) != 0) {
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goto bad;
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}
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/* no pointer */
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if (offset == 0xffff) {
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/* reset the offset to LAN0 */
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offset = EEPROM_OFF_MACADDR;
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do_invert = 1;
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goto do_read;
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}
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switch (sc->sc_funcid) {
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case 1:
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offset += EEPROM_OFF_MACADDR_LAN1;
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break;
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case 2:
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offset += EEPROM_OFF_MACADDR_LAN2;
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break;
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case 3:
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offset += EEPROM_OFF_MACADDR_LAN3;
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break;
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default:
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goto bad;
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/* NOTREACHED */
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break;
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}
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break;
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default:
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do_invert = 1;
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break;
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}
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}
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do_read:
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if (wm_read_eeprom(sc, offset, sizeof(myea) / sizeof(myea[0]),
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myea) != 0) {
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goto bad;
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}
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enaddr[0] = myea[0] & 0xff;
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enaddr[1] = myea[0] >> 8;
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enaddr[2] = myea[1] & 0xff;
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enaddr[3] = myea[1] >> 8;
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enaddr[4] = myea[2] & 0xff;
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enaddr[5] = myea[2] >> 8;
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/*
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* Toggle the LSB of the MAC address on the second port
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* of some dual port cards.
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*/
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if (do_invert != 0)
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enaddr[5] ^= 1;
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return 0;
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bad:
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aprint_error_dev(sc->sc_dev, "unable to read Ethernet address\n");
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return -1;
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}
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/*
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* wm_add_rxbuf:
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*
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@ -5494,8 +5590,35 @@ wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
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ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
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wm_gmii_mediastatus);
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mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
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MII_OFFSET_ANY, MIIF_DOPAUSE);
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if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
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|| (sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)) {
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if ((sc->sc_flags & WM_F_SGMII) == 0) {
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/* Attach only one port */
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mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
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MII_OFFSET_ANY, MIIF_DOPAUSE);
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} else {
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int i;
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uint32_t ctrl_ext;
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/* Power on sgmii phy if it is disabled */
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ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
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CSR_WRITE(sc, WMREG_CTRL_EXT,
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ctrl_ext &~ CTRL_EXT_SWDPIN(3));
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CSR_WRITE_FLUSH(sc);
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delay(300*1000); /* XXX too long */
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/* from 1 to 8 */
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for (i = 1; i < 8; i++)
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mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
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i, MII_OFFSET_ANY, MIIF_DOPAUSE);
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/* restore previous sfp cage power state */
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CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
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}
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} else {
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mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
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MII_OFFSET_ANY, MIIF_DOPAUSE);
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}
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if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
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/* if failed, retry with *_bm_* */
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@ -7290,6 +7413,10 @@ wm_get_wakeup(struct wm_softc *sc)
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case WM_T_82574:
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case WM_T_82575:
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case WM_T_82576:
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#if 0 /* XXX */
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case WM_T_82580:
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case WM_T_82580ER:
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#endif
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if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE_MASK) != 0)
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sc->sc_flags |= WM_F_ARC_SUBSYS_VALID;
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sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wmreg.h,v 1.41 2010/06/25 03:47:57 msaitoh Exp $ */
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/* $NetBSD: if_wmreg.h,v 1.42 2010/06/25 04:03:14 msaitoh Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -232,6 +232,7 @@ struct livengood_tcpip_ctxdesc {
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#define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2)
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#define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3)
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#define STATUS_GIO_M_ENA (1U << 19) /* GIO master enable */
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#define STATUS_DEV_RST_SET (1U << 20) /* Device Reset Set */
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#define WMREG_EECD 0x0010 /* EEPROM Control Register */
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#define EECD_SK (1U << 0) /* clock */
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@ -280,6 +281,7 @@ struct livengood_tcpip_ctxdesc {
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#define EEPROM_OFF_K1_CONFIG 0x1b /* NVM K1 Config */
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#define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */
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#define EEPROM_OFF_CFG3_PORTA 0x24 /* config word 3 */
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#define EEPROM_ALT_MAC_ADDR_PTR 0x37 /* to the alternative MAC addresses */
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#define EEPROM_CFG1_LVDID (1U << 0)
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#define EEPROM_CFG1_LSSID (1U << 1)
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@ -323,6 +325,18 @@ struct livengood_tcpip_ctxdesc {
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#define EEPROM_CFG3_APME (1U << 10)
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#define EEPROM_OFF_MACADDR_LAN1 3 /* macaddr offset from PTR (port 1) */
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#define EEPROM_OFF_MACADDR_LAN2 6 /* macaddr offset from PTR (port 2) */
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#define EEPROM_OFF_MACADDR_LAN3 9 /* macaddr offset from PTR (port 3) */
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/*
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* EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning"
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* in 82580's datasheet.
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*/
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#define EEPROM_OFF_LAN1 0x0080 /* Offset for LAN1 (82580)*/
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#define EEPROM_OFF_LAN2 0x00c0 /* Offset for LAN1 (82580)*/
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#define EEPROM_OFF_LAN3 0x0100 /* Offset for LAN1 (82580)*/
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#define WMREG_EERD 0x0014 /* EEPROM read */
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#define EERD_DONE 0x02 /* done bit */
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#define EERD_START 0x01 /* First bit for telling part to start operation */
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@ -333,10 +347,13 @@ struct livengood_tcpip_ctxdesc {
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#define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */
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#define CTRL_EXT_SWDPINS_SHIFT 4
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#define CTRL_EXT_SWDPINS_MASK 0x0d
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#define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT + (x) - 4))
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/* The bit order of the SW Definable pin is not 6543 but 3654! */
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#define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT \
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+ ((x) == 3 ? 3 : ((x) - 4))))
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#define CTRL_EXT_SWDPIO_SHIFT 8
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#define CTRL_EXT_SWDPIO_MASK 0x0d
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#define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT + (x) - 4))
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#define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \
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+ ((x) == 3 ? 3 : ((x) - 4))))
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#define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */
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#define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */
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#define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */
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