Support Intel PXA250 and PXA210 application processors.
This commit is contained in:
bsh
parent
6875b78ca7
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/* $NetBSD: pxa2x0.c,v 1.1 2002/10/19 19:31:38 bsh Exp $ */
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/*
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* Copyright (c) 2002 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
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||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* Autoconfiguration support for the Intel PXA2[15]0 application
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* processor. This code is derived from arm/sa11x0/sa11x0.c
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*/
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/*-
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* Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by IWAMOTO Toshihiro and Ichiro FUKUHARA.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*/
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/*-
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* Copyright (c) 1999
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* Shin Takemura and PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/reboot.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <arm/cpufunc.h>
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#include <arm/mainbus/mainbus.h>
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#include <arm/xscale/pxa2x0reg.h>
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#include <arm/xscale/pxa2x0var.h>
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#include "locators.h"
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/* prototypes */
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static int pxa2x0_match(struct device *, struct cfdata *, void *);
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static void pxa2x0_attach(struct device *, struct device *, void *);
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static int pxa2x0_search(struct device *, struct cfdata *, void *);
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/* attach structures */
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CFATTACH_DECL(pxaip, sizeof(struct pxa2x0_softc), pxa2x0_match, pxa2x0_attach,
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NULL, NULL);
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extern struct bus_space pxa2x0_bs_tag;
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struct pxa2x0_softc *pxa2x0_softc;
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static int
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pxa2x0_print(void *aux, const char *name)
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{
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struct pxa2x0_attach_args *sa = (struct pxa2x0_attach_args*)aux;
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if (sa->pxa_size)
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printf(" addr 0x%lx", sa->pxa_addr);
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if (sa->pxa_size > 1)
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printf("-0x%lx", sa->pxa_addr + sa->pxa_size - 1);
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if (sa->pxa_intr > 1)
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printf(" intr %d", sa->pxa_intr);
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if (sa->pxa_gpio != -1)
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printf(" gpio %d", sa->pxa_gpio);
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return (UNCONF);
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}
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int
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pxa2x0_match(struct device *parent, struct cfdata *match, void *aux)
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{
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return 1;
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}
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void
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pxa2x0_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pxa2x0_softc *sc = (struct pxa2x0_softc*)self;
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bus_space_tag_t iot;
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const char *which_registers; /* for panic message */
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#define FAIL(which) do { \
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which_registers=(which); goto abort; }while(/*CONSTCOND*/0)
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pxa2x0_softc = sc;
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sc->saip.sc_iot = iot = &pxa2x0_bs_tag;
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if (bus_space_map(iot,
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PXA2X0_INTCTL_BASE, PXA2X0_INTCTL_SIZE,
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0, &sc->saip.sc_ioh))
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FAIL("intc");
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/* Map the GPIO registers */
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if (bus_space_map(iot, PXA2X0_GPIO_BASE, PXA2X0_GPIO_SIZE,
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0, &sc->saip.sc_gpioh))
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FAIL("GPIO");
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/* Map the DMA controller registers */
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if (bus_space_map(iot, PXA2X0_DMAC_BASE, PXA2X0_DMAC_SIZE,
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0, &sc->saip.sc_dmach))
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FAIL("DMAC");
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/* Memory controller */
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if( bus_space_map(iot, PXA2X0_MEMCTL_BASE,
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PXA2X0_MEMCTL_SIZE, 0, &sc->sc_memctl_ioh) )
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FAIL("MEMC");
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/* Clock manager */
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if( bus_space_map(iot, PXA2X0_CLKMAN_BASE,
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PXA2X0_CLKMAN_SIZE, 0, &sc->sc_clkman_ioh) )
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FAIL("CLK");
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/* Real time clock */
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if( bus_space_map(iot, PXA2X0_RTC_BASE,
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PXA2X0_RTC_SIZE, 0, &sc->sc_rtc_ioh) )
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FAIL("RTC");
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#if 1
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/* This takes 2 secs at most. */
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{
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int cpuclock;
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cpuclock = pxa2x0_measure_cpuclock( sc ) / 1000;
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printf( " CPU clock = %d.%03d MHz", cpuclock/1000, cpuclock%1000 );
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}
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#endif
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printf("\n");
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pxa2x0_set_intcbase(sc->saip.sc_ioh);
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pxa2x0_intr_init();
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/*
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* Attach devices.
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*/
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config_search(pxa2x0_search, self, NULL);
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return;
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abort:
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panic("%s: unable to map %s registers\n",
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self->dv_xname, which_registers);
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#undef FAIL
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}
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int
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pxa2x0_search(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct pxa2x0_softc *sc = (struct pxa2x0_softc *)parent;
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struct pxa2x0_attach_args aa;
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aa.pxa_sc = sc;
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aa.pxa_iot = sc->saip.sc_iot;
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aa.pxa_addr = cf->cf_loc[PXAIPCF_ADDR];
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aa.pxa_size = cf->cf_loc[PXAIPCF_SIZE];
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aa.pxa_index = cf->cf_loc[PXAIPCF_INDEX];
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aa.pxa_sa.sa_membase = 0;
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aa.pxa_sa.sa_memsize = 0;
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aa.pxa_intr = cf->cf_loc[PXAIPCF_INTR];
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aa.pxa_gpio = cf->cf_loc[PXAIPCF_GPIO];
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if (config_match(parent, cf, &aa))
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config_attach(parent, cf, &aa, pxa2x0_print);
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return 0;
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}
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static inline uint32_t
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read_clock_counter(void)
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{
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uint32_t x;
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__asm __volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (x) );
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return x;
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}
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int
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pxa2x0_measure_cpuclock( struct pxa2x0_softc *sc )
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{
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uint32_t rtc0, rtc1, start, end;
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uint32_t pmcr_save;
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bus_space_tag_t iot = sc->saip.sc_iot;
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bus_space_handle_t rtc_ioh = sc->sc_rtc_ioh;
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int irq = disable_interrupts(I32_bit|F32_bit);
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__asm __volatile( "mrc p14, 0, %0, c0, c0, 0" : "=r" (pmcr_save) );
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/* Enable clock counter */
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__asm __volatile( "mcr p14, 0, %0, c0, c0, 0" : : "r" (0x0001) );
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rtc0 = bus_space_read_4( iot, rtc_ioh, RTC_RCNR );
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/* Wait for next second starts */
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while( (rtc1 = bus_space_read_4( iot, rtc_ioh, RTC_RCNR )) == rtc0 )
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;
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start = read_clock_counter();
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while( rtc1 == bus_space_read_4( iot, rtc_ioh, RTC_RCNR ) )
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; /* Wait for 1sec */
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end = read_clock_counter();
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__asm __volatile( "mcr p14, 0, %0, c0, c0, 0" : : "r" (pmcr_save) );
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restore_interrupts(irq);
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return end - start;
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}
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void
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pxa2x0_turbo_mode( int f )
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{
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__asm __volatile("mcr p14, 0, %0, c6, c0, 0" : : "r" (f));
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}
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@ -0,0 +1,103 @@
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/* $NetBSD: pxa2x0_a4x_io.S,v 1.1 2002/10/19 19:31:39 bsh Exp $ */
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/*
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* Copyright (c) 2002 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
|
||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* There are simple bus space functions for IO registers mapped at
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* 32-bit aligned positions. offset is multiplied by 4.
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*/
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#include <machine/asm.h>
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/*
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* bus_space I/O functions with offset*4
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*/
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/*
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* read single
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*/
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ENTRY(a4x_bs_r_1)
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ldrb r0, [r1, r2, LSL #2]
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mov pc, lr
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ENTRY(a4x_bs_r_2)
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mov r2, r2, LSL #2
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ldrh r0, [r1, r2]
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mov pc, lr
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ENTRY(a4x_bs_r_4)
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ldr r0, [r1, r2, LSL #2]
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mov pc, lr
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/*
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* write single
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*/
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ENTRY(a4x_bs_w_1)
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strb r3, [r1, r2, LSL #2]
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mov pc, lr
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ENTRY(a4x_bs_w_2)
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mov r2, r2, LSL #2
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strh r3, [r1, r2]
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mov pc, lr
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ENTRY(a4x_bs_w_4)
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str r3, [r1, r2, LSL #2]
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mov pc, lr
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/*
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* read multiple
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*/
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ENTRY(a4x_bs_rm_1)
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mov r2, r2, LSL #2
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b generic_bs_rm_1
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ENTRY(a4x_bs_rm_2)
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mov r2, r2, LSL #2
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b generic_armv4_bs_rm_2
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/*
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* write multiple
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*/
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ENTRY(a4x_bs_wm_1)
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mov r2, r2, LSL #2
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b generic_bs_wm_1
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ENTRY(a4x_bs_wm_2)
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mov r2, r2, LSL #2
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b generic_armv4_bs_wm_2
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@ -0,0 +1,133 @@
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/* $NetBSD: pxa2x0_a4x_space.c,v 1.1 2002/10/19 19:31:39 bsh Exp $ */
|
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|
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/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
* Written by Hiroyuki Bessho for Genetec Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
|
||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
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/*
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* Bus space tag for 8/16-bit devices on 32-bit bus.
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* all registers are located at the address of multiple of 4.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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/* Prototypes for all the bus_space structure functions */
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bs_protos(pxa2x0);
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bs_protos(a4x);
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bs_protos(generic);
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bs_protos(generic_armv4);
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bs_protos(bs_notimpl);
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|
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struct bus_space pxa2x0_a4x_bs_tag = {
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||||
/* cookie */
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||||
(void *) 0,
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||||
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||||
/* mapping/unmapping */
|
||||
pxa2x0_bs_map,
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||||
pxa2x0_bs_unmap,
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||||
pxa2x0_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
pxa2x0_bs_alloc, /* not implemented */
|
||||
pxa2x0_bs_free, /* not implemented */
|
||||
|
||||
/* get kernel virtual address */
|
||||
pxa2x0_bs_vaddr,
|
||||
|
||||
/* mmap */
|
||||
bs_notimpl_bs_mmap,
|
||||
|
||||
/* barrier */
|
||||
pxa2x0_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
a4x_bs_r_1,
|
||||
a4x_bs_r_2,
|
||||
a4x_bs_r_4,
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
a4x_bs_rm_1,
|
||||
a4x_bs_rm_2,
|
||||
bs_notimpl_bs_rm_4,
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
bs_notimpl_bs_rr_1,
|
||||
bs_notimpl_bs_rr_2,
|
||||
bs_notimpl_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
a4x_bs_w_1,
|
||||
a4x_bs_w_2,
|
||||
a4x_bs_w_4,
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
a4x_bs_wm_1,
|
||||
a4x_bs_wm_2,
|
||||
bs_notimpl_bs_wm_4,
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
bs_notimpl_bs_wr_1,
|
||||
bs_notimpl_bs_wr_2,
|
||||
bs_notimpl_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_bs_sr_1,
|
||||
bs_notimpl_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_bs_c_1,
|
||||
bs_notimpl_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/* $NetBSD: pxa2x0_dma.c,v 1.1 2002/10/19 19:31:39 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
* Written by Hiroyuki Bessho for Genetec Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
|
||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* bus dma tag for PXA2[15]0 processor.
|
||||
* (Currently used only for LCD frame buffer)
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/mbuf.h>
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#define _ARM32_BUS_DMA_PRIVATE
|
||||
#include <machine/bus.h>
|
||||
|
||||
struct arm32_bus_dma_tag pxa2x0_bus_dma_tag = {
|
||||
0,
|
||||
0,
|
||||
_bus_dmamap_create,
|
||||
_bus_dmamap_destroy,
|
||||
_bus_dmamap_load,
|
||||
_bus_dmamap_load_mbuf,
|
||||
_bus_dmamap_load_uio,
|
||||
_bus_dmamap_load_raw,
|
||||
_bus_dmamap_unload,
|
||||
_bus_dmamap_sync,
|
||||
NULL, /* sync_post */
|
||||
_bus_dmamem_alloc,
|
||||
_bus_dmamem_free,
|
||||
_bus_dmamem_map,
|
||||
_bus_dmamem_unmap,
|
||||
_bus_dmamem_mmap
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
/* $NetBSD: pxa2x0_intr.c,v 1.1 2002/10/19 19:31:39 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
* Written by Hiroyuki Bessho for Genetec Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
|
||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* IRQ handler for the Intel PXA2X0 processor.
|
||||
* It has integrated interrupt controller.
|
||||
*/
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <uvm/uvm_extern.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/intr.h>
|
||||
#include <arm/cpufunc.h>
|
||||
|
||||
#include <arm/xscale/pxa2x0reg.h>
|
||||
#include <arm/xscale/pxa2x0var.h>
|
||||
#include <arm/sa11x0/sa11x0_var.h>
|
||||
#include <arm/xscale/pxa2x0_intr.h>
|
||||
|
||||
/*
|
||||
* interrupt dispatch table.
|
||||
*/
|
||||
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
|
||||
struct intrhand {
|
||||
TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
|
||||
int (*ih_func)(void *); /* handler */
|
||||
void *ih_arg; /* arg for handler */
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct {
|
||||
#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
|
||||
TAILQ_HEAD(,intrhand) list;
|
||||
#else
|
||||
pxa2x0_irq_handler_t func;
|
||||
#endif
|
||||
void *cookie; /* NULL for stackframe */
|
||||
/* struct evbnt ev; */
|
||||
} handler[ICU_LEN];
|
||||
|
||||
__volatile int softint_pending;
|
||||
|
||||
__volatile int current_spl_level;
|
||||
__volatile int intr_mask;
|
||||
/* interrupt masks for each level */
|
||||
int pxa2x0_imask[NIPL];
|
||||
static int extirq_level[ICU_LEN];
|
||||
|
||||
int current_intr_depth;
|
||||
|
||||
static __inline void
|
||||
__raise(int ipl)
|
||||
{
|
||||
if( current_spl_level < ipl ){
|
||||
pxa2x0_setipl(ipl);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Map a software interrupt queue to an interrupt priority level.
|
||||
*/
|
||||
static const int si_to_ipl[SI_NQUEUES] = {
|
||||
IPL_SOFT, /* SI_SOFT */
|
||||
IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
|
||||
IPL_SOFTNET, /* SI_SOFTNET */
|
||||
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
|
||||
};
|
||||
|
||||
/*
|
||||
* called from irq_entry.
|
||||
*/
|
||||
void
|
||||
pxa2x0_irq_handler(struct clockframe *frame)
|
||||
{
|
||||
uint32_t irqbits;
|
||||
int irqno;
|
||||
int saved_spl_level;
|
||||
|
||||
++current_intr_depth;
|
||||
saved_spl_level = current_spl_level;
|
||||
|
||||
/* get pending IRQs */
|
||||
irqbits = read_icu(SAIPIC_IP);
|
||||
|
||||
while( (irqno = find_first_bit(irqbits)) >= 0 ){
|
||||
/* XXX: Shuould we handle IRQs in priority order? */
|
||||
|
||||
/* raise spl to stop interrupts of lower priorities */
|
||||
if( saved_spl_level < extirq_level[irqno] )
|
||||
pxa2x0_setipl(extirq_level[irqno]);
|
||||
|
||||
#ifdef notyet
|
||||
/* Enable interrupt */
|
||||
#endif
|
||||
#ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
|
||||
(* handler[irqno].func)(
|
||||
handler[irqno].cookie == 0
|
||||
? frame : handler[irqno].cookie );
|
||||
#else
|
||||
/* process all handlers for this interrupt.
|
||||
XXX not yet */
|
||||
#endif
|
||||
|
||||
#ifdef notyet
|
||||
/* Disable interrupt */
|
||||
#endif
|
||||
|
||||
irqbits &= ~(1<<irqno);
|
||||
}
|
||||
|
||||
/* restore spl to that was when this interrupt happen */
|
||||
pxa2x0_setipl(saved_spl_level);
|
||||
|
||||
if( softint_pending & intr_mask )
|
||||
pxa2x0_do_pending();
|
||||
|
||||
--current_intr_depth;
|
||||
}
|
||||
|
||||
static int
|
||||
stray_interrupt( void *cookie )
|
||||
{
|
||||
int irqno = (int)cookie;
|
||||
printf( "stray interrupt %d\n", irqno );
|
||||
|
||||
if( PXA2X0_IRQ_MIN <= irqno && irqno < ICU_LEN ){
|
||||
int save = disable_interrupts(I32_bit);
|
||||
write_icu( SAIPIC_MR,
|
||||
read_icu(SAIPIC_MR) & ~(1U<<irqno) );
|
||||
restore_interrupts(save);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Mask Handling
|
||||
*/
|
||||
|
||||
void
|
||||
pxa2x0_update_intr_masks( int irqno, int level )
|
||||
{
|
||||
int mask = 1U<<irqno;
|
||||
int psw = disable_interrupts(I32_bit);
|
||||
int i;
|
||||
|
||||
|
||||
for( i=IPL_BIO; i < level; ++i )
|
||||
pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */
|
||||
for( ; i < NIPL-1; ++i )
|
||||
pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */
|
||||
|
||||
/*
|
||||
* Enforce a heirarchy that gives "slow" device (or devices with
|
||||
* limited input buffer space/"real-time" requirements) a better
|
||||
* chance at not dropping data.
|
||||
*/
|
||||
pxa2x0_imask[IPL_BIO] &= pxa2x0_imask[IPL_SOFTNET];
|
||||
pxa2x0_imask[IPL_NET] &= pxa2x0_imask[IPL_BIO];
|
||||
pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_NET];
|
||||
pxa2x0_imask[IPL_TTY] &= pxa2x0_imask[IPL_SOFTSERIAL];
|
||||
|
||||
/*
|
||||
* splvm() blocks all interrupts that use the kernel memory
|
||||
* allocation facilities.
|
||||
*/
|
||||
pxa2x0_imask[IPL_IMP] &= pxa2x0_imask[IPL_TTY];
|
||||
|
||||
/*
|
||||
* Audio devices are not allowed to perform memory allocation
|
||||
* in their interrupt routines, and they have fairly "real-time"
|
||||
* requirements, so give them a high interrupt priority.
|
||||
*/
|
||||
pxa2x0_imask[IPL_AUDIO] &= pxa2x0_imask[IPL_IMP];
|
||||
|
||||
/*
|
||||
* splclock() must block anything that uses the scheduler.
|
||||
*/
|
||||
pxa2x0_imask[IPL_CLOCK] &= pxa2x0_imask[IPL_AUDIO];
|
||||
|
||||
/*
|
||||
* splhigh() must block "everything".
|
||||
*/
|
||||
pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_STATCLOCK];
|
||||
|
||||
/*
|
||||
* XXX We need serial drivers to run at the absolute highest priority
|
||||
* in order to avoid overruns, so serial > high.
|
||||
*/
|
||||
pxa2x0_imask[IPL_SERIAL] &= pxa2x0_imask[IPL_HIGH];
|
||||
|
||||
write_icu( SAIPIC_MR, pxa2x0_imask[current_spl_level] );
|
||||
|
||||
restore_interrupts(psw);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
init_interrupt_masks(void)
|
||||
{
|
||||
int i;
|
||||
pxa2x0_imask[IPL_NONE] = 0xffffffff;
|
||||
|
||||
for( i = IPL_BIO; i < NIPL; ++i )
|
||||
pxa2x0_imask[i] = 0;
|
||||
|
||||
/*
|
||||
* Initialize the soft interrupt masks to block themselves.
|
||||
*/
|
||||
pxa2x0_imask[IPL_SOFT] = ~SI_TO_IRQBIT(SI_SOFT);
|
||||
pxa2x0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK);
|
||||
pxa2x0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET);
|
||||
pxa2x0_imask[IPL_SOFTSERIAL] = ~SI_TO_IRQBIT(SI_SOFTSERIAL);
|
||||
|
||||
/*
|
||||
* splsoftclock() is the only interface that users of the
|
||||
* generic software interrupt facility have to block their
|
||||
* soft intrs, so splsoftclock() must also block IPL_SOFT.
|
||||
*/
|
||||
pxa2x0_imask[IPL_SOFTCLOCK] &= pxa2x0_imask[IPL_SOFT];
|
||||
|
||||
/*
|
||||
* splsoftnet() must also block splsoftclock(), since we don't
|
||||
* want timer-driven network events to occur while we're
|
||||
* processing incoming packets.
|
||||
*/
|
||||
pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTCLOCK];
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
pxa2x0_do_pending(void)
|
||||
{
|
||||
static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
|
||||
int oldirqstate, spl_save;
|
||||
|
||||
if (__cpu_simple_lock_try(&processing) == 0)
|
||||
return;
|
||||
|
||||
spl_save = current_spl_level;
|
||||
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
|
||||
#if 1
|
||||
#define DO_SOFTINT(si,ipl) \
|
||||
if ((softint_pending & intr_mask) & SI_TO_IRQBIT(si)) { \
|
||||
softint_pending &= ~SI_TO_IRQBIT(si); \
|
||||
__raise(ipl); \
|
||||
restore_interrupts(oldirqstate); \
|
||||
softintr_dispatch(si); \
|
||||
oldirqstate = disable_interrupts(I32_bit); \
|
||||
pxa2x0_setipl(spl_save); \
|
||||
}
|
||||
|
||||
do {
|
||||
DO_SOFTINT(SI_SOFTSERIAL,IPL_SOFTSERIAL);
|
||||
DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET);
|
||||
DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK);
|
||||
DO_SOFTINT(SI_SOFT, IPL_SOFT);
|
||||
} while( softint_pending & intr_mask );
|
||||
#else
|
||||
while( (si = find_first_bit(softint_pending & intr_mask)) >= 0 ){
|
||||
softint_pending &= ~SI_TO_IRQBIT(si);
|
||||
__raise(si_to_ipl(si));
|
||||
restore_interrupts(oldirqstate);
|
||||
softintr_dispatch(si);
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
pxa2x0_setipl(spl_save);
|
||||
}
|
||||
#endif
|
||||
|
||||
__cpu_simple_unlock(&processing);
|
||||
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
|
||||
|
||||
#undef splx
|
||||
void
|
||||
splx(int ipl)
|
||||
{
|
||||
pxa2x0_splx(ipl);
|
||||
}
|
||||
|
||||
#undef _splraise
|
||||
int
|
||||
_splraise(int ipl)
|
||||
{
|
||||
return pxa2x0_splraise(ipl);
|
||||
}
|
||||
|
||||
#undef _spllower
|
||||
int
|
||||
_spllower(int ipl)
|
||||
{
|
||||
return pxa2x0_spllower(ipl);
|
||||
}
|
||||
|
||||
#undef _setsoftintr
|
||||
void
|
||||
_setsoftintr(int si)
|
||||
{
|
||||
return pxa2x0_setsoftintr(si);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Initialize interrupt dispatcher.
|
||||
*/
|
||||
void
|
||||
pxa2x0_intr_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for( i=0; i < sizeof handler / sizeof handler[0]; ++i ){
|
||||
handler[i].func = stray_interrupt;
|
||||
handler[i].cookie = (void *)(i);
|
||||
extirq_level[i] = IPL_SERIAL;
|
||||
}
|
||||
|
||||
init_interrupt_masks();
|
||||
|
||||
_splraise(IPL_SERIAL);
|
||||
enable_interrupts(I32_bit);
|
||||
}
|
||||
|
||||
void
|
||||
pxa2x0_set_intcbase( vaddr_t addr )
|
||||
{
|
||||
pxaic_base = addr;
|
||||
}
|
||||
|
||||
void *
|
||||
pxa2x0_intr_establish(int irqno, int level,
|
||||
int (*func)(void *), void *cookie)
|
||||
{
|
||||
int psw;
|
||||
|
||||
if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN )
|
||||
panic("intr_establish: bogus irq number %d", irqno);
|
||||
|
||||
psw = disable_interrupts(I32_bit);
|
||||
|
||||
handler[irqno].cookie = cookie;
|
||||
handler[irqno].func = func;
|
||||
extirq_level[irqno] = level;
|
||||
pxa2x0_update_intr_masks( irqno, level );
|
||||
|
||||
intr_mask = pxa2x0_imask[current_spl_level];
|
||||
|
||||
restore_interrupts(psw);
|
||||
|
||||
return ( &handler[irqno] );
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Glue for drivers of sa11x0 compatible integrated logics.
|
||||
*/
|
||||
void *
|
||||
sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
|
||||
int (*ih_fun)(void *), void *ih_arg)
|
||||
{
|
||||
return pxa2x0_intr_establish(irq,level,ih_fun,ih_arg);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/* $NetBSD: pxa2x0_intr.h,v 1.1 2002/10/19 19:31:39 bsh Exp $ */
|
||||
|
||||
/* Derived from i80321_intr.h */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PXA2X0_INTR_H_
|
||||
#define _PXA2X0_INTR_H_
|
||||
|
||||
#include <arm/cpu.h>
|
||||
#include <arm/armreg.h>
|
||||
#include <arm/cpufunc.h>
|
||||
#include <machine/atomic.h>
|
||||
#include <machine/intr.h>
|
||||
#include <arm/softintr.h>
|
||||
|
||||
#include <arm/xscale/pxa2x0reg.h>
|
||||
|
||||
vaddr_t pxaic_base; /* Shared with pxa2x0_irq.S */
|
||||
#define read_icu(offset) (*(volatile uint32_t *)(pxaic_base+(offset)))
|
||||
#define write_icu(offset,value) \
|
||||
(*(volatile uint32_t *)(pxaic_base+(offset))=(value))
|
||||
|
||||
extern __volatile int current_spl_level;
|
||||
extern __volatile int intr_mask;
|
||||
extern __volatile int softint_pending;
|
||||
extern int pxa2x0_imask[];
|
||||
void pxa2x0_do_pending(void);
|
||||
|
||||
/*
|
||||
* Cotulla's integrated ICU doesn't have IRQ0..7, so
|
||||
* we map software interrupts to bit 0..3
|
||||
*/
|
||||
#define SI_TO_IRQBIT(si) (1U<<(si))
|
||||
|
||||
|
||||
static __inline void
|
||||
pxa2x0_setipl(int new)
|
||||
{
|
||||
current_spl_level = new;
|
||||
intr_mask = pxa2x0_imask[current_spl_level];
|
||||
write_icu( SAIPIC_MR, intr_mask );
|
||||
}
|
||||
|
||||
|
||||
static __inline void
|
||||
pxa2x0_splx(int new)
|
||||
{
|
||||
int psw;
|
||||
|
||||
psw = disable_interrupts(I32_bit);
|
||||
pxa2x0_setipl(new);
|
||||
restore_interrupts(psw);
|
||||
|
||||
/* If there are software interrupts to process, do it. */
|
||||
if (softint_pending & intr_mask)
|
||||
pxa2x0_do_pending();
|
||||
}
|
||||
|
||||
|
||||
static __inline int
|
||||
pxa2x0_splraise(int ipl)
|
||||
{
|
||||
int old, psw;
|
||||
|
||||
old = current_spl_level;
|
||||
if( ipl > current_spl_level ){
|
||||
psw = disable_interrupts(I32_bit);
|
||||
pxa2x0_setipl(ipl);
|
||||
restore_interrupts(psw);
|
||||
}
|
||||
|
||||
return (old);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pxa2x0_spllower(int ipl)
|
||||
{
|
||||
int old = current_spl_level;
|
||||
int psw = disable_interrupts(I32_bit);
|
||||
pxa2x0_splx(ipl);
|
||||
restore_interrupts(psw);
|
||||
return(old);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
pxa2x0_setsoftintr(int si)
|
||||
{
|
||||
atomic_set_bit( (u_int *)&softint_pending, SI_TO_IRQBIT(si) );
|
||||
|
||||
/* Process unmasked pending soft interrupts. */
|
||||
if ( softint_pending & intr_mask )
|
||||
pxa2x0_do_pending();
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* An useful function for interrupt handlers.
|
||||
* XXX: This shouldn't be here.
|
||||
*/
|
||||
static __inline int
|
||||
find_first_bit( uint32_t bits )
|
||||
{
|
||||
int count;
|
||||
|
||||
/* since CLZ is available only on ARMv5, this isn't portable
|
||||
* to all ARM CPUs. This file is for PXA2[15]0 processor.
|
||||
*/
|
||||
asm( "clz %0, %1" : "=r" (count) : "r" (bits) );
|
||||
return 31-count;
|
||||
}
|
||||
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
void _setsoftintr(int);
|
||||
|
||||
#if !defined(EVBARM_SPL_NOINLINE)
|
||||
|
||||
#define splx(new) pxa2x0_splx(new)
|
||||
#define _spllower(ipl) pxa2x0_spllower(ipl)
|
||||
#define _splraise(ipl) pxa2x0_splraise(ipl)
|
||||
#define _setsoftintr(si) pxa2x0_setsoftintr(si)
|
||||
|
||||
#endif /* !EVBARM_SPL_NOINTR */
|
||||
|
||||
#endif _PXA2X0_INTR_H_
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/* $NetBSD: pxa2x0_irq.S,v 1.1 2002/10/19 19:31:40 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* This code is derived from i80200_irq.S by Jason R. Thorpe.
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 2002 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "assym.h"
|
||||
|
||||
#include <machine/asm.h>
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/frame.h>
|
||||
|
||||
/*
|
||||
* irq_entry:
|
||||
* Main entry point for the IRQ vector.
|
||||
*/
|
||||
|
||||
.text
|
||||
.align 0
|
||||
Lastpending:
|
||||
.word _C_LABEL(astpending)
|
||||
|
||||
ASENTRY_NP(irq_entry)
|
||||
sub lr, lr, #0x00000004 /* Adjust the lr */
|
||||
|
||||
PUSHFRAMEINSVC /* Push an interrupt frame */
|
||||
|
||||
mov r0, sp
|
||||
bl _C_LABEL(pxa2x0_irq_handler)
|
||||
1:
|
||||
|
||||
/*
|
||||
* If we're returning to user mode, check for pending ASTs.
|
||||
*/
|
||||
ldr r0, [sp] /* Get the SPSR from stack */
|
||||
and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the IRQ */
|
||||
teq r0, #(PSR_USR32_MODE)
|
||||
bne Lirqout /* Nope, get out now */
|
||||
|
||||
Lastloop:
|
||||
ldr r0, Lastpending /* Do we have an AST pending? */
|
||||
ldr r1, [r0]
|
||||
teq r1, #0x00000000
|
||||
beq Lirqout /* Nope, get out now */
|
||||
|
||||
mov r1, #0x00000000
|
||||
str r1, [r0] /* Clear astpending */
|
||||
|
||||
mrs r4, cpsr_all /* save CPSR */
|
||||
bic r0, r4, #(I32_bit) /* Enable IRQs */
|
||||
msr cpsr_all, r0
|
||||
|
||||
mov r0, sp
|
||||
bl _C_LABEL(ast) /* ast(frame) */
|
||||
|
||||
msr cpsr_all, r4 /* Disable IRQs */
|
||||
b Lastloop /* Check for more ASTs */
|
||||
|
||||
Lirqout:
|
||||
PULLFRAMEFROMSVCANDEXIT
|
||||
movs pc, lr /* Exit */
|
||||
|
||||
.bss
|
||||
.align 0
|
||||
|
||||
.global _C_LABEL(astpending)
|
||||
_C_LABEL(astpending):
|
||||
.word 0
|
||||
|
||||
/*
|
||||
* XXX Provide intrnames/intrcnt for legacy code, but
|
||||
* don't actually use them.
|
||||
*/
|
||||
|
||||
.global _C_LABEL(intrnames), _C_LABEL(eintrnames)
|
||||
.global _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
|
||||
_C_LABEL(intrnames):
|
||||
_C_LABEL(eintrnames):
|
||||
|
||||
.global _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt)
|
||||
_C_LABEL(intrcnt):
|
||||
_C_LABEL(eintrcnt):
|
||||
|
|
@ -0,0 +1,749 @@
|
|||
/* $Id: pxa2x0_lcd.c,v 1.1 2002/10/19 19:31:40 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
* Written by Hiroyuki Bessho for Genetec Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
|
||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Support PXA2[15]0's integrated LCD controller.
|
||||
*/
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/uio.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/kernel.h> /* for cold */
|
||||
|
||||
#include <dev/cons.h>
|
||||
#include <dev/wscons/wsconsio.h>
|
||||
#include <dev/wscons/wsdisplayvar.h>
|
||||
#include <dev/wscons/wscons_callbacks.h>
|
||||
#include <dev/rasops/rasops.h>
|
||||
#include <dev/wsfont/wsfont.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/cpu.h>
|
||||
#include <arm/cpufunc.h>
|
||||
|
||||
#include <arm/xscale/pxa2x0var.h>
|
||||
#include <arm/xscale/pxa2x0reg.h>
|
||||
#include <arm/xscale/pxa2x0_lcd.h>
|
||||
|
||||
#include "wsdisplay.h"
|
||||
|
||||
int lcdintr(void *);
|
||||
|
||||
void
|
||||
pxa2x0_lcd_geometry( struct pxa2x0_lcd_softc *sc,
|
||||
const struct lcd_panel_geometry *info )
|
||||
{
|
||||
int lines;
|
||||
bus_space_tag_t iot = sc->iot;
|
||||
bus_space_handle_t ioh = sc->ioh;
|
||||
uint32_t ccr0;
|
||||
|
||||
sc->geometry = info;
|
||||
|
||||
ccr0 = LCCR0_IMASK;
|
||||
if( info->panel_info & LCDPANEL_ACTIVE )
|
||||
ccr0 |= LCCR0_PAS; /* passive mode */
|
||||
if( (info->panel_info & (LCDPANEL_DUAL|LCDPANEL_ACTIVE))
|
||||
== LCDPANEL_DUAL )
|
||||
ccr0 |= LCCR0_SDS; /* dual panel */
|
||||
if( info->panel_info & LCDPANEL_MONOCHROME )
|
||||
ccr0 |= LCCR0_CMS;
|
||||
bus_space_write_4( iot, ioh, LCDC_LCCR0, ccr0 );
|
||||
|
||||
bus_space_write_4( iot, ioh, LCDC_LCCR1,
|
||||
(info->panel_width-1)
|
||||
| ((info->hsync_pulse_width-1)<<10)
|
||||
| ((info->end_line_wait-1)<<16)
|
||||
| ((info->beg_line_wait-1)<<24) );
|
||||
|
||||
if( info->panel_info & LCDPANEL_DUAL )
|
||||
lines = info->panel_height/2 + info->extra_lines;
|
||||
else
|
||||
lines = info->panel_height + info->extra_lines;
|
||||
|
||||
bus_space_write_4( iot, ioh, LCDC_LCCR2,
|
||||
(lines-1)
|
||||
| (info->vsync_pulse_width<<10)
|
||||
| (info->end_frame_wait<<16)
|
||||
| (info->beg_frame_wait<<24) );
|
||||
|
||||
bus_space_write_4( iot, ioh, LCDC_LCCR3,
|
||||
(info->pixel_clock_div<<0)
|
||||
| (info->ac_bias << 8)
|
||||
| ((info->panel_info &
|
||||
(LCDPANEL_VSP|LCDPANEL_HSP|LCDPANEL_PCP|LCDPANEL_OEP))
|
||||
<<20)
|
||||
| ( 4 << 24 ) /* 16bpp */
|
||||
| ((info->panel_info & LCDPANEL_DPC) ? (1<<27) : 0)
|
||||
);
|
||||
}
|
||||
|
||||
void
|
||||
pxa2x0_lcd_attach_sub( struct pxa2x0_softc *parent,
|
||||
struct pxa2x0_lcd_softc *sc,
|
||||
const struct lcd_panel_geometry *geom )
|
||||
{
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
uint32_t tmp;
|
||||
int error;
|
||||
|
||||
|
||||
iot = parent->saip.sc_iot;
|
||||
|
||||
sc->n_screens = 0;
|
||||
LIST_INIT(&sc->screens);
|
||||
|
||||
/* map controller registers */
|
||||
error = bus_space_map( iot, PXA2X0_LCDC_BASE,
|
||||
PXA2X0_LCDC_SIZE, 0, &ioh );
|
||||
if( error ){
|
||||
printf( ": failed to map registers %d", error );
|
||||
return;
|
||||
}
|
||||
|
||||
sc->iot = iot;
|
||||
sc->ioh = ioh;
|
||||
sc->dma_tag = &pxa2x0_bus_dma_tag;
|
||||
|
||||
sc->ih = pxa2x0_intr_establish(17, IPL_BIO, lcdintr, sc);
|
||||
if (sc->ih == NULL)
|
||||
printf("%s: unable to establish interrupt at irq %d",
|
||||
sc->dev.dv_xname, 17);
|
||||
|
||||
/* Initialize LCD controller */
|
||||
|
||||
/* enable clock */
|
||||
tmp = bus_space_read_4( iot, parent->sc_clkman_ioh, CLKMAN_CKEN );
|
||||
bus_space_write_4( iot, parent->sc_clkman_ioh, CLKMAN_CKEN,
|
||||
tmp | (1U<<16) );
|
||||
|
||||
bus_space_write_4( iot, ioh, LCDC_LCCR0, LCCR0_IMASK );
|
||||
|
||||
/*
|
||||
* setup GP[77:58] for LCD
|
||||
*/
|
||||
{
|
||||
bus_space_handle_t gpioh = parent->saip.sc_gpioh;
|
||||
uint32_t gafr1, gafr2, gpdr1, gpdr2;
|
||||
int panelinfo = geom->panel_info;
|
||||
|
||||
gpdr1 = bus_space_read_4( iot, gpioh, GPIO_GPDR1 );
|
||||
gpdr2 = bus_space_read_4( iot, gpioh, GPIO_GPDR2 );
|
||||
gafr1 = bus_space_read_4( iot, gpioh, GPIO_GAFR1_U );
|
||||
gafr2 = bus_space_read_4( iot, gpioh, GPIO_GAFR2_L );
|
||||
|
||||
/* Always use L_DD[3:0], [FLP]CLK, ACBIAS */
|
||||
gafr1 = (gafr1 & ~(0xff<<20)) | (0xaa<<20);
|
||||
gafr2 = (gafr2 & ~(0xff<<20)) | (0xaa<<20);
|
||||
gpdr1 |= 0x0f<<26;
|
||||
gpdr2 |= 0x0f<<10;
|
||||
|
||||
if( (panelinfo & LCDPANEL_ACTIVE) ||
|
||||
((panelinfo & (LCDPANEL_MONOCHROME|LCDPANEL_DUAL))
|
||||
== LCDPANEL_DUAL ) ){
|
||||
/* active and color dual panel need L_DD[15:0] */
|
||||
gafr1 = (gafr1 & ~(0x0f<<28)) | (0x0a<<28);
|
||||
gafr2 = (gafr2 & ~0xfffff) | 0xaaaaa;
|
||||
gpdr1 |= 0x03<<30;
|
||||
gpdr2 |= 0x3ff;
|
||||
}
|
||||
else if( (panelinfo & LCDPANEL_DUAL) ||
|
||||
!(panelinfo & LCDPANEL_MONOCHROME ) ){
|
||||
/* dual or color need L_DD[7:0] */
|
||||
|
||||
gafr1 = (gafr1 & ~(0x0f<<28)) | (0x0a<<28);
|
||||
gafr2 = (gafr2 & ~0x0f) | 0x0a;
|
||||
gpdr1 |= 0x03<<30;
|
||||
gpdr2 |= 0x03;
|
||||
}
|
||||
|
||||
|
||||
bus_space_write_4( iot, gpioh, GPIO_GAFR1_U, gafr1 );
|
||||
bus_space_write_4( iot, gpioh, GPIO_GAFR2_L, gafr2 );
|
||||
bus_space_write_4( iot, gpioh, GPIO_GPDR1, gpdr1 );
|
||||
bus_space_write_4( iot, gpioh, GPIO_GPDR2, gpdr2 );
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
pxa2x0_lcd_geometry( sc, geom );
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
lcdintr(void *arg)
|
||||
{
|
||||
struct pxa2x0_lcd_softc *sc = arg;
|
||||
bus_space_tag_t iot = sc->iot;
|
||||
bus_space_handle_t ioh = sc->ioh;
|
||||
|
||||
static uint32_t status;
|
||||
|
||||
status = bus_space_read_4( iot, ioh, LCDC_LCSR );
|
||||
/* Clear stickey status bits */
|
||||
bus_space_write_4( iot, ioh, LCDC_LCSR, status );
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void
|
||||
pxa2x0_lcd_start_dma( struct pxa2x0_lcd_softc *sc,
|
||||
struct pxa2x0_lcd_screen *scr )
|
||||
{
|
||||
uint32_t tmp;
|
||||
bus_space_tag_t iot = sc->iot;
|
||||
bus_space_handle_t ioh = sc->ioh;
|
||||
int val, save;
|
||||
|
||||
save = disable_interrupts( I32_bit );
|
||||
|
||||
switch( scr->depth ){
|
||||
case 1: val = 0; break;
|
||||
case 2: val = 1; break;
|
||||
case 4: val = 2; break;
|
||||
case 8: val = 3; break;
|
||||
case 16: /* FALLTHROUGH */
|
||||
default:
|
||||
val = 4; break;
|
||||
}
|
||||
|
||||
tmp = bus_space_read_4( iot, ioh, LCDC_LCCR3 );
|
||||
bus_space_write_4( iot, ioh, LCDC_LCCR3,
|
||||
(tmp & ~LCCR3_BPP) | (val << LCCR3_BPP_SHIFT) );
|
||||
|
||||
bus_space_write_4( iot, ioh, LCDC_FDADR0,
|
||||
scr->depth == 16 ? scr->dma_desc_pa :
|
||||
scr->dma_desc_pa + 2 * sizeof (struct lcd_dma_descriptor) );
|
||||
bus_space_write_4( iot, ioh, LCDC_FDADR1,
|
||||
scr->dma_desc_pa + 1 * sizeof (struct lcd_dma_descriptor) );
|
||||
|
||||
/* clear status */
|
||||
bus_space_write_4( iot, ioh, LCDC_LCSR, 0 );
|
||||
|
||||
delay(1000); /* ??? */
|
||||
|
||||
/* Enable LCDC */
|
||||
tmp = bus_space_read_4( iot, ioh, LCDC_LCCR0 );
|
||||
/*tmp &= ~LCCR0_SFM;*/
|
||||
bus_space_write_4( iot, ioh, LCDC_LCCR0, tmp | LCCR0_ENB );
|
||||
|
||||
restore_interrupts( save );
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
pxa2x0_lcd_stop_dma( struct pxa2x0_lcd_softc *sc )
|
||||
{
|
||||
/* Stop LCD DMA after current frame */
|
||||
bus_space_write_4( sc->iot, sc->ioh, LCDC_LCCR0,
|
||||
LCCR0_DIS |
|
||||
bus_space_read_4( sc->iot, sc->ioh, LCDC_LCCR0 ) );
|
||||
|
||||
/* wait for disabling done.
|
||||
XXX: use interrupt. */
|
||||
while( LCCR0_ENB &
|
||||
bus_space_read_4( sc->iot, sc->ioh, LCDC_LCCR0 ) )
|
||||
;
|
||||
|
||||
bus_space_write_4( sc->iot, sc->ioh, LCDC_LCCR0,
|
||||
~LCCR0_DIS &
|
||||
bus_space_read_4( sc->iot, sc->ioh, LCDC_LCCR0 ) );
|
||||
}
|
||||
|
||||
#define _rgb(r,g,b) (((r)<<11) | ((g)<<5) | b)
|
||||
#define rgb(r,g,b) _rgb((r)>>1,g,(b)>>1)
|
||||
|
||||
#define L 0x1f /* low intensity */
|
||||
#define H 0x3f /* hight intensity */
|
||||
|
||||
static uint16_t basic_color_map[] = {
|
||||
rgb( 0, 0, 0), /* black */
|
||||
rgb( L, 0, 0), /* red */
|
||||
rgb( 0, L, 0), /* green */
|
||||
rgb( L, L, 0), /* brown */
|
||||
rgb( 0, 0, L), /* blue */
|
||||
rgb( L, 0, L), /* magenta */
|
||||
rgb( 0, L, L), /* cyan */
|
||||
_rgb(0x1c,0x38,0x1c), /* white */
|
||||
|
||||
rgb( L, L, L), /* black */
|
||||
rgb( H, 0, 0), /* red */
|
||||
rgb( 0, H, 0), /* green */
|
||||
rgb( H, H, 0), /* brown */
|
||||
rgb( 0, 0, H), /* blue */
|
||||
rgb( H, 0, H), /* magenta */
|
||||
rgb( 0, H, H), /* cyan */
|
||||
rgb( H, H, H)
|
||||
};
|
||||
|
||||
#undef H
|
||||
#undef L
|
||||
|
||||
static void
|
||||
init_pallet( uint16_t *buf, int depth )
|
||||
{
|
||||
int i;
|
||||
|
||||
/* convert RGB332 to RGB565 */
|
||||
switch( depth ){
|
||||
case 8:
|
||||
case 4:
|
||||
#if 0
|
||||
for( i=0; i <= 255; ++i ){
|
||||
buf[i] = ((9 * ((i>>5) & 0x07)) <<11) |
|
||||
((9 * ((i>>2) & 0x07)) << 5) |
|
||||
((21 * (i & 0x03))/2 );
|
||||
}
|
||||
#else
|
||||
memcpy( buf, basic_color_map, sizeof basic_color_map );
|
||||
for( i=16; i < (1<<depth); ++i )
|
||||
buf[i] = 0xffff;
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
}
|
||||
}
|
||||
|
||||
struct pxa2x0_lcd_screen *
|
||||
pxa2x0_lcd_new_screen( struct pxa2x0_lcd_softc *sc,
|
||||
int depth )
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = NULL;
|
||||
int width, height;
|
||||
bus_size_t size;
|
||||
int error, pallet_size;
|
||||
int busdma_flag = (cold ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
|
||||
struct lcd_dma_descriptor *desc;
|
||||
paddr_t buf_pa, desc_pa;
|
||||
|
||||
width = sc->geometry->panel_width;
|
||||
height = sc->geometry->panel_height;
|
||||
pallet_size = 0;
|
||||
|
||||
switch( depth ){
|
||||
case 1:
|
||||
case 2:
|
||||
case 4:
|
||||
case 8:
|
||||
pallet_size = (1<<depth) * sizeof (uint16_t);
|
||||
/* FALLTHROUGH */
|
||||
case 16:
|
||||
size = roundup(width,4)*depth/8 * height;
|
||||
break;
|
||||
default:
|
||||
printf( "%s: Unknown depth (%d)\n", sc->dev.dv_xname, depth );
|
||||
return NULL;
|
||||
}
|
||||
|
||||
scr = malloc( sizeof *scr, M_DEVBUF,
|
||||
M_ZERO | (cold ? M_NOWAIT : M_WAITOK) );
|
||||
|
||||
if( scr == NULL )
|
||||
return NULL;
|
||||
|
||||
scr->nsegs = 0;
|
||||
scr->depth = depth;
|
||||
scr->buf_size = size;
|
||||
scr->buf_va = NULL;
|
||||
size = roundup(size,16) + 3 * sizeof (struct lcd_dma_descriptor)
|
||||
+ pallet_size;
|
||||
|
||||
error = bus_dmamem_alloc( sc->dma_tag, size, 16, 0,
|
||||
scr->segs, 1, &(scr->nsegs), busdma_flag );
|
||||
|
||||
if( error || scr->nsegs != 1 ){
|
||||
/* XXX: Actually we can handle nsegs>1 case by means
|
||||
of multiple DMA descriptors for a panel. it will
|
||||
makes code here a bit hairly */
|
||||
goto bad;
|
||||
}
|
||||
|
||||
error = bus_dmamem_map( sc->dma_tag, scr->segs, scr->nsegs,
|
||||
size, (caddr_t *)&(scr->buf_va), busdma_flag | BUS_DMA_COHERENT );
|
||||
if( error )
|
||||
goto bad;
|
||||
|
||||
|
||||
memset( scr->buf_va, 0, scr->buf_size );
|
||||
|
||||
/* map memory for DMA */
|
||||
if( bus_dmamap_create( sc->dma_tag, 1024*1024*2, 1,
|
||||
1024*1024*2, 0, busdma_flag, &scr->dma ) )
|
||||
goto bad;
|
||||
error = bus_dmamap_load( sc->dma_tag, scr->dma,
|
||||
scr->buf_va, size, NULL, busdma_flag );
|
||||
if( error ){
|
||||
goto bad;
|
||||
}
|
||||
|
||||
buf_pa = scr->segs[0].ds_addr;
|
||||
desc_pa = buf_pa + roundup(size, NBPG) - 3*sizeof *desc;
|
||||
|
||||
/* make descriptors at the top of mapped memory */
|
||||
desc = (struct lcd_dma_descriptor *)(
|
||||
(caddr_t)(scr->buf_va) + roundup(size, NBPG) - 3*sizeof *desc);
|
||||
|
||||
desc[0].fdadr = desc_pa;
|
||||
desc[0].fsadr = buf_pa;
|
||||
desc[0].ldcmd = scr->buf_size;
|
||||
|
||||
if( pallet_size ){
|
||||
init_pallet( (uint16_t *)((char *)desc - pallet_size), depth );
|
||||
|
||||
desc[2].fdadr = desc_pa; /* chain to panel 0 */
|
||||
desc[2].fsadr = desc_pa - pallet_size;
|
||||
desc[2].ldcmd = pallet_size | LDCMD_PAL;
|
||||
}
|
||||
|
||||
if( sc->geometry->panel_info & LCDPANEL_DUAL ){
|
||||
/* Dual panel */
|
||||
desc[1].fdadr = desc_pa + sizeof *desc;
|
||||
desc[1].fsadr = buf_pa + scr->buf_size/2;
|
||||
desc[0].ldcmd = desc[1].ldcmd = scr->buf_size/2;
|
||||
|
||||
}
|
||||
|
||||
#if 0
|
||||
desc[0].ldcmd |= LDCMD_SOFINT;
|
||||
desc[1].ldcmd |= LDCMD_SOFINT;
|
||||
#endif
|
||||
|
||||
scr->dma_desc = desc;
|
||||
scr->dma_desc_pa = desc_pa;
|
||||
scr->map_size = size; /* used when unmap this. */
|
||||
|
||||
LIST_INSERT_HEAD( &(sc->screens), scr, link );
|
||||
sc->n_screens++;
|
||||
|
||||
return scr;
|
||||
|
||||
bad:
|
||||
if( scr ){
|
||||
if( scr->buf_va )
|
||||
bus_dmamem_unmap( sc->dma_tag, scr->buf_va, size );
|
||||
if( scr->nsegs )
|
||||
bus_dmamem_free( sc->dma_tag, scr->segs, scr->nsegs );
|
||||
free( scr, M_DEVBUF );
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
#if NWSDISPLAY > 0
|
||||
|
||||
/*
|
||||
* Initialize struct wsscreen_descr based on values calculated by
|
||||
* raster operation subsystem.
|
||||
*/
|
||||
int
|
||||
pxa2x0_lcd_setup_wsscreen(struct pxa2x0_wsscreen_descr *descr,
|
||||
const struct lcd_panel_geometry *geom,
|
||||
const char *fontname )
|
||||
{
|
||||
int width = geom->panel_width;
|
||||
int height = geom->panel_height;
|
||||
int cookie = -1;
|
||||
struct rasops_info rinfo;
|
||||
|
||||
memset( &rinfo, 0, sizeof rinfo );
|
||||
|
||||
if( fontname ){
|
||||
wsfont_init();
|
||||
cookie = wsfont_find( (char *)fontname, 0, 0, 0,
|
||||
WSDISPLAY_FONTORDER_L2R, WSDISPLAY_FONTORDER_L2R );
|
||||
if( cookie < 0 ||
|
||||
wsfont_lock(cookie, &rinfo.ri_font) )
|
||||
return -1;
|
||||
}
|
||||
else {
|
||||
/* let rasops_init() choose any font */
|
||||
}
|
||||
|
||||
/* let rasops_init calculate # of cols and rows in character */
|
||||
rinfo.ri_flg = 0;
|
||||
rinfo.ri_depth = descr->depth;
|
||||
rinfo.ri_bits = NULL;
|
||||
rinfo.ri_width = width;
|
||||
rinfo.ri_height = height;
|
||||
rinfo.ri_stride = width * rinfo.ri_depth / 8;
|
||||
rinfo.ri_wsfcookie = cookie;
|
||||
|
||||
rasops_init( &rinfo, 100, 100 );
|
||||
|
||||
descr->c.nrows = rinfo.ri_rows;
|
||||
descr->c.ncols = rinfo.ri_cols;
|
||||
descr->c.capabilities = rinfo.ri_caps;
|
||||
|
||||
return cookie;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pxa2x0_lcd_show_screen(void *v, void *cookie, int waitok,
|
||||
void (*cb)(void *, int, int), void *cbarg)
|
||||
{
|
||||
struct pxa2x0_lcd_softc *sc = v;
|
||||
struct pxa2x0_lcd_screen *scr = cookie, *old;
|
||||
|
||||
old = sc->active;
|
||||
if( old == scr )
|
||||
return 0;
|
||||
|
||||
if( old )
|
||||
pxa2x0_lcd_stop_dma( sc );
|
||||
|
||||
pxa2x0_lcd_start_dma( sc, scr );
|
||||
|
||||
sc->active = scr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
pxa2x0_lcd_alloc_screen(void *v, const struct wsscreen_descr *_type,
|
||||
void **cookiep, int *curxp, int *curyp, long *attrp)
|
||||
{
|
||||
struct pxa2x0_lcd_softc *sc = v;
|
||||
struct pxa2x0_lcd_screen *scr;
|
||||
struct pxa2x0_wsscreen_descr *type = (struct pxa2x0_wsscreen_descr *)_type;
|
||||
|
||||
scr = pxa2x0_lcd_new_screen( sc, type->depth );
|
||||
if( scr == NULL )
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* initialize raster operation for this screen.
|
||||
*/
|
||||
scr->rinfo.ri_flg = 0;
|
||||
scr->rinfo.ri_depth = type->depth;
|
||||
scr->rinfo.ri_bits = scr->buf_va;
|
||||
scr->rinfo.ri_width = sc->geometry->panel_width;
|
||||
scr->rinfo.ri_height = sc->geometry->panel_height;
|
||||
scr->rinfo.ri_stride = scr->rinfo.ri_width * scr->rinfo.ri_depth / 8;
|
||||
scr->rinfo.ri_wsfcookie = -1; /* XXX */
|
||||
|
||||
rasops_init( &scr->rinfo, type->c.nrows, type->c.ncols );
|
||||
|
||||
(* scr->rinfo.ri_ops.allocattr)(&scr->rinfo, 0, 0, 0, attrp );
|
||||
|
||||
*cookiep = scr;
|
||||
*curxp = 0;
|
||||
*curyp = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pxa2x0_lcd_free_screen(void *v, void *cookie)
|
||||
{
|
||||
struct pxa2x0_lcd_softc *sc = v;
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
LIST_REMOVE( scr, link );
|
||||
sc->n_screens--;
|
||||
if( scr == sc->active ){
|
||||
/* at first, we need to stop LCD DMA */
|
||||
sc->active = NULL;
|
||||
|
||||
printf( "lcd_free on active screen\n" );
|
||||
|
||||
pxa2x0_lcd_stop_dma(sc);
|
||||
}
|
||||
|
||||
if( scr->buf_va )
|
||||
bus_dmamem_unmap( sc->dma_tag, scr->buf_va, scr->map_size );
|
||||
|
||||
if( scr->nsegs > 0 )
|
||||
bus_dmamem_free( sc->dma_tag, scr->segs, scr->nsegs );
|
||||
|
||||
free( scr, M_DEVBUF );
|
||||
}
|
||||
|
||||
int
|
||||
pxa2x0_lcd_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p)
|
||||
{
|
||||
struct pxa2x0_lcd_softc *sc = v;
|
||||
struct wsdisplay_fbinfo *wsdisp_info;
|
||||
uint32_t ccr0;
|
||||
|
||||
switch (cmd) {
|
||||
case WSDISPLAYIO_GTYPE:
|
||||
*(u_int *)data = WSDISPLAY_TYPE_UNKNOWN; /* XXX */
|
||||
return 0;
|
||||
|
||||
case WSDISPLAYIO_GINFO:
|
||||
wsdisp_info = (struct wsdisplay_fbinfo *)data;
|
||||
|
||||
wsdisp_info->height = sc->geometry->panel_height;
|
||||
wsdisp_info->width = sc->geometry->panel_width;
|
||||
wsdisp_info->depth = 16; /* XXX */
|
||||
wsdisp_info->cmsize = 0;
|
||||
return 0;
|
||||
|
||||
case WSDISPLAYIO_GETCMAP:
|
||||
case WSDISPLAYIO_PUTCMAP:
|
||||
return EPASSTHROUGH; /* XXX Colormap */
|
||||
|
||||
case WSDISPLAYIO_SVIDEO:
|
||||
if( *(int *)data == WSDISPLAYIO_VIDEO_ON ){
|
||||
/* turn it on */
|
||||
}
|
||||
else {
|
||||
/* start LCD shutdown */
|
||||
/* sleep until interrupt */
|
||||
}
|
||||
return 0;
|
||||
|
||||
case WSDISPLAYIO_GVIDEO:
|
||||
ccr0 = bus_space_read_4( sc->iot, sc->ioh, LCDC_LCCR0 );
|
||||
*(u_int *)data = (ccr0 & (LCCR0_ENB|LCCR0_DIS)) == LCCR0_ENB ?
|
||||
WSDISPLAYIO_VIDEO_ON : WSDISPLAYIO_VIDEO_OFF;
|
||||
return 0;
|
||||
|
||||
|
||||
|
||||
case WSDISPLAYIO_GCURPOS:
|
||||
case WSDISPLAYIO_SCURPOS:
|
||||
case WSDISPLAYIO_GCURMAX:
|
||||
case WSDISPLAYIO_GCURSOR:
|
||||
case WSDISPLAYIO_SCURSOR:
|
||||
return EPASSTHROUGH; /* XXX */
|
||||
}
|
||||
|
||||
return EPASSTHROUGH;
|
||||
}
|
||||
|
||||
paddr_t
|
||||
pxa2x0_lcd_mmap(void *v, off_t offset, int prot)
|
||||
{
|
||||
struct pxa2x0_lcd_softc *sc = v;
|
||||
struct pxa2x0_lcd_screen *screen = sc->active; /* ??? */
|
||||
|
||||
if( screen == NULL )
|
||||
return -1;
|
||||
|
||||
return bus_dmamem_mmap( sc->dma_tag, screen->segs, screen->nsegs,
|
||||
offset, prot, BUS_DMA_WAITOK|BUS_DMA_COHERENT );
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
pxa2x0_lcd_cursor( void *cookie, int on, int row, int col )
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
(* scr->rinfo.ri_ops.cursor)( &scr->rinfo, on, row, col );
|
||||
}
|
||||
|
||||
static int
|
||||
pxa2x0_lcd_mapchar( void *cookie, int c, unsigned int *cp )
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
return (* scr->rinfo.ri_ops.mapchar)( &scr->rinfo, c, cp );
|
||||
}
|
||||
|
||||
static void
|
||||
pxa2x0_lcd_putchar( void *cookie, int row, int col, u_int uc, long attr )
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
(* scr->rinfo.ri_ops.putchar)( &scr->rinfo,
|
||||
row, col, uc, attr );
|
||||
}
|
||||
|
||||
static void
|
||||
pxa2x0_lcd_copycols( void *cookie, int row, int src, int dst, int num)
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
(* scr->rinfo.ri_ops.copycols)( &scr->rinfo,
|
||||
row, src, dst, num );
|
||||
}
|
||||
|
||||
static void
|
||||
pxa2x0_lcd_erasecols( void *cookie, int row, int col, int num, long attr)
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
(* scr->rinfo.ri_ops.erasecols)( &scr->rinfo,
|
||||
row, col, num, attr );
|
||||
}
|
||||
|
||||
static void
|
||||
pxa2x0_lcd_copyrows( void *cookie, int src, int dst, int num )
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
(* scr->rinfo.ri_ops.copyrows)( &scr->rinfo,
|
||||
src, dst, num );
|
||||
}
|
||||
|
||||
static void
|
||||
pxa2x0_lcd_eraserows( void *cookie, int row, int num, long attr )
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
(* scr->rinfo.ri_ops.eraserows)( &scr->rinfo,
|
||||
row, num, attr );
|
||||
}
|
||||
|
||||
static int
|
||||
pxa2x0_lcd_alloc_attr( void *cookie, int fg, int bg, int flg, long *attr)
|
||||
{
|
||||
struct pxa2x0_lcd_screen *scr = cookie;
|
||||
|
||||
return (* scr->rinfo.ri_ops.allocattr)( &scr->rinfo,
|
||||
fg, bg, flg, attr );
|
||||
}
|
||||
|
||||
|
||||
const struct wsdisplay_emulops pxa2x0_lcd_emulops = {
|
||||
pxa2x0_lcd_cursor,
|
||||
pxa2x0_lcd_mapchar,
|
||||
pxa2x0_lcd_putchar,
|
||||
pxa2x0_lcd_copycols,
|
||||
pxa2x0_lcd_erasecols,
|
||||
pxa2x0_lcd_copyrows,
|
||||
pxa2x0_lcd_eraserows,
|
||||
pxa2x0_lcd_alloc_attr
|
||||
};
|
||||
|
||||
#endif /* NWSDISPLAY > 0 */
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/* $NetBSD: pxa2x0_lcd.h,v 1.1 2002/10/19 19:31:40 bsh Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
* Written by Hiroyuki Bessho for Genetec Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
|
||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _ARM_XSCALE_PXA2X0_LCD_H
|
||||
#define _ARM_XSCALE_PXA2X0_LCD_H
|
||||
|
||||
#include <dev/rasops/rasops.h>
|
||||
#include <machine/bus.h>
|
||||
|
||||
/* LCD Contoroller */
|
||||
|
||||
struct lcd_dma_descriptor {
|
||||
uint32_t fdadr; /* next frame descriptor */
|
||||
uint32_t fsadr; /* frame start address */
|
||||
uint32_t fidr; /* frame ID */
|
||||
uint32_t ldcmd; /* DMA command */
|
||||
#define LDCMD_PAL (1U<<26) /* Pallet buffer */
|
||||
#define LDCMD_SOFINT (1U<<22) /* Start of Frame interrupt */
|
||||
#define LDCMD_EOFINT (1U<<21) /* End of Frame interrupt */
|
||||
};
|
||||
|
||||
|
||||
struct pxa2x0_lcd_screen {
|
||||
LIST_ENTRY(pxa2x0_lcd_screen) link;
|
||||
|
||||
/* Frame buffer */
|
||||
bus_dmamap_t dma;
|
||||
bus_dma_segment_t segs[1];
|
||||
int nsegs;
|
||||
size_t buf_size;
|
||||
size_t map_size;
|
||||
void *buf_va;
|
||||
int depth;
|
||||
|
||||
/* DMA frame descriptor */
|
||||
struct lcd_dma_descriptor *dma_desc;
|
||||
paddr_t dma_desc_pa;
|
||||
|
||||
/* rasterop */
|
||||
struct rasops_info rinfo;
|
||||
};
|
||||
|
||||
struct pxa2x0_lcd_softc {
|
||||
struct device dev;
|
||||
/* control register */
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
bus_dma_tag_t dma_tag;
|
||||
|
||||
const struct lcd_panel_geometry *geometry;
|
||||
|
||||
int n_screens;
|
||||
LIST_HEAD(, pxa2x0_lcd_screen) screens;
|
||||
struct pxa2x0_lcd_screen *active;
|
||||
void *ih; /* interrupt handler */
|
||||
};
|
||||
|
||||
void pxa2x0_lcd_attach_sub( struct pxa2x0_softc *,
|
||||
struct pxa2x0_lcd_softc *, const struct lcd_panel_geometry * );
|
||||
void pxa2x0_lcd_start_dma( struct pxa2x0_lcd_softc *, struct pxa2x0_lcd_screen * );
|
||||
|
||||
struct lcd_panel_geometry {
|
||||
short panel_width;
|
||||
short panel_height;
|
||||
short extra_lines;
|
||||
|
||||
short panel_info;
|
||||
#define LCDPANEL_VSP (1<<0) /* L_FCLK pin is active low */
|
||||
#define LCDPANEL_HSP (1<<1) /* L_LCLK pin is active low */
|
||||
#define LCDPANEL_PCP (1<<2) /* use L_PCLK falling edge */
|
||||
#define LCDPANEL_OEP (1<<3) /* L_BIAS pin is active low */
|
||||
#define LCDPANEL_DPC (1<<4) /* double pixel clock mode */
|
||||
|
||||
#define LCDPANEL_DUAL (1<<5) /* Dual or single */
|
||||
#define LCDPANEL_SINGLE 0
|
||||
#define LCDPANEL_ACTIVE (1<<6) /* Active or Passive */
|
||||
#define LCDPANEL_PASSIVE 0
|
||||
#define LCDPANEL_MONOCHROME (1<<7) /* depth=1 */
|
||||
|
||||
short pixel_clock_div; /* pixel clock divider */
|
||||
short ac_bias; /* AC bias pin frequency */
|
||||
|
||||
short hsync_pulse_width; /* Horizontao sync pulse width */
|
||||
short beg_line_wait; /* beginning of line wait (BLW) */
|
||||
short end_line_wait; /* end of line pxel wait (ELW) */
|
||||
|
||||
short vsync_pulse_width; /* vertical sync pulse width */
|
||||
short beg_frame_wait; /* beginning of frame wait (BFW) */
|
||||
short end_frame_wait; /* end of frame wait (EFW) */
|
||||
};
|
||||
|
||||
void pxa2x0_lcd_geometry( struct pxa2x0_lcd_softc *,
|
||||
const struct lcd_panel_geometry *);
|
||||
struct pxa2x0_lcd_screen *pxa2x0_lcd_new_screen(
|
||||
struct pxa2x0_lcd_softc *, int depth );
|
||||
|
||||
/*
|
||||
* we need bits-per-pixel value to configure wsdisplay screen
|
||||
*/
|
||||
struct pxa2x0_wsscreen_descr {
|
||||
struct wsscreen_descr c; /* standard descriptor */
|
||||
int depth; /* bits per pixel */
|
||||
};
|
||||
|
||||
int pxa2x0_lcd_setup_wsscreen(struct pxa2x0_wsscreen_descr *,
|
||||
const struct lcd_panel_geometry *, const char * );
|
||||
|
||||
int pxa2x0_lcd_show_screen(void *, void *, int, void (*)(void *, int, int), void *);
|
||||
int pxa2x0_lcd_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p);
|
||||
paddr_t pxa2x0_lcd_mmap(void *, off_t, int);
|
||||
int pxa2x0_lcd_alloc_screen(void *, const struct wsscreen_descr *,
|
||||
void **, int *, int *, long *);
|
||||
void pxa2x0_lcd_free_screen(void *, void *);
|
||||
|
||||
extern const struct wsdisplay_emulops pxa2x0_lcd_emulops;
|
||||
|
||||
#endif /* _ARM_XSCALE_PXA2X0_LCD_H */
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
/* $NetBSD: pxa2x0_space.c,v 1.1 2002/10/19 19:31:40 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
* Copyright (c) 1997 Causality Limited.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Ichiro FUKUHARA.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Mark Brinicombe.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* bus_space functions for Intel PXA2[51]0 application processor.
|
||||
* Derived from i80321_space.c.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
/* Prototypes for all the bus_space structure functions */
|
||||
bs_protos(pxa2x0);
|
||||
bs_protos(generic);
|
||||
bs_protos(generic_armv4);
|
||||
bs_protos(bs_notimpl);
|
||||
|
||||
struct bus_space pxa2x0_bs_tag = {
|
||||
/* cookie */
|
||||
(void *) 0,
|
||||
|
||||
/* mapping/unmapping */
|
||||
pxa2x0_bs_map,
|
||||
pxa2x0_bs_unmap,
|
||||
pxa2x0_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
pxa2x0_bs_alloc, /* not implemented */
|
||||
pxa2x0_bs_free, /* not implemented */
|
||||
|
||||
/* get kernel virtual address */
|
||||
pxa2x0_bs_vaddr,
|
||||
|
||||
/* mmap */
|
||||
bs_notimpl_bs_mmap,
|
||||
|
||||
/* barrier */
|
||||
pxa2x0_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
generic_bs_r_1,
|
||||
generic_armv4_bs_r_2,
|
||||
generic_bs_r_4,
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
generic_bs_rm_1,
|
||||
generic_armv4_bs_rm_2,
|
||||
generic_bs_rm_4,
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
bs_notimpl_bs_rr_1,
|
||||
generic_armv4_bs_rr_2,
|
||||
generic_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
generic_bs_w_1,
|
||||
generic_armv4_bs_w_2,
|
||||
generic_bs_w_4,
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
generic_bs_wm_1,
|
||||
generic_armv4_bs_wm_2,
|
||||
generic_bs_wm_4,
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
bs_notimpl_bs_wr_1,
|
||||
generic_armv4_bs_wr_2,
|
||||
generic_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_bs_sr_1,
|
||||
generic_armv4_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_bs_c_1,
|
||||
generic_armv4_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
int
|
||||
pxa2x0_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
|
||||
int cacheable, bus_space_handle_t *bshp)
|
||||
{
|
||||
u_long startpa, endpa, pa;
|
||||
vaddr_t va;
|
||||
pt_entry_t *pte;
|
||||
|
||||
if ((u_long)bpa > (u_long)KERNEL_BASE) {
|
||||
/* Some IO registers (ex. UART ports for console)
|
||||
are mapped to fixed address by board specific
|
||||
routine. */
|
||||
*bshp = bpa;
|
||||
return(0);
|
||||
}
|
||||
|
||||
startpa = trunc_page(bpa);
|
||||
endpa = round_page(bpa + size);
|
||||
|
||||
/* XXX use extent manager to check duplicate mapping */
|
||||
|
||||
va = uvm_km_valloc(kernel_map, endpa - startpa);
|
||||
if (! va)
|
||||
return(ENOMEM);
|
||||
|
||||
*bshp = (bus_space_handle_t)(va + (bpa - startpa));
|
||||
|
||||
for(pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
|
||||
pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
|
||||
pte = vtopte(va);
|
||||
if (cacheable == 0)
|
||||
*pte &= ~L2_S_CACHE_MASK;
|
||||
}
|
||||
pmap_update(pmap_kernel());
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
void
|
||||
pxa2x0_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
|
||||
{
|
||||
|
||||
/* Nothing to do. */
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pxa2x0_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
|
||||
bus_size_t size, bus_space_handle_t *nbshp)
|
||||
{
|
||||
|
||||
*nbshp = bsh + offset;
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
pxa2x0_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
|
||||
bus_size_t len, int flags)
|
||||
{
|
||||
|
||||
/* Nothing to do. */
|
||||
}
|
||||
|
||||
void *
|
||||
pxa2x0_bs_vaddr(void *t, bus_space_handle_t bsh)
|
||||
{
|
||||
|
||||
return ((void *)bsh);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pxa2x0_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
|
||||
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
|
||||
bus_addr_t *bpap, bus_space_handle_t *bshp)
|
||||
{
|
||||
|
||||
panic("pxa2x0_io_bs_alloc(): not implemented\n");
|
||||
}
|
||||
|
||||
void
|
||||
pxa2x0_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
|
||||
{
|
||||
|
||||
panic("pxa2x0_io_bs_free(): not implemented\n");
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
/* $NetBSD: pxa2x0reg.h,v 1.1 2002/10/19 19:31:40 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
* Written by Hiroyuki Bessho for Genetec Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
|
||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Intel PXA2[15]0 processor is XScale based integrated CPU
|
||||
*
|
||||
* Reference:
|
||||
* Intel(r) PXA250 and PXA210 Application Processors
|
||||
* Developer's Manual
|
||||
* (278522-001.pdf)
|
||||
*/
|
||||
#ifndef _ARM_XSCALE_PXA2X0REG_H_
|
||||
#define _ARM_XSCALE_PXA2X0REG_H_
|
||||
|
||||
/* Borrow some register definitions from sa11x0 */
|
||||
#include <arm/sa11x0/sa11x0_reg.h>
|
||||
|
||||
#ifndef _LOCORE
|
||||
#include <sys/types.h> /* for uint32_t */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Chip select domains
|
||||
*/
|
||||
#define PXA2X0_CS0_START 0x00000000
|
||||
#define PXA2X0_CS1_START 0x04000000
|
||||
#define PXA2X0_CS2_START 0x08000000
|
||||
#define PXA2X0_CS3_START 0x0c000000
|
||||
#define PXA2X0_CS4_START 0x10000000
|
||||
#define PXA2X0_CS5_START 0x14000000
|
||||
|
||||
#define PXA2X0_PCMCIA_SLOT0 0x20000000
|
||||
#define PXA2X0_PCMCIA_SLOT1 0x30000000
|
||||
|
||||
#define PXA2X0_PERIPH_START 0x40000000
|
||||
/* #define PXA2X0_MEMCTL_START 0x48000000 */
|
||||
#define PXA2X0_PERIPH_END 0x480fffff
|
||||
|
||||
#define PXA2X0_SDRAM0_START 0xa0000000
|
||||
#define PXA2X0_SDRAM1_START 0xa4000000
|
||||
#define PXA2X0_SDRAM2_START 0xa8000000
|
||||
#define PXA2X0_SDRAM3_START 0xac000000
|
||||
|
||||
/*
|
||||
* Physical address of integrated peripherals
|
||||
*/
|
||||
|
||||
#define PXA2X0_DMAC_BASE 0x40000000
|
||||
#define PXA2X0_DMAC_SIZE 0x300
|
||||
#define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */
|
||||
#define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */
|
||||
#define PXA2X0_I2C_BASE 0x40300000
|
||||
#define PXA2X0_I2C_SIZE 0x000016a4
|
||||
#define PXA2X0_I2S_BASE 0x40400000
|
||||
#define PXA2X0_AC97_BASE 0x40500000
|
||||
#define PXA2X0_UDC_BASE 0x40600000 /* USB Client */
|
||||
#define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */
|
||||
#define PXA2X0_ICP_BASE 0x40800000
|
||||
#define PXA2X0_RTC_BASE 0x40900000
|
||||
#define PXA2X0_RTC_SIZE 0x10
|
||||
#define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */
|
||||
#define PXA2X0_PWM0_BASE 0x40b00000
|
||||
#define PXA2X0_PWM1_BASE 0x40c00000
|
||||
#define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */
|
||||
#define PXA2X0_INTCTL_SIZE 0x20
|
||||
#define PXA2X0_GPIO_BASE 0x40e00000
|
||||
#define PXA2X0_GPIO_SIZE 0x70
|
||||
#define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */
|
||||
#define PXA2X0_SSP_BASE 0x41000000
|
||||
#define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */
|
||||
#define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */
|
||||
#define PXA2X0_CLKMAN_SIZE 12
|
||||
#define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */
|
||||
#define PXA2X0_LCDC_SIZE 0x220
|
||||
#define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */
|
||||
#define PXA2X0_MEMCTL_SIZE 0x48
|
||||
|
||||
/* width of interrupt controller */
|
||||
#define ICU_LEN 32 /* but [0..7,15,16] is not used */
|
||||
#define ICU_INT_HWMASK 0xffffff00
|
||||
#define PXA2X0_IRQ_MIN 8 /* 0..7 are not used by integrated
|
||||
peripherals */
|
||||
|
||||
/* UART */
|
||||
#define PXA2X0_COM_FREQ 14745600L
|
||||
|
||||
/* I2C */
|
||||
#define I2C_IBMR 0x1680 /* Bus monitor register */
|
||||
#define I2C_IDBR 0x1688 /* Data buffer */
|
||||
#define I2C_ICR 0x1690 /* Control register */
|
||||
#define ICR_START (1<<0)
|
||||
#define ICR_STOP (1<<1)
|
||||
#define ICR_ACKNAK (1<<2)
|
||||
#define ICR_TB (1<<3)
|
||||
#define ICR_MA (1<<4)
|
||||
#define I2C_ISR 0x1698 /* Status register */
|
||||
#define I2C_ISAR 0x16a0 /* Slave address */
|
||||
|
||||
/* Clock Manager */
|
||||
#define CLKMAN_CCCR 0x00 /* Core Clock Configuration */
|
||||
#define CCCR_TURBO_X1 (2<<7)
|
||||
#define CCCR_TURBO_X15 (3<<7) /* x 1.5 */
|
||||
#define CCCR_TURBO_X2 (4<<7)
|
||||
#define CCCR_TURBO_X25 (5<<7) /* x 2.5 */
|
||||
#define CCCR_TURBO_X3 (6<<7) /* x 3.0 */
|
||||
#define CCCR_RUN_X1 (1<<5)
|
||||
#define CCCR_RUN_X2 (2<<5)
|
||||
#define CCCR_RUN_X4 (3<<5)
|
||||
#define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */
|
||||
#define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */
|
||||
#define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */
|
||||
#define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */
|
||||
#define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */
|
||||
#define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */
|
||||
|
||||
#define CLKMAN_CKEN 0x04 /* Clock Enable Register */
|
||||
#define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */
|
||||
|
||||
#define CCCR_N_SHIFT 7
|
||||
#define CCCR_N_MASK (0x07<<CCCR_N_SHIFT)
|
||||
#define CCCR_M_SHIFT 5
|
||||
#define CCCR_M_MASK (0x03<<CCCR_M_SHIFT)
|
||||
#define CCCR_L_MASK 0x1f
|
||||
|
||||
#define CKEN_PWM0 (1<<0)
|
||||
#define CKEN_PWM1 (1<<1)
|
||||
#define CKEN_AC97 (1<<2)
|
||||
#define CKEN_SSP (1<<3)
|
||||
#define CKEN_STUART (1<<5)
|
||||
#define CKEN_FFUART (1<<6)
|
||||
#define CKEN_BTUART (1<<7)
|
||||
#define CKEN_I2S (1<<8)
|
||||
#define CKEN_USB (1<<11)
|
||||
#define CKEN_MMC (1<<12)
|
||||
#define CKEN_FICP (1<<13)
|
||||
#define CKEN_I2C (1<<14)
|
||||
#define CKEN_LCD (1<<16)
|
||||
|
||||
#define OSCC_OOK (1<<0) /* 32.768KHz oscillator status */
|
||||
#define OSCC_OON (1<<1) /* 32.768KHz oscillator */
|
||||
|
||||
/*
|
||||
* RTC
|
||||
*/
|
||||
#define RTC_RCNR 0x0000 /* count register */
|
||||
#define RTC_RTAR 0x0004 /* alarm register */
|
||||
#define RTC_RTSR 0x0008 /* status register */
|
||||
#define RTC_RTTR 0x000c /* trim register */
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
#define GPIO_GPLR0 0x00 /* Level reg [31:0] */
|
||||
#define GPIO_GPLR1 0x04 /* Level reg [63:32] */
|
||||
#define GPIO_GPLR2 0x08 /* Level reg [80:64] */
|
||||
|
||||
#define GPIO_GPDR0 0x0c /* dir reg [31:0] */
|
||||
#define GPIO_GPDR1 0x10 /* dir reg [63:32] */
|
||||
#define GPIO_GPDR2 0x14 /* dir reg [80:64] */
|
||||
|
||||
#define GPIO_GPSR0 0x18 /* set reg [31:0] */
|
||||
#define GPIO_GPSR1 0x1c /* set reg [63:32] */
|
||||
#define GPIO_GPSR2 0x20 /* set reg [80:64] */
|
||||
|
||||
#define GPIO_GPCR0 0x24 /* clear reg [31:0] */
|
||||
#define GPIO_GPCR1 0x28 /* clear reg [63:32] */
|
||||
#define GPIO_GPCR2 0x2c /* clear reg [80:64] */
|
||||
|
||||
#define GPIO_GPER0 0x30 /* rising edge [31:0] */
|
||||
#define GPIO_GPER1 0x34 /* rising edge [63:32] */
|
||||
#define GPIO_GPER2 0x38 /* rising edge [80:64] */
|
||||
|
||||
#define GPIO_GRER0 0x30 /* rising edge [31:0] */
|
||||
#define GPIO_GRER1 0x34 /* rising edge [63:32] */
|
||||
#define GPIO_GRER2 0x38 /* rising edge [80:64] */
|
||||
|
||||
#define GPIO_GFER0 0x3c /* falling edge [31:0] */
|
||||
#define GPIO_GFER1 0x40 /* falling edge [63:32] */
|
||||
#define GPIO_GFER2 0x44 /* falling edge [80:64] */
|
||||
|
||||
#define GPIO_GEDR0 0x48 /* edge detect [31:0] */
|
||||
#define GPIO_GEDR1 0x4c /* edge detect [63:32] */
|
||||
#define GPIO_GEDR2 0x50 /* edge detect [80:64] */
|
||||
|
||||
#define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */
|
||||
#define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */
|
||||
#define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */
|
||||
#define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */
|
||||
#define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */
|
||||
#define GPIO_GAFR2_U 0x68 /* alternate function [80] */
|
||||
|
||||
/*
|
||||
* memory controller
|
||||
*/
|
||||
|
||||
#define MEMCTL_MDCNFG 0x0000
|
||||
#define MDCNFG_DE0 (1<<0)
|
||||
#define MDCNFG_DE1 (1<<1)
|
||||
#define MDCNFG_DE2 (1<<16)
|
||||
#define MDCNFG_DE3 (1<<17)
|
||||
|
||||
#define MEMCTL_MDREFR 0x04 /* refresh control register */
|
||||
#define MDREFR_DRI 0xfff
|
||||
#define MDREFR_E0PIN (1<<12)
|
||||
#define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */
|
||||
#define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */
|
||||
#define MDREFR_E1PIN (1<<15)
|
||||
#define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */
|
||||
#define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */
|
||||
#define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */
|
||||
#define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */
|
||||
#define MDREFR_APD (1<<20) /* Auto Power Down */
|
||||
#define MDREFR_SLFRSH (1<<22) /* Self Refresh */
|
||||
#define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */
|
||||
#define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */
|
||||
#define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */
|
||||
|
||||
#define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */
|
||||
#define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */
|
||||
#define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */
|
||||
#define MSC2_RBUFF_SHIFT 15 /* return data buffer */
|
||||
#define MSC2_RBUFF (1<<MSC2_RBUFF_SHIFT)
|
||||
#define MSC2_RRR_SHIFT 12 /* recovery time */
|
||||
#define MSC2_RRR (7<<MSC2_RRR_SHIFT)
|
||||
#define MSC2_RDN_SHIFT 8 /* ROM delay next access */
|
||||
#define MSC2_RDN (0x0f<<MSC2_RDN_SHIFT)
|
||||
#define MSC2_RDF_SHIFT 4 /* ROM delay first access*/
|
||||
#define MSC2_RDF (0x0f<<MSC2_RDF_SHIFT)
|
||||
#define MSC2_RBW_SHIFT 3 /* 32/16 bit bus */
|
||||
#define MSC2_RBW (1<<MSC2_RBW_SHIFT)
|
||||
#define MSC2_RT_SHIFT 0 /* type */
|
||||
#define MSC2_RT (7<<MSC2_RT_SHIFT)
|
||||
#define MSC2_RT_NONBURST 0
|
||||
#define MSC2_RT_SRAM 1
|
||||
#define MSC2_RT_BURST4 2
|
||||
#define MSC2_RT_BURST8 3
|
||||
#define MSC2_RT_VLIO 4
|
||||
|
||||
#define MEMCTL_MCMEM0 0x28 /* expansion memory timing configuration */
|
||||
#define MEMCTL_MCMEM1 0x2c /* expansion memory timing configuration */
|
||||
#define MEMCTL_MCATT0 0x30
|
||||
#define MEMCTL_MCATT1 0x34
|
||||
#define MEMCTL_MCIO0 0x38
|
||||
#define MEMCTL_MCIO1 0x3c
|
||||
|
||||
#define MEMCTL_MECR 0x14 /* Expansion memory configuration */
|
||||
#define MECR_NOS (1<<0) /* Number of sockets */
|
||||
#define MECR_CIT (1<<1) /* Card-is-there */
|
||||
|
||||
#define MEMCTL_MDMRS 0x0040
|
||||
|
||||
/*
|
||||
* LCD Controller
|
||||
*/
|
||||
#define LCDC_LCCR0 0x000 /* Controller Control Register 0 */
|
||||
#define LCCR0_ENB (1U<<0) /* LCD Controller Enable */
|
||||
#define LCCR0_CMS (1U<<1) /* Color/Mono select */
|
||||
#define LCCR0_SDS (1U<<2) /* Single/Dual -panel */
|
||||
#define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */
|
||||
#define LCCR0_SFM (1U<<4) /* Start of Frame Mask */
|
||||
#define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */
|
||||
#define LCCR0_EFM (1U<<6) /* End of Frame Mask */
|
||||
#define LCCR0_PAS (1U<<7) /* Passive/Active Display select */
|
||||
#define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */
|
||||
#define LCCR0_DIS (1U<<10) /* LCD Disable */
|
||||
#define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */
|
||||
#define LCCR0_BM (1U<<20) /* Branch Mask */
|
||||
#define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */
|
||||
|
||||
#define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM)
|
||||
|
||||
|
||||
#define LCDC_LCCR1 0x004 /* Controller Control Register 1 */
|
||||
#define LCDC_LCCR2 0x008 /* Controller Control Register 2 */
|
||||
#define LCDC_LCCR3 0x00c /* Controller Control Register 2 */
|
||||
#define LCCR3_BPP_SHIFT 24 /* Bits per pixel */
|
||||
#define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT)
|
||||
#define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */
|
||||
#define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */
|
||||
#define LCDC_LCSR 0x038 /* controller status register */
|
||||
#define LCSR_LDD (1U<<0) /* LCD disable done */
|
||||
#define LCSR_SOF (1U<<1) /* Start of frame */
|
||||
#define LCDC_LIIDR 0x03c /* controller interrupt ID Register */
|
||||
#define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */
|
||||
#define LCDC_TCR 0x044 /* TMED Control Register */
|
||||
#define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */
|
||||
#define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */
|
||||
#define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */
|
||||
#define LCDC_LDCMD0 0x20c /* DMA ch0 command register */
|
||||
#define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */
|
||||
#define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */
|
||||
#define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */
|
||||
#define LCDC_LDCMD1 0x21c /* DMA ch1 command register */
|
||||
|
||||
#endif /* _ARM_XSCALE_PXA2X0REG_H_ */
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/* $NetBSD: pxa2x0var.h,v 1.1 2002/10/19 19:31:41 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
|
||||
* Written by Hiroyuki Bessho for Genetec Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Genetec Corporation.
|
||||
* 4. The name of Genetec Corporation may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _ARM_XSCALE_PXA2X0VAR_H_
|
||||
#define _ARM_XSCALE_PXA2X0VAR_H_
|
||||
|
||||
#include <arm/sa11x0/sa11x0_var.h>
|
||||
|
||||
/* PXA2X0's integrated peripheral bus.
|
||||
*
|
||||
* pxaip_softc `inherits' sa11x0_softc. This is a hack to make OS
|
||||
* timer driver for SA11x0 (arm/sa11x0/sa11x0_ost.c) work on PXA2X0.
|
||||
* PXA2X0 has a same OS timer unit as SA11X0 has.
|
||||
*/
|
||||
|
||||
typedef int (* pxa2x0_irq_handler_t)(void *);
|
||||
|
||||
struct pxa2x0_softc {
|
||||
struct sa11x0_softc saip;
|
||||
|
||||
bus_space_handle_t sc_memctl_ioh; /* Memory controller */
|
||||
bus_space_handle_t sc_clkman_ioh; /* Clock manager */
|
||||
bus_space_handle_t sc_rtc_ioh; /* real time clock */
|
||||
};
|
||||
|
||||
extern struct pxa2x0_softc *pxa2x0_softc;
|
||||
|
||||
struct pxa2x0_attach_args {
|
||||
struct sa11x0_attach_args pxa_sa;
|
||||
|
||||
int pxa_index; /* to specify device by index number */
|
||||
|
||||
#define pxa_sc pxa_sa.sa_sc
|
||||
#define pxa_iot pxa_sa.sa_iot
|
||||
#define pxa_addr pxa_sa.sa_addr
|
||||
#define pxa_size pxa_sa.sa_size
|
||||
#define pxa_intr pxa_sa.sa_intr
|
||||
#define pxa_gpio pxa_sa.sa_gpio
|
||||
};
|
||||
|
||||
|
||||
extern struct bus_space pxa2x0_bs_tag;
|
||||
extern struct arm32_bus_dma_tag pxa2x0_bus_dma_tag;
|
||||
extern struct bus_space pxa2x0_a4x_bs_tag;
|
||||
|
||||
void pxa2x0_set_intcbase(vaddr_t);
|
||||
void pxa2x0_intr_init(void);
|
||||
void *pxa2x0_intr_establish(int irqno, int level,
|
||||
int (*func)(void *), void *cookie);
|
||||
void pxa2x0_update_intr_masks( int irqno, int level );
|
||||
extern int current_spl_level;
|
||||
|
||||
/* Integrated UART */
|
||||
enum pxa2x0_uart_id { UART_FFUART, UART_BTUART, UART_STUART };
|
||||
extern void com_pxaip_setup( struct pxa2x0_softc *, enum pxa2x0_uart_id );
|
||||
|
||||
|
||||
/* misc. */
|
||||
extern int pxa2x0_measure_cpuclock( struct pxa2x0_softc * );
|
||||
extern void pxa2x0_fcs_init(void);
|
||||
extern void pxa2x0_freq_change(int);
|
||||
extern void pxa2x0_turbo_mode(int);
|
||||
extern int pxa2x0_i2c_master_tx( int, uint8_t *, int );
|
||||
|
||||
void pxa2x0_irq_handler(struct clockframe *);
|
||||
|
||||
|
||||
#endif /* _ARM_XSCALE_PXA2X0VAR_H_ */
|
||||
Loading…
Reference in New Issue