s,#ifdef MIPS3,#if defined(MIPS3) || defined(MIPS64),g
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sekiya
parent
82ca9dba92
commit
5e061c633c
@ -1,4 +1,4 @@
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/* $NetBSD: bus.c,v 1.32 2004/09/29 04:06:52 sekiya Exp $ */
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/* $NetBSD: bus.c,v 1.33 2004/10/01 07:16:57 sekiya Exp $ */
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/*
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -38,7 +38,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.32 2004/09/29 04:06:52 sekiya Exp $");
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__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.33 2004/10/01 07:16:57 sekiya Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -94,7 +94,7 @@ sgimips_bus_dma_init(void)
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break;
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#endif
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#ifdef MIPS3
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#if defined(MIPS3) || defined(MIPS64)
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/* >=R4000*/
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case MACH_SGI_IP20:
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case MACH_SGI_IP22:
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@ -235,7 +235,7 @@ bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o, u_i
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}
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}
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#ifdef MIPS3
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#if defined(MIPS3) || defined(MIPS64)
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u_int64_t
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bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o)
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{
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@ -275,7 +275,7 @@ bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o, u_i
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break;
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}
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}
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#endif /* MIPS3 */
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#endif /* MIPS3 || MIPS64 */
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int
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bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size,
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@ -767,7 +767,7 @@ _bus_dmamap_sync_mips1(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
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}
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#endif /* MIPS1 */
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#ifdef MIPS3
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#if defined(MIPS3) || defined(MIPS64)
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/*
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* Common function for DMA map synchronization. May be called
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* by chipset-specific DMA map synchronization functions.
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@ -922,7 +922,7 @@ _bus_dmamap_sync_mips3(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
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len -= minlen;
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}
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}
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#endif /* MIPS3 */
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#endif /* MIPS3 || MIPS64 */
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/*
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* Common function for DMA-safe memory allocation. May be called
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@ -1,4 +1,4 @@
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/* $NetBSD: clock.c,v 1.13 2004/04/10 22:48:12 pooka Exp $ */
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/* $NetBSD: clock.c,v 1.14 2004/10/01 07:16:57 sekiya Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -79,7 +79,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.13 2004/04/10 22:48:12 pooka Exp $");
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.14 2004/10/01 07:16:57 sekiya Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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@ -155,7 +155,7 @@ cpu_initclocks()
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if (clockfns == NULL)
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panic("cpu_initclocks: clock device not attached");
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#ifdef MIPS3
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#if defined(MIPS3) || defined(MIPS64)
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if (mach_type != MACH_SGI_IP12) {
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next_clk_intr = mips3_cp0_count_read()
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+ curcpu()->ci_cycles_per_hz;
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@ -172,7 +172,7 @@ cpu_initclocks()
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tickfixinterval = hz >> (ftp - 1);
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}
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}
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#endif /* MIPS3 */
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#endif /* MIPS3 || MIPS64 */
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(*clockfns->cf_init)(clockdev);
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}
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@ -285,7 +285,7 @@ mips1_clkread()
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return 0;
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}
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#ifdef MIPS3
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#if defined(MIPS3) || defined(MIPS64)
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void
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mips3_clock_intr(u_int32_t status, u_int32_t cause, u_int32_t pc,
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u_int32_t ipending)
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@ -325,4 +325,4 @@ mips3_clkread()
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MIPS_COUNT_TO_MHZ(curcpu(), count, res);
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return (res);
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}
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#endif /* MIPS3 */
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#endif /* MIPS3 || MIPS64 */
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.85 2004/04/11 12:17:10 pooka Exp $ */
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/* $NetBSD: machdep.c,v 1.86 2004/10/01 07:16:57 sekiya Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang
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@ -34,7 +34,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.85 2004/04/11 12:17:10 pooka Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.86 2004/10/01 07:16:57 sekiya Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -414,7 +414,7 @@ mach_init(int argc, char **argv, int magic, struct btinfo_common *btinfo)
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platform.clkread = mips1_clkread;
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break;
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#endif /* MIPS1 */
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#ifdef MIPS3
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#if defined(MIPS3) || defined(MIPS64)
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case MACH_SGI_IP20:
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i = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd0000);
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mach_boardrev = (i & 0x7000) >> 12;
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@ -442,7 +442,7 @@ mach_init(int argc, char **argv, int magic, struct btinfo_common *btinfo)
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platform.intr5 = mips3_clock_intr;
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platform.clkread = mips3_clkread;
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break;
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#endif /* MIPS3 */
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#endif /* MIPS3 || MIPS64 */
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default:
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panic("IP%d architecture not supported", mach_type);
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break;
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@ -829,7 +829,7 @@ void ddb_trap_hook(int where)
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void mips_machdep_cache_config(void)
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{
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#if defined(MIPS3)
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#if defined(MIPS3) || defined(MIPS64)
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volatile u_int32_t cpu_config;
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arcbios_tree_walk(mips_machdep_find_l2cache, NULL);
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