Cleanup some and make these look more like hp300 versions.
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briggs
parent
23622438bf
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5dd8297b11
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.9 1995/04/10 12:42:07 mycroft Exp $ */
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/* $NetBSD: pmap.h,v 1.10 1995/06/21 03:14:06 briggs Exp $ */
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/*
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* Copyright (c) 1987 Carnegie-Mellon University
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@ -77,17 +77,26 @@
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#ifndef _PMAP_MACHINE_
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#define _PMAP_MACHINE_
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#define MAC_PAGE_SIZE NBPG
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#include <machine/pte.h>
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#if defined(M68040)
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#define MAC_SEG_SIZE (mmutype == MMU_68040 ? 0x40000 : NBSEG)
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#else
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#define MAC_SEG_SIZE NBSEG
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#endif
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#define mac68k_trunc_seg(x) (((unsigned)(x)) & ~(MAC_SEG_SIZE-1))
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#define mac68k_round_seg(x) mac68k_trunc_seg((unsigned)(x)+MAC_SEG_SIZE-1)
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/*
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* Pmap stuff
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*/
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struct pmap {
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struct pte *pm_ptab; /* KVA of page table */
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struct ste *pm_stab; /* KVA of segment table */
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struct ste *pm_rtab; /* KVA of 68040 root table */
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pt_entry_t *pm_ptab; /* KVA of page table */
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st_entry_t *pm_stab; /* KVA of segment table */
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int pm_stchanged; /* ST changed */
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int pm_stfree; /* 040: free lev2 blocks */
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st_entry_t *pm_stpa; /* 040: ST phys addr */
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short pm_sref; /* segment table ref count */
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short pm_count; /* pmap reference count */
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simple_lock_data_t pm_lock; /* lock on pmap */
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@ -97,14 +106,28 @@ struct pmap {
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typedef struct pmap *pmap_t;
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/*
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* On the 040, we keep track of which level 2 blocks are already in use
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* with the pm_stfree mask. Bits are arranged from LSB (block 0) to MSB
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* (block 31). For convenience, the level 1 table is considered to be
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* block 0.
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*
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* MAX[KU]L2SIZE control how many pages of level 2 descriptors are allowed
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* for the kernel and users. 8 implies only the initial "segment table"
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* page is used. WARNING: don't change MAXUL2SIZE unless you can allocate
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* physically contiguous pages for the ST in pmap.c!
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*/
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#define MAXKL2SIZE 32
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#define MAXUL2SIZE 8
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#define l2tobm(n) (1 << (n))
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#define bmtol2(n) (ffs(n) - 1)
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/*
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* Macros for speed
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*/
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#define PMAP_ACTIVATE(pmapp, pcbp, iscurproc) \
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if ((pmapp) != NULL && (pmapp)->pm_stchanged) { \
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(pcbp)->pcb_ustp = \
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mac68k_btop(pmap_extract(pmap_kernel(), (vm_offset_t) \
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(cpu040 ? (pmapp)->pm_rtab : (pmapp)->pm_stab))); \
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if ((pmapp)->pm_stchanged) { \
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(pcbp)->pcb_ustp = mac68k_btop((vm_offset_t)(pmapp)->pm_stpa); \
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if (iscurproc) \
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loadustp((pcbp)->pcb_ustp); \
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(pmapp)->pm_stchanged = FALSE; \
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@ -119,7 +142,7 @@ typedef struct pv_entry {
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struct pv_entry *pv_next; /* next pv_entry */
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struct pmap *pv_pmap; /* pmap where mapping lies */
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vm_offset_t pv_va; /* virtual address for mapping */
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struct ste *pv_ptste; /* non-zero if VA maps a PT page */
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st_entry_t *pv_ptste; /* non-zero if VA maps a PT page */
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struct pmap *pv_ptpmap; /* if pv_ptste, pmap for PT page */
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int pv_flags; /* flags */
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} *pv_entry_t;
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@ -127,22 +150,41 @@ typedef struct pv_entry {
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#define PV_CI 0x01 /* all entries must be cache inhibited */
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#define PV_PTPAGE 0x02 /* entry maps a page table page */
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struct pv_page;
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struct pv_page_info {
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TAILQ_ENTRY(pv_page) pgi_list;
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struct pv_entry *pgi_freelist;
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int pgi_nfree;
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};
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/*
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* This is basically:
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* ((NBPG - sizeof(struct pv_page_info)) / sizeof(struct pv_entry))
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*/
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#define NPVPPG 170
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struct pv_page {
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struct pv_page_info pvp_pgi;
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struct pv_entry pvp_pv[NPVPPG];
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};
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#ifdef _KERNEL
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pv_entry_t pv_table; /* array of entries, one per page */
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struct pmap kernel_pmap_store;
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#ifdef MACHINE_NONCONTIG
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#define pa_index(pa) pmap_page_index(pa)
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#else
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#define pa_index(pa) atop(pa - vm_first_phys)
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#endif
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#define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
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#define pmap_kernel() (&kernel_pmap_store)
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#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
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#define active_pmap(pm) \
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((pm) == pmap_kernel() || (pm) == curproc->p_vmspace->vm_map.pmap)
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extern struct pte *Sysmap;
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extern struct pv_entry *pv_table; /* array of entries, one per page */
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#define pmap_page_index(pa) pmap_page_index(pa)
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#define pa_to_pvh(pa) (&pv_table[pmap_page_index(pa)])
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#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
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#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
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extern pt_entry_t *Sysmap;
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extern char *vmmap; /* map for mem, dumps, etc. */
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#endif /* _KERNEL */
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@ -1,4 +1,4 @@
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/* $NetBSD: pte.h,v 1.7 1994/10/26 08:46:43 cgd Exp $ */
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/* $NetBSD: pte.h,v 1.8 1995/06/21 03:14:11 briggs Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -83,29 +83,8 @@
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* Mac hardware segment/page table entries
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*/
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struct ste {
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unsigned int sg_pfnum:20; /* page table frame number */
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unsigned int :8; /* reserved at 0 */
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unsigned int :1; /* reserved at 1 */
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unsigned int sg_prot:1; /* write protect bit */
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unsigned int sg_v:2; /* valid bits */
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};
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struct pte {
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unsigned int pg_pfnum:20; /* page frame number or 0 */
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unsigned int :3;
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unsigned int pg_w:1; /* is wired */
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unsigned int :1; /* reserved at zero */
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unsigned int pg_ci:1; /* cache inhibit bit */
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unsigned int pg_cm1:1; /* cache mode, lsb (68040) */
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unsigned int pg_m:1; /* hardware modified (dirty) bit */
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unsigned int pg_u:1; /* hardware used (reference) bit */
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unsigned int pg_prot:1; /* write protect bit */
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unsigned int pg_v:2; /* valid bit */
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};
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typedef struct ste st_entry_t; /* segment table entry */
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typedef struct pte pt_entry_t; /* Mach page table entry */
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typedef int st_entry_t; /* segment table entry */
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typedef int pt_entry_t; /* Mach page table entry */
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#define PT_ENTRY_NULL ((pt_entry_t *) 0)
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#define ST_ENTRY_NULL ((st_entry_t *) 0)
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@ -115,18 +94,26 @@ typedef struct pte pt_entry_t; /* Mach page table entry */
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#define SG_PROT 0x00000004 /* access protection mask */
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#define SG_RO 0x00000004
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#define SG_RW 0x00000000
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#define SG_U 0x00000008 /* modified bit (68040) */
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#define SG_FRAME 0xfffff000
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#define SG_IMASK1 0xfe000000
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#define SG_IMASK2 0x01fc0000
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#define SG_040IMASK 0xfffc0000
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#define SG_040PMASK 0x0003f000
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#define SG_ISHIFT1 25
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#define SG_040ISHIFT 18
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#define SG_IMASK 0xffc00000
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#define SG_PMASK 0x003ff000
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#define SG_ISHIFT 22
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#define SG_PMASK 0x003ff000
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#define SG_PSHIFT 12
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/* 68040 additions */
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#define SG4_MASK1 0xfe000000
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#define SG4_SHIFT1 25
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#define SG4_MASK2 0x01fc0000
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#define SG4_SHIFT2 18
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#define SG4_MASK3 0x0003f000
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#define SG4_SHIFT3 12
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#define SG4_ADDR1 0xfffffe00
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#define SG4_ADDR2 0xffffff00
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#define SG4_LEV1SIZE 128
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#define SG4_LEV2SIZE 128
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#define SG4_LEV3SIZE 64
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#define PG_V 0x00000001
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#define PG_NV 0x00000000
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#define PG_PROT 0x00000004
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@ -135,20 +122,24 @@ typedef struct pte pt_entry_t; /* Mach page table entry */
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#define PG_W 0x00000100
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#define PG_RO 0x00000004
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#define PG_RW 0x00000000
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#define PG_CI 0x00000040
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#define PG_CCB 0x00000020
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#define PG_CIN 0x00000060
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#define PG_FRAME 0xfffff000
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#define PG_CI 0x00000040
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#define PG_SHIFT 12
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#define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT)
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#define MAC_040RTSIZE 512 /* root (level 1) table size */
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#define MAC_040STSIZE 512 /* segment (level 2) table size */
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#define MAC_040PTSIZE 256 /* page (level 3) table size */
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#define MAC_STSIZE MAC_PAGE_SIZE /* segment table size */
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#define MAC_MAX_PTSIZE MAC_SEG_SIZE /* max size of UPT */
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/* 68040 additions */
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#define PG_CMASK 0x00000060 /* cache mode mask */
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#define PG_CWT 0x00000000 /* writethrough caching */
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#define PG_CCB 0x00000020 /* copyback caching */
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#define PG_CIS 0x00000040 /* cache inhibited serialized */
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#define PG_CIN 0x00000060 /* cache inhibited nonserialized */
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#define PG_SO 0x00000080 /* supervisor only */
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#define MAC_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t))
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/* user process segment table size */
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#define MAC_MAX_PTSIZE 0x400000 /* max size of UPT */
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#define MAC_MAX_KPTSIZE 0x100000 /* max memory to allocate to KPT */
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#define MAC_PTBASE 0x60100000 /* UPT map base address */
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#define MAC_PTBASE 0x10000000 /* UPT map base address */
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#define MAC_PTMAXSIZE 0x70000000 /* UPT map maximum size */
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/*
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@ -156,8 +147,6 @@ typedef struct pte pt_entry_t; /* Mach page table entry */
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*/
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#define kvtopte(va) \
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(&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT])
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#define kvtoste(va) \
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(&Sysseg[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> SEGSHIFT])
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#define ptetokv(pt) \
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((((pt_entry_t *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
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#define kvtophys(va) \
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