Finally make cpufuncs work properly on acorn26, since something seems to be
using it. This entailed adding support for ARM2 and ARM2as, and allowing for getting CPU IDs other than from CP15, since ARM2(as) doesn't have CP15.
This commit is contained in:
bjh21
parent
65c9a0b32e
commit
5dbe04b416
@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.22 2007/03/04 05:59:03 christos Exp $ */
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/* $NetBSD: cpu.c,v 1.23 2007/03/04 14:47:18 bjh21 Exp $ */
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/*-
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* Copyright (c) 2000, 2001 Ben Harris
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@ -32,7 +32,7 @@
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.22 2007/03/04 05:59:03 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.23 2007/03/04 14:47:18 bjh21 Exp $");
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#include <sys/device.h>
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#include <sys/proc.h>
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@ -62,8 +62,6 @@ static void cpu_arm3_setup(struct device *, int);
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#endif
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static void cpu_delay_calibrate(struct device *);
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register_t cpu_type;
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struct cpu_softc {
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struct device sc_dev;
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};
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@ -92,9 +90,9 @@ cpu_attach(struct device *parent, struct device *self, void *aux)
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the_cpu = (struct cpu_softc *)self;
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printf(": ");
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cpu_type = cpu_identify();
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cputype = cpu_identify();
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supported = 0;
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switch (cpu_type) {
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switch (cputype) {
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case CPU_ID_ARM2:
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printf("ARM2");
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#ifdef CPU_ARM2
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@ -110,17 +108,18 @@ cpu_attach(struct device *parent, struct device *self, void *aux)
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#endif
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break;
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case CPU_ID_ARM3:
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printf("ARM3 (rev. %d)", cpu_type & CPU_ID_REVISION_MASK);
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printf("ARM3 (rev. %d)", cputype & CPU_ID_REVISION_MASK);
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#ifdef CPU_ARM3
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supported = 1;
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cpu_arm3_setup(self, device_cfdata(self)->cf_flags);
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#endif
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break;
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default:
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printf("Unknown type, ID=0x%08x", cpu_type);
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printf("Unknown type, ID=0x%08x", cputype);
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break;
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}
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printf("\n");
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set_cpufuncs();
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if (!supported)
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printf("%s: WARNING: CPU type not supported by kernel\n",
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self->dv_xname);
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@ -286,7 +285,7 @@ cpu_cache_flush(void)
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#ifdef CPU_ARM3
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#if defined(CPU_ARM2) || defined(CPU_ARM250)
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if ((cpu_type & CPU_ID_CPU_MASK) == CPU_ID_ARM3)
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if ((cputype & CPU_ID_CPU_MASK) == CPU_ID_ARM3)
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#endif
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ARM3_WRITE(ARM3_CP15_FLUSH, 0);
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.78 2007/01/06 00:50:54 christos Exp $ */
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/* $NetBSD: cpufunc.c,v 1.79 2007/03/04 14:47:18 bjh21 Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -46,7 +46,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.78 2007/01/06 00:50:54 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.79 2007/03/04 14:47:18 bjh21 Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_cpuoptions.h"
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@ -106,6 +106,122 @@ int arm_dcache_align_mask;
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/* 1 == use cpu_sleep(), 0 == don't */
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int cpu_do_powersave;
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#ifdef CPU_ARM2
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struct cpu_functions arm2_cpufuncs = {
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/* CPU functions */
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arm2_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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(void *)cpufunc_nullop, /* control */
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NULL, /* domain */
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NULL, /* setttb */
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NULL, /* faultstatus */
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NULL, /* faultaddress */
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/* TLB functions */
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cpufunc_nullop, /* tlb_flushID */
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(void *)cpufunc_nullop, /* tlb_flushID_SE */
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cpufunc_nullop, /* tlb_flushI */
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(void *)cpufunc_nullop, /* tlb_flushI_SE */
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cpufunc_nullop, /* tlb_flushD */
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(void *)cpufunc_nullop, /* tlb_flushD_SE */
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/* Cache operations */
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cpufunc_nullop, /* icache_sync_all */
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(void *) cpufunc_nullop, /* icache_sync_range */
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arm3_cache_flush, /* dcache_wbinv_all */
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(void *)cpufunc_nullop, /* dcache_wbinv_range */
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(void *)cpufunc_nullop, /* dcache_inv_range */
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(void *)cpufunc_nullop, /* dcache_wb_range */
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cpufunc_nullop, /* idcache_wbinv_all */
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(void *)cpufunc_nullop, /* idcache_wbinv_range */
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/* Other functions */
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cpufunc_nullop, /* flush_prefetchbuf */
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cpufunc_nullop, /* drain_writebuf */
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cpufunc_nullop, /* flush_brnchtgt_C */
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(void *)cpufunc_nullop, /* flush_brnchtgt_E */
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(void *)cpufunc_nullop, /* sleep */
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/* Soft functions */
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early_abort_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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NULL, /* context_switch */
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(void *)cpufunc_nullop /* cpu setup */
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};
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#endif /* CPU_ARM2 */
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#ifdef CPU_ARM250
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struct cpu_functions arm250_cpufuncs = {
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/* CPU functions */
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arm250_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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(void *)cpufunc_nullop, /* control */
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NULL, /* domain */
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NULL, /* setttb */
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NULL, /* faultstatus */
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NULL, /* faultaddress */
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/* TLB functions */
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cpufunc_nullop, /* tlb_flushID */
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(void *)cpufunc_nullop, /* tlb_flushID_SE */
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cpufunc_nullop, /* tlb_flushI */
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(void *)cpufunc_nullop, /* tlb_flushI_SE */
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cpufunc_nullop, /* tlb_flushD */
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(void *)cpufunc_nullop, /* tlb_flushD_SE */
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/* Cache operations */
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cpufunc_nullop, /* icache_sync_all */
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(void *) cpufunc_nullop, /* icache_sync_range */
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arm3_cache_flush, /* dcache_wbinv_all */
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(void *)cpufunc_nullop, /* dcache_wbinv_range */
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(void *)cpufunc_nullop, /* dcache_inv_range */
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(void *)cpufunc_nullop, /* dcache_wb_range */
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cpufunc_nullop, /* idcache_wbinv_all */
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(void *)cpufunc_nullop, /* idcache_wbinv_range */
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/* Other functions */
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cpufunc_nullop, /* flush_prefetchbuf */
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cpufunc_nullop, /* drain_writebuf */
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cpufunc_nullop, /* flush_brnchtgt_C */
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(void *)cpufunc_nullop, /* flush_brnchtgt_E */
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(void *)cpufunc_nullop, /* sleep */
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/* Soft functions */
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early_abort_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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NULL, /* context_switch */
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(void *)cpufunc_nullop /* cpu setup */
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};
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#endif /* CPU_ARM250 */
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#ifdef CPU_ARM3
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struct cpu_functions arm3_cpufuncs = {
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/* CPU functions */
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@ -897,7 +1013,7 @@ get_cachetype_cp15()
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* reserved ID register is encountered, the System Control
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* processor returns the value of the main ID register.
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*/
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if (ctype == cpufunc_id())
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if (ctype == cpu_id())
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goto out;
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if ((ctype & CPU_CT_S) == 0)
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@ -991,7 +1107,7 @@ static void
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get_cachetype_table()
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{
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int i;
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u_int32_t cpuid = cpufunc_id();
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u_int32_t cpuid = cpu_id();
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for (i = 0; cachetab[i].ct_cpuid != 0; i++) {
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if (cachetab[i].ct_cpuid == (cpuid & CPU_ID_CPU_MASK)) {
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@ -1021,14 +1137,32 @@ get_cachetype_table()
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int
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set_cpufuncs()
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{
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cputype = cpufunc_id();
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cputype &= CPU_ID_CPU_MASK;
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if (cputype != 0) {
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cputype = cpufunc_id();
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cputype &= CPU_ID_CPU_MASK;
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}
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/*
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* NOTE: cpu_do_powersave defaults to off. If we encounter a
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* CPU type where we want to use it by default, then we set it.
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*/
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#ifdef CPU_ARM2
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if (cputype == CPU_ID_ARM2) {
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cpufuncs = arm2_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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get_cachetype_table();
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return 0;
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}
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#endif /* CPU_ARM2 */
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#ifdef CPU_ARM250
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if (cputype == CPU_ID_ARM250) {
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cpufuncs = arm250_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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get_cachetype_table();
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return 0;
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}
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#endif
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#ifdef CPU_ARM3
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if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
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(cputype & 0x00000f00) == 0x00000300) {
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@ -1322,6 +1456,22 @@ set_cpufuncs()
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return(ARCHITECTURE_NOT_PRESENT);
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}
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#ifdef CPU_ARM2
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u_int arm2_id(void)
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{
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return CPU_ID_ARM2;
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}
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#endif /* CPU_ARM2 */
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#ifdef CPU_ARM250
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u_int arm250_id(void)
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{
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return CPU_ID_ARM250;
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}
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#endif /* CPU_ARM250 */
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/*
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* Fixup routines for data and prefetch aborts.
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*
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.h,v 1.39 2007/03/04 13:42:51 bjh21 Exp $ */
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/* $NetBSD: cpufunc.h,v 1.40 2007/03/04 14:47:18 bjh21 Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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@ -197,6 +197,7 @@ extern u_int cputype;
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#define cpu_setup(a) cpufuncs.cf_setup(a)
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int set_cpufuncs (void);
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int set_cpufuncs_id (u_int);
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#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
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#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
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@ -210,6 +211,14 @@ void cpufunc_domains (u_int);
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u_int cpufunc_faultstatus (void);
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u_int cpufunc_faultaddress (void);
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#ifdef CPU_ARM2
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u_int arm2_id (void);
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#endif /* CPU_ARM2 */
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#ifdef CPU_ARM250
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u_int arm250_id (void);
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#endif
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#ifdef CPU_ARM3
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u_int arm3_control (u_int, u_int);
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void arm3_cache_flush (void);
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