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/* $NetBSD: iocreg.h,v 1.1 2001/05/11 03:18:57 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Rafal K. Boni
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_HPC_IOCREG_H_
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#define _ARCH_SGIMIPS_HPC_IOCREG_H_
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/*
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* IOC1/2 memory map.
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*
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* The IOC1/2 is connected to the HPC#0, PBus channel 6, so these registers
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* are based from the external register window for PBus channel 6 on HPC#0.
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*
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* XXX: define register values as well as their offsets.
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*
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*/
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#define IOC_PLP_REGS 0x00000000 /* Parallel port registers */
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#define IOC_PLP_REGS_SIZE 0x0000002c
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#define IOC_PLP_DATA 0x00000000 /* Data register */
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#define IOC_PLP_CTL 0x00000004 /* Control register */
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#define IOC_PLP_STAT 0x00000008 /* Status register */
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#define IOC_PLP_DMACTL 0x0000000c /* DMA control register */
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#define IOC_PLP_INTSTAT 0x00000010 /* Interrupt status register */
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#define IOC_PLP_INTMASK 0x00000014 /* Interrupt mask register */
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#define IOC_PLP_TIMER1 0x00000018 /* Timer 1 register */
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#define IOC_PLP_TIMER2 0x0000001c /* Timer 2 register */
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#define IOC_PLP_TIMER3 0x00000020 /* Timer 3 register */
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#define IOC_PLP_TIMER4 0x00000024 /* Timer 4 register */
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#define IOC_SERIAL_REGS 0x00000030 /* Serial port registers */
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#define IOC_SERIAL_REGS_SIZE 0x0000000c
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#define IOC_SERIAL_PORT1_CMD 0x00000000 /* Port 1 command transfer */
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#define IOC_SERIAL_PORT1_DATA 0x00000004 /* Port 1 data transfer */
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#define IOC_SERIAL_PORT2_CMD 0x00000008 /* Port 2 command transfer */
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#define IOC_SERIAL_PORT2_DATA 0x0000000c /* Port 2 data transfer */
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#define IOC_KB_REGS 0x00000040 /* Keyboard/mouse registers */
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#define IOC_KB_REGS_SIZE 0x00000008
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#define IOC_MISC_REGS 0x00000048 /* Misc. IOC regs */
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#define IOC_MISC_REGS_SIZE 0x00000034
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#define IOC_MISC_GCSEL 0x00000000 /* General control select */
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#define IOC_MISC_GCREG 0x00000004 /* General control register */
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#define IOC_MISC_PANEL 0x00000008 /* Front Panel register */
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/* UNUSED 0x0000000c */
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#define IOC_MISC_SYSID 0x00000010 /* System ID register */
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/* UNUSED 0x00000014 */
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#define IOC_MISC_READ 0x00000018 /* Read register */
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/* UNUSED 0x0000001c */
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#define IOC_MISC_DMASEL 0x00000020 /* DMA select register */
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/* UNUSED 0x00000024 */
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#define IOC_MISC_RESET 0x00000028 /* Reset register */
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/* UNUSED 0x0000002c */
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#define IOC_MISC_WRITE 0x00000030 /* Write register */
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/* UNUSED 0x00000034 */
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/* The same misc IOC registers as above, but as offsets from IOC base */
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#define IOC_GCSEL 0x00000048 /* General control select */
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#define IOC_GCREG 0x0000004c /* General control register */
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#define IOC_PANEL 0x00000050 /* Front Panel register */
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/* UNUSED 0x00000054 */
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#define IOC_SYSID 0x00000058 /* System ID register */
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/* UNUSED 0x0000005c */
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#define IOC_READ 0x00000060 /* Read register */
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/* UNUSED 0x00000064 */
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#define IOC_DMASEL 0x00000068 /* DMA select register */
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/* UNUSED 0x0000006c */
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#define IOC_RESET 0x00000070 /* Reset register */
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/* UNUSED 0x00000074 */
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#define IOC_WRITE 0x00000078 /* Write register */
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/* UNUSED 0x0000007c */
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#define IOC_INT3_REGS 0x00000080 /* INT3 interrupt controller */
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#define IOC_INT3_REGS_SIZE 0x0000002c
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/* See int23regs.h for INT2/3 register layout */
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#endif /* _ARCH_SGIMIPS_HPC_IOCREG_H_ */
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