Missing part of CS Mk. III changes
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/* $NetBSD: siopreg.h,v 1.8 1996/04/21 21:12:37 veego Exp $ */
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/* $NetBSD: siopreg.h,v 1.9 1999/03/09 20:31:34 is Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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@ -45,50 +45,172 @@
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*/
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typedef struct {
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#ifndef ARCH_720
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/*00*/ volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */
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/*01*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */
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/*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */
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/*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */
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/*04*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */
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/*05*/ volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */
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/*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */
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/*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */
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/*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */
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/*09*/ volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */
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/*0a*/ volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */
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/*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */
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/*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */
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/*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */
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/*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */
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/*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */
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/*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */
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/*14*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */
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/*15*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */
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/*16*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */
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/*17*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */
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/*18*/ volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */
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/*19*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */
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/*1a*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */
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/*1b*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */
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/*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */
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/*20*/ volatile unsigned char siop_lcrc; /* rw: LCRC value */
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/*21*/ volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */
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/*22*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */
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/*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */
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/*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */
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/*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */
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/*26*/ volatile unsigned char siop_dbc1;
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/*27*/ volatile unsigned char siop_dbc0;
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/*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */
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/*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */
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/*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */
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/*34*/ volatile unsigned long siop_scratch; /* rw: Scratch Register */
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/*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */
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/*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */
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/*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */
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/*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */
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/*3c*/ volatile unsigned long siop_adder;
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#else
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/*00*/ volatile unsigned char siop_scntl3; /* rw: SCSI control reg 3 */
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/*01*/ volatile unsigned char siop_scntl2; /* rw: SCSI control reg 2 */
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/*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */
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/*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */
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/*04*/ volatile unsigned char siop_gpreg; /* rw: SCSI */
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/*05*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */
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/*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */
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/*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */
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/*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */
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/*09*/ volatile unsigned char siop_ssid; /* ro: SCSI */
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/*0a*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */
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/*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */
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/*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */
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/*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */
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/*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */
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/*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */
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/*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */
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/*14*/ volatile unsigned char siop_14_; /* ??: */
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/*15*/ volatile unsigned char siop_15_; /* ??: */
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/*16*/ volatile unsigned char siop_16_; /* ??: */
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/*17*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */
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/*18*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */
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/*19*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */
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/*1a*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */
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/*1b*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */
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/*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */
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/*20*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */
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/*21*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */
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/*22*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */
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/*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */
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/*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */
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/*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */
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/*26*/ volatile unsigned char siop_dbc1;
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/*27*/ volatile unsigned char siop_dbc0;
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/*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */
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/*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */
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/*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */
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/*34*/ volatile unsigned long siop_scratcha; /* rw: Scratch Register A */
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/*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */
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/*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */
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/*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */
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/*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */
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/*3c*/ volatile unsigned long siop_adder;
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/*40*/ volatile unsigned short siop_sist; /* rw: SCSI Interrupt Status */
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#define SIOP_SIST_STO 0x0400 /* timeout (select) */
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#define SIOP_SIST_GEN 0x0200 /* timeout (general) */
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#define SIOP_SIST_MA 0x0080 /* phase mispatch */
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#define SIOP_SIST_SGE 0x0008 /* gross error (over/underflow) */
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#define SIOP_SIST_UDC 0x0004 /* unexpected disconnect */
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#define SIOP_SIST_PAR 0x0001 /* scsi parity error */
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/*42*/ volatile unsigned short siop_sien; /* rw: SCSI Interrupt Enable */
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#define SIOP_SIEN_STO 0x0400 /* timeout (select) */
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#define SIOP_SIEN_GEN 0x0200 /* timeout (general) */
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#define SIOP_SIEN_MA 0x0080 /* phase mispatch */
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#define SIOP_SIEN_SGE 0x0008 /* gross error (over/underflow) */
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#define SIOP_SIEN_UDC 0x0004 /* unexpected disconnect */
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#define SIOP_SIEN_RST 0x0002 /* scsi bus reset */
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#define SIOP_SIEN_PAR 0x0001 /* scsi parity error */
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/*44*/ volatile unsigned char siop_gpcntl; /* rw: SCSI */
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/*45*/ volatile unsigned char siop_macntl; /* rw: SCSI */
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/*46*/ volatile unsigned char siop_swide; /* rw: SCSI */
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/*47*/ volatile unsigned char siop_slpar; /* rw: SCSI */
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/*48*/ volatile unsigned short siop_respid; /* rw: SCSI Reselect-IDS */
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/*4a*/ volatile unsigned char siop_stime1; /* rw: SCSI */
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/*4b*/ volatile unsigned char siop_stime0; /* rw: SCSI */
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/*4c*/ volatile unsigned char siop_stest3; /* ro: Chip test register 3 */
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/*4d*/ volatile unsigned char siop_stest2; /* ro: Chip test register 2 */
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/*4e*/ volatile unsigned char siop_stest1; /* ro: Chip test register 1 */
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/*4f*/ volatile unsigned char siop_stest0; /* ro: Chip test register 0 */
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/*50*/ volatile unsigned char siop_50_; /* rw: SCSI */
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/*51*/ volatile unsigned char siop_stest4; /* rw: SCSI */
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/*52*/ volatile unsigned short siop_sidl; /* ro: SCSI Input Data Latch */
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/*54*/ volatile unsigned short siop_54_; /* rw: SCSI */
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/*56*/ volatile unsigned short siop_sodl; /* rw: SCSI Output Data Latch */
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/*58*/ volatile unsigned short siop_58_; /* rw: SCSI */
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/*5a*/ volatile unsigned short siop_sbdl; /* ro: SCSI Bus Data Lines */
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/*5c*/ volatile unsigned long siop_scratchb; /* rw: Scratch Register B */
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#endif
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} siop_regmap_t;
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typedef volatile siop_regmap_t *siop_regmap_p;
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@ -121,6 +243,7 @@ typedef volatile siop_regmap_t *siop_regmap_p;
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/* Scsi interrupt enable register (sien) */
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#ifndef ARCH_720
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#define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */
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#define SIOP_SIEN_FCMP 0x40 /* Function Complete */
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#define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */
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@ -129,6 +252,7 @@ typedef volatile siop_regmap_t *siop_regmap_p;
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#define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */
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#define SIOP_SIEN_RST 0x02 /* RST asserted */
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#define SIOP_SIEN_PAR 0x01 /* Parity Error */
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#endif
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/* Scsi chip ID (scid) */
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@ -142,8 +266,13 @@ typedef volatile siop_regmap_t *siop_regmap_p;
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Period = TCP * (4 + XFERP )
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TCP = 1 + CLK + 1..2;
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*/
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#ifndef ARCH_720
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#define SIOP_SXFER_MO 0x0f /* Synch Max Offset */
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# define SIOP_MAX_OFFSET 8
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#else
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#define SIOP_SXFER_MO 0x1f /* Synch Max Offset */
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# define SIOP_MAX_OFFSET 16
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#endif
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/* Scsi output data latch register (sodl) */
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@ -1,4 +1,4 @@
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/* $NetBSD: siopvar.h,v 1.16 1998/11/19 21:44:37 thorpej Exp $ */
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/* $NetBSD: siopvar.h,v 1.17 1999/03/09 20:31:34 is Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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@ -127,8 +127,13 @@ struct siop_softc {
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u_char sc_istat;
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u_char sc_dstat;
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#ifndef ARCH_720
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u_char sc_sstat0;
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#endif
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u_char sc_sstat1;
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#ifdef ARCH_720
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u_short sc_sist;
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#endif
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u_long sc_intcode;
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struct scsipi_link sc_link; /* proto for sub devices */
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struct scsipi_adapter sc_adapter;
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@ -142,7 +147,7 @@ struct siop_softc {
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nexus_list;
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struct siop_acb *sc_nexus; /* current command */
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#define SIOP_NACB 8
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#define SIOP_NACB 16
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struct siop_acb *sc_acb; /* the real command blocks */
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struct siop_tinfo sc_tinfo[8];
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@ -151,15 +156,19 @@ struct siop_softc {
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u_char sc_ctest7;
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u_short sc_tcp[4];
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u_char sc_flags;
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u_char sc_sien;
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u_char sc_dien;
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u_char sc_minsync;
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#ifndef ARCH_720
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u_char sc_sien;
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#else
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u_short sc_sien;
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#endif
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/* one for each target */
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struct syncpar {
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u_char state;
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u_char sxfer;
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u_char sbcl;
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} sc_sync[8];
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} sc_sync[16];
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};
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/* sc_flags */
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@ -196,12 +205,26 @@ struct siop_softc {
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#define STS_INTERMED 0x10 /* Intermediate status sent */
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#define STS_EXT 0x80 /* Extended status valid */
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#ifdef ARCH_720
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void siopng_minphys __P((struct buf *bp));
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int siopng_scsicmd __P((struct scsipi_xfer *));
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void siopnginitialize __P((struct siop_softc *));
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void siopngintr __P((struct siop_softc *));
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void siopng_dump_registers __P((struct siop_softc *));
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#ifdef DEBUG
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void siopng_dump __P((struct siop_softc *));
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#endif
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#else
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void siop_minphys __P((struct buf *bp));
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int siop_scsicmd __P((struct scsipi_xfer *));
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void siopinitialize __P((struct siop_softc *));
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void siopintr __P((struct siop_softc *));
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void siop_dump_registers __P((struct siop_softc *));
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#ifdef DEBUG
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void siop_dump __P((struct siop_softc *));
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#endif
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#endif
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#endif /* _SIOPVAR_H */
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