Rewrote most of the code to make the 8245 I2C module finally work.
Tested with a RICOH RS5C372 RTC on a Synology DS-101g+ and Kurobox. Reviewed by <nisimura>.
This commit is contained in:
phx
parent
2731b5ff2f
commit
5bc4943cb2
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@ -1,4 +1,4 @@
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/* $NetBSD: eumbvar.h,v 1.4 2008/04/28 20:23:34 martin Exp $ */
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/* $NetBSD: eumbvar.h,v 1.5 2010/05/12 17:20:24 phx Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -38,5 +38,3 @@ struct eumb_attach_args {
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};
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int eumbcnattach(bus_space_tag_t, int, int, int, int, int);
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void iic_bootstrap_init(void);
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int iic_bootstrap_read(int, int, uint8_t *, size_t);
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@ -1,4 +1,4 @@
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/* $NetBSD: iic_eumb.c,v 1.7 2009/03/18 10:22:35 cegger Exp $ */
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/* $NetBSD: iic_eumb.c,v 1.8 2010/05/12 17:20:24 phx Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: iic_eumb.c,v 1.7 2009/03/18 10:22:35 cegger Exp $");
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__KERNEL_RCSID(0, "$NetBSD: iic_eumb.c,v 1.8 2010/05/12 17:20:24 phx Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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@ -45,31 +45,31 @@ __KERNEL_RCSID(0, "$NetBSD: iic_eumb.c,v 1.7 2009/03/18 10:22:35 cegger Exp $");
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#include <sandpoint/sandpoint/eumbvar.h>
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void iic_bootstrap_init(void);
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int iic_bootstrap_read(int, int, uint8_t *, size_t);
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static int iic_eumb_match(struct device *, struct cfdata *, void *);
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static void iic_eumb_attach(struct device *, struct device *, void *);
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struct iic_eumb_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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struct i2c_controller sc_i2c;
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kmutex_t sc_buslock;
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bool sc_start;
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};
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static int iic_eumb_match(struct device *, struct cfdata *, void *);
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static void iic_eumb_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(iic_eumb, sizeof(struct iic_eumb_softc),
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iic_eumb_match, iic_eumb_attach, NULL, NULL);
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static int motoi2c_acquire_bus(void *, int);
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static int motoi2c_acquire_bus(void *, int);
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static void motoi2c_release_bus(void *, int);
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static int motoi2c_send_start(void *, int);
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static int motoi2c_send_stop(void *, int);
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static int motoi2c_initiate_xfer(void *, uint16_t, int);
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static int motoi2c_read_byte(void *, uint8_t *, int);
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static int motoi2c_write_byte(void *, uint8_t, int);
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static void waitxferdone(int);
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static int motoi2c_send_start(void *, int);
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static int motoi2c_send_stop(void *, int);
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static int motoi2c_initiate_xfer(void *, uint16_t, int);
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static int motoi2c_read_byte(void *, uint8_t *, int);
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static int motoi2c_write_byte(void *, uint8_t, int);
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static int motoi2c_waitxferdone(struct iic_eumb_softc *);
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struct iic_eumb_softc *iic_eumb;
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static struct i2c_controller motoi2c = {
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.ic_acquire_bus = motoi2c_acquire_bus,
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@ -103,9 +103,11 @@ static struct i2c_controller motoi2c = {
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#define SR_RXAK 0x01 /* 1 to indicate receive has completed */
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#define I2CDR 0x0010 /* data */
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#define CSR_READ(r) in8rb(0xfc003000 + (r))
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#define CSR_WRITE(r,v) out8rb(0xfc003000 + (r), (v))
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#define CSR_WRITE4(r,v) out32rb(0xfc003000 + (r), (v))
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#define I2C_READ(r) bus_space_read_4(sc->sc_iot, sc->sc_ioh, (r))
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#define I2C_WRITE(r,v) bus_space_write_4(sc->sc_iot, sc->sc_ioh, (r), (v))
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#define I2C_SETCLR(r, s, c) \
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, (r), \
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(bus_space_read_4(sc->sc_iot, sc->sc_ioh, (r)) | (s)) & ~(c))
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static int found;
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@ -119,74 +121,48 @@ iic_eumb_match(struct device *parent, struct cfdata *cf, void *aux)
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static void
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iic_eumb_attach(struct device *parent, struct device *self, void *aux)
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{
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struct iic_eumb_softc *sc = (void *)self;
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struct eumb_attach_args *eaa = aux;
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struct iic_eumb_softc *sc;
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struct eumb_attach_args *eaa;
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struct i2cbus_attach_args iba;
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bus_space_handle_t ioh;
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sc = (struct iic_eumb_softc *)self;
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eaa = aux;
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found = 1;
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printf("\n");
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bus_space_map(eaa->eumb_bt, 0x3000, 0x20, 0, &ioh);
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mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
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iic_eumb = sc;
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sc->sc_i2c = motoi2c;
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sc->sc_i2c.ic_cookie = sc;
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sc->sc_iot = eaa->eumb_bt;
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sc->sc_ioh = ioh;
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sc->sc_start = false;
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memset(&iba, 0, sizeof(iba));
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iba.iba_tag = &sc->sc_i2c;
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iic_bootstrap_init();
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#if 0
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/* not yet */
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I2C_WRITE(I2CCR, 0); /* reset before changing anything */
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I2C_WRITE(I2CFDR, 0x1031); /* DFFSR=0x10, divider 3072 (0x31) */
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I2C_WRITE(I2CADR, 0x7f << 1); /* our slave address is 0x7f */
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I2C_WRITE(I2CSR, 0); /* clear status flags */
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I2C_WRITE(I2CCR, CR_MEN); /* enable the I2C module */
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config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print);
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/* we never attempt to use I2C interrupt */
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intr_establish(16 + 16, IST_LEVEL, IPL_BIO, iic_intr, sc);
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#if 0
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/* we do not use the I2C interrupt yet */
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intr_establish(16 + 16, IST_LEVEL, IPL_BIO, motoic2_intr, sc);
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#endif
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}
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void
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iic_bootstrap_init(void)
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{
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CSR_WRITE(I2CCR, 0);
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CSR_WRITE4(I2CFDR, 0x1031); /* XXX magic XXX */
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CSR_WRITE(I2CADR, 0);
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CSR_WRITE(I2CSR, 0);
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CSR_WRITE(I2CCR, CR_MEN);
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}
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int
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iic_bootstrap_read(int i2caddr, int offset, uint8_t *rvp, size_t len)
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{
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i2c_addr_t addr;
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uint8_t cmdbuf[1];
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if (motoi2c_acquire_bus(&motoi2c, I2C_F_POLL) != 0)
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return -1;
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while (len) {
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addr = i2caddr + (offset >> 8);
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cmdbuf[0] = offset & 0xff;
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if (iic_exec(&motoi2c, I2C_OP_READ_WITH_STOP, addr,
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cmdbuf, 1, rvp, 1, I2C_F_POLL)) {
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motoi2c_release_bus(&motoi2c, I2C_F_POLL);
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return -1;
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}
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len--;
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rvp++;
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offset++;
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}
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motoi2c_release_bus(&motoi2c, I2C_F_POLL);
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return 0;
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}
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static int
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motoi2c_acquire_bus(void *v, int flags)
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{
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struct iic_eumb_softc *sc = v;
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struct iic_eumb_softc *sc;
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if (flags & I2C_F_POLL)
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return 0;
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sc = v;
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mutex_enter(&sc->sc_buslock);
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return 0;
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}
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static void
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motoi2c_release_bus(void *v, int flags)
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{
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struct iic_eumb_softc *sc = v;
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struct iic_eumb_softc *sc;
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if (flags & I2C_F_POLL)
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return;
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sc = v;
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mutex_exit(&sc->sc_buslock);
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}
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static int
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motoi2c_send_start(void *v, int flags)
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{
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int loop = 10;
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struct iic_eumb_softc *sc;
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int timo;
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sc = v;
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if (!sc->sc_start && (I2C_READ(I2CSR) & SR_MBB) != 0) {
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/* wait for bus becoming available */
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timo = 100;
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do
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DELAY(10);
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while (--timo > 0 && (I2C_READ(I2CSR) & SR_MBB) != 0);
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if (timo == 0) {
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#ifdef DEBUG
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printf("%s: bus is busy\n", __func__);
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#endif
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return -1;
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}
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}
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else if (sc->sc_start &&
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(I2C_READ(I2CSR) & (SR_MIF | SR_MAL)) == SR_MIF) {
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sc->sc_start = false;
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#ifdef DEBUG
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printf("%s: lost the bus\n", __func__);
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#endif
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return -1;
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}
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/* reset interrupt and arbitration-lost flags */
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I2C_SETCLR(I2CSR, 0, SR_MIF | SR_MAL);
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if (!sc->sc_start) {
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/* generate start condition */
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I2C_SETCLR(I2CCR, CR_MSTA | CR_MTX, CR_TXAK | CR_RSTA);
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sc->sc_start = true;
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} else /* repeated start, we still own the bus */
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I2C_SETCLR(I2CCR, CR_RSTA | CR_MTX, CR_TXAK);
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CSR_WRITE(I2CSR, 0);
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CSR_WRITE(I2CCR, CR_MEN);
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do {
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DELAY(1);
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} while (--loop > 0 && (CSR_READ(I2CSR) & SR_MBB));
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return 0;
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}
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static int
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motoi2c_send_stop(void *v, int flags)
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{
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struct iic_eumb_softc *sc;
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CSR_WRITE(I2CCR, CR_MEN);
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sc = v;
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I2C_SETCLR(I2CCR, 0, CR_MSTA | CR_RSTA | CR_TXAK);
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sc->sc_start = false;
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DELAY(100);
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return 0;
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}
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static int
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motoi2c_initiate_xfer(void *v, i2c_addr_t addr, int flags)
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{
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int rd_req;
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struct iic_eumb_softc *sc;
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rd_req = !!(flags & I2C_F_READ);
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CSR_WRITE(I2CCR, CR_MIEN | CR_MEN | CR_MSTA | CR_MTX);
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CSR_WRITE(I2CDR, (addr << 1) | rd_req);
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if (flags & I2C_F_STOP)
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CSR_WRITE(I2CCR, CR_MIEN | CR_MEN | CR_TXAK);
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waitxferdone(SR_MIF);
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return 0;
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sc = v;
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/* start condition */
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if (motoi2c_send_start(v, flags) != 0)
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return -1;
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/* send target address and transfer direction */
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I2C_WRITE(I2CDR, (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0));
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if (motoi2c_waitxferdone(sc) == 0) {
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if (flags & I2C_F_READ) {
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/* clear TX mode */
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I2C_SETCLR(I2CCR, 0, CR_MTX);
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/*
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* A dummy read is required to start with
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* receiving bytes.
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*/
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(void)I2C_READ(I2CDR);
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}
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if (flags & I2C_F_STOP)
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return motoi2c_send_stop(v, flags);
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return 0;
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}
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return -1;
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}
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static int
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motoi2c_read_byte(void *v, uint8_t *bytep, int flags)
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{
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int last_byte, send_stop;
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struct iic_eumb_softc *sc;
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sc = v;
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/* wait for next byte */
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if (motoi2c_waitxferdone(sc) != 0)
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return -1;
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/* no TX-acknowledge for next byte */
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if (flags & I2C_F_LAST)
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I2C_SETCLR(I2CCR, CR_TXAK, 0);
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*bytep = I2C_READ(I2CDR);
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/*
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* To make the TXAK take effect we have to receive another
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* byte, which will be discarded.
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*/
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if (flags & I2C_F_LAST) {
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(void)motoi2c_waitxferdone(sc); /* ignore RXAK flag */
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if (flags & I2C_F_STOP)
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(void)motoi2c_send_stop(v, flags);
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(void)I2C_READ(I2CDR);
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} else if (flags & I2C_F_STOP)
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return motoi2c_send_stop(v, flags);
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last_byte = (flags & I2C_F_LAST) != 0;
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send_stop = (flags & I2C_F_STOP) != 0;
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if (last_byte)
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CSR_WRITE(I2CCR, CR_MIEN | CR_MEN | CR_MSTA | CR_TXAK);
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if (send_stop)
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CSR_WRITE(I2CCR, CR_MIEN | CR_MEN | CR_TXAK);
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waitxferdone(SR_MIF);
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*bytep = CSR_READ(I2CDR);
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return 0;
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}
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static int
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motoi2c_write_byte(void *v, uint8_t byte, int flags)
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{
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int send_stop;
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struct iic_eumb_softc *sc;
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sc = v;
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I2C_WRITE(I2CDR, byte);
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DELAY(10);
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if (motoi2c_waitxferdone(sc) != 0)
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return -1;
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if (flags & I2C_F_STOP)
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return motoi2c_send_stop(v, flags);
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send_stop = (flags & I2C_F_STOP) != 0;
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if (send_stop)
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CSR_WRITE(I2CCR, CR_MEN);
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CSR_WRITE(I2CDR, byte);
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waitxferdone(SR_MIF);
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return 0;
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}
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/* busy waiting for byte data transfer completion */
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static void
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waitxferdone(int cond)
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static int
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motoi2c_waitxferdone(struct iic_eumb_softc *sc)
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{
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int timo, sr;
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uint32_t sr;
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int timo;
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timo = 100;
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timo = 1000;
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do {
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DELAY(1);
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sr = CSR_READ(I2CSR);
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} while (--timo > 0 && (sr & cond) == 0);
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sr &= ~cond;
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CSR_WRITE(I2CSR, sr);
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sr = I2C_READ(I2CSR);
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DELAY(10);
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} while (--timo > 0 && (sr & SR_MIF) == 0);
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#ifdef DEBUG
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if (timo == 0)
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printf("%s: timeout\n", __func__);
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if (sr & SR_RXAK)
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printf("%s: missing rx ack\n", __func__);
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#endif
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I2C_SETCLR(I2CSR, 0, sr);
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return (timo == 0 || (sr & SR_RXAK) != 0) ? -1 : 0;
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}
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