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Regen.

This commit is contained in:
msaitoh 2018-03-02 06:41:18 +00:00
parent 04c91ad0e7
commit 5b82bfebd0
2 changed files with 4089 additions and 3976 deletions
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40
sys/dev/pci/pcidevs.h
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@ -1,10 +1,10 @@
/* $NetBSD: pcidevs.h,v 1.1308 2018/02/24 14:06:27 mlelstv Exp $ */
/* $NetBSD: pcidevs.h,v 1.1309 2018/03/02 06:41:18 msaitoh Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: pcidevs,v 1.1316 2018/02/24 14:05:46 mlelstv Exp
* NetBSD: pcidevs,v 1.1317 2018/03/02 06:40:31 msaitoh Exp
*/
/*
@ -4194,6 +4194,42 @@
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_DDRIO_C 0x2fdb /* Xeon E5 v3 IMC DDRIO */
#define PCI_PRODUCT_INTEL_WIFI_LINK_3165_1 0x3165 /* Dual Band Wireless AC 3165 */
#define PCI_PRODUCT_INTEL_WIFI_LINK_3165_2 0x3166 /* Dual Band Wireless AC 3165 */
#define PCI_PRODUCT_INTEL_GLK_IGD_1 0x3184 /* UHD Graphics 605 */
#define PCI_PRODUCT_INTEL_GLK_IGD_2 0x3185 /* UHD Graphics 600 */
#define PCI_PRODUCT_INTEL_GLK_DPTF 0x318c /* Gemini Lake DPTF */
#define PCI_PRODUCT_INTEL_GLK_GNA 0x3190 /* Gemini Lake GNA */
#define PCI_PRODUCT_INTEL_GLK_P2SB 0x3192 /* Gemini Lake Primary to SideBand Bridge */
#define PCI_PRODUCT_INTEL_GLK_PMC 0x3194 /* Gemini Lake PMC */
#define PCI_PRODUCT_INTEL_GLK_FASTSPI 0x3196 /* Gemini Lake Fast SPI */
#define PCI_PRODUCT_INTEL_GLK_ESPI 0x3197 /* Gemini Lake eSPI */
#define PCI_PRODUCT_INTEL_GLK_HDA 0x3198 /* Gemini Lake HD Audio */
#define PCI_PRODUCT_INTEL_GLK_ISH 0x31a2 /* Gemini Lake Integrated Sensor Hub */
#define PCI_PRODUCT_INTEL_GLK_XHCI 0x31a8 /* Gemini Lake USB Host (xHCI) */
#define PCI_PRODUCT_INTEL_GLK_XDCI 0x31aa /* Gemini Lake USB Device (xDCI) */
#define PCI_PRODUCT_INTEL_GLK_I2C_0 0x31ac /* Gemini Lake I2C 0 */
#define PCI_PRODUCT_INTEL_GLK_I2C_1 0x31ae /* Gemini Lake I2C 1 */
#define PCI_PRODUCT_INTEL_GLK_I2C_2 0x31b0 /* Gemini Lake I2C 2 */
#define PCI_PRODUCT_INTEL_GLK_I2C_3 0x31b2 /* Gemini Lake I2C 3 */
#define PCI_PRODUCT_INTEL_GLK_I2C_4 0x31b4 /* Gemini Lake I2C 4 */
#define PCI_PRODUCT_INTEL_GLK_I2C_5 0x31b6 /* Gemini Lake I2C 5 */
#define PCI_PRODUCT_INTEL_GLK_I2C_6 0x31b8 /* Gemini Lake I2C 6 */
#define PCI_PRODUCT_INTEL_GLK_I2C_7 0x31ba /* Gemini Lake I2C 7 */
#define PCI_PRODUCT_INTEL_GLK_UART_0 0x31bc /* Gemini Lake UART 0 */
#define PCI_PRODUCT_INTEL_GLK_UART_2 0x31c0 /* Gemini Lake UART 2 */
#define PCI_PRODUCT_INTEL_GLK_SPI 0x31c2 /* Gemini Lake SPI */
#define PCI_PRODUCT_INTEL_GLK_EMMC 0x31cc /* Gemini Lake eMMC */
#define PCI_PRODUCT_INTEL_GLK_SMB 0x31d4 /* Gemini Lake SMBus */
#define PCI_PRODUCT_INTEL_GLK_PCIE_4 0x31d6 /* Gemini Lake PCIe x2 */
#define PCI_PRODUCT_INTEL_GLK_PCIE_5 0x31d7 /* Gemini Lake PCIe x2 */
#define PCI_PRODUCT_INTEL_GLK_PCIE_0 0x31d8 /* Gemini Lake PCIe x4 */
#define PCI_PRODUCT_INTEL_GLK_PCIE_1 0x31d9 /* Gemini Lake PCIe x4 */
#define PCI_PRODUCT_INTEL_GLK_PCIE_2 0x31da /* Gemini Lake PCIe x4 */
#define PCI_PRODUCT_INTEL_GLK_PCIE_3 0x31db /* Gemini Lake PCIe x4 */
#define PCI_PRODUCT_INTEL_GLK_CNVI 0x31dc /* Gemini Lake CNVi */
#define PCI_PRODUCT_INTEL_GLK_SATA 0x31e3 /* Gemini Lake SATA */
#define PCI_PRODUCT_INTEL_GLK_LPC 0x31e8 /* Gemini Lake LPC */
#define PCI_PRODUCT_INTEL_GLK_SSRAM 0x31ec /* Gemini Lake Shared SRAM */
#define PCI_PRODUCT_INTEL_GLK_HB 0x31f0 /* Gemini Lake Host Bridge */
#define PCI_PRODUCT_INTEL_31244 0x3200 /* 31244 Serial ATA Controller */
#define PCI_PRODUCT_INTEL_82855PM_DDR 0x3340 /* 82855PM MCH Host Controller */
#define PCI_PRODUCT_INTEL_82855PM_AGP 0x3341 /* 82855PM Host-AGP Bridge */

8025
sys/dev/pci/pcidevs_data.h
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