Backend for MTRRs on PII and up or Athlon CPUs. The only other implementation
is on the AMD K6.
This commit is contained in:
fvdl
parent
86b144f468
commit
5b0257ed49
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@ -0,0 +1,680 @@
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/* $NetBSD: mtrr_i686.c,v 1.1 2001/09/10 10:14:21 fvdl Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Bill Sommerfeld
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_multiprocessor.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/lock.h>
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#include <sys/user.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/specialreg.h>
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#include <machine/cpufunc.h>
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#include <machine/mtrr.h>
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extern paddr_t avail_end;
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static void i686_mtrr_reload(int);
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static void i686_mtrr_init_cpu(struct cpu_info *);
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static void i686_mtrr_reload_cpu(struct cpu_info *);
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static void i686_mtrr_clean(struct proc *p);
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static int i686_mtrr_set(struct mtrr *, int *n, struct proc *p, int flags);
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static int i686_mtrr_get(struct mtrr *, int *n, struct proc *p, int flags);
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static void i686_mtrr_dump(const char *tag);
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static int i686_mtrr_validate(struct mtrr *, struct proc *p);
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static void i686_soft2raw(void);
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static void i686_raw2soft(void);
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static void i686_mtrr_commit(void);
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static int i686_mtrr_setone(struct mtrr *, struct proc *p);
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static struct mtrr_state
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mtrr_raw[] = {
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{ MSR_MTRRphysBase0 },
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{ MSR_MTRRphysMask0 },
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{ MSR_MTRRphysBase1 },
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{ MSR_MTRRphysMask1 },
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{ MSR_MTRRphysBase2 },
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{ MSR_MTRRphysMask2 },
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{ MSR_MTRRphysBase3 },
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{ MSR_MTRRphysMask3 },
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{ MSR_MTRRphysBase4 },
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{ MSR_MTRRphysMask4 },
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{ MSR_MTRRphysBase5 },
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{ MSR_MTRRphysMask5 },
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{ MSR_MTRRphysBase6 },
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{ MSR_MTRRphysMask6 },
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{ MSR_MTRRphysBase7 },
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{ MSR_MTRRphysMask7 },
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{ MSR_MTRRfix64K_00000 },
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{ MSR_MTRRfix16K_80000 },
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{ MSR_MTRRfix16K_A0000 },
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{ MSR_MTRRfix4K_C0000 },
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{ MSR_MTRRfix4K_C8000 },
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{ MSR_MTRRfix4K_D0000 },
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{ MSR_MTRRfix4K_D8000 },
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{ MSR_MTRRfix4K_E0000 },
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{ MSR_MTRRfix4K_E8000 },
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{ MSR_MTRRfix4K_F0000 },
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{ MSR_MTRRfix4K_F8000 },
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{ MSR_MTRRdefType }
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};
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static const int nmtrr_raw = sizeof(mtrr_raw)/sizeof(mtrr_raw[0]);
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static struct mtrr_state *mtrr_var_raw;
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static struct mtrr_state *mtrr_fixed_raw;
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static struct mtrr *mtrr_fixed;
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static struct mtrr *mtrr_var;
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struct mtrr_funcs i686_mtrr_funcs = {
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i686_mtrr_init_cpu,
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i686_mtrr_reload_cpu,
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i686_mtrr_clean,
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i686_mtrr_set,
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i686_mtrr_get,
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i686_mtrr_commit,
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i686_mtrr_dump
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};
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#ifdef MULTIPROCESSOR
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static volatile uint32_t mtrr_waiting;
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#endif
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static uint64_t i686_mtrr_cap;
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static void
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i686_mtrr_dump(const char *tag)
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{
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int i;
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for (i = 0; i < nmtrr_raw; i++)
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printf("%s: %x: %016llx\n",
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tag, mtrr_raw[i].msraddr, rdmsr(mtrr_raw[i].msraddr));
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}
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/*
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* The Intel Archicture Software Developer's Manual volume 3 (systems
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* programming) section 9.12.8 describes a simple 15-step process for
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* updating the MTRR's on all processors on a multiprocessor system.
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* If synch is nonzero, assume we're being called from an IPI handler,
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* and synchronize with all running processors.
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*/
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/*
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* 1. Broadcast to all processor to execute the following code sequence.
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*/
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static void
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i686_mtrr_reload(int synch)
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{
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int i;
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uint32_t cr0, cr3, cr4;
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uint32_t origcr0, origcr4;
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#ifdef MULTIPROCESSOR
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uint32_t mymask = 1 << cpu_number();
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#endif
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/*
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* 2. Disable interrupts
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*/
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disable_intr();
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#ifdef MULTIPROCESSOR
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if (synch) {
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/*
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* 3. Wait for all processors to reach this point.
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*/
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i386_atomic_setbits_l(&mtrr_waiting, mymask);
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while (mtrr_waiting != cpus_running)
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DELAY(10);
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}
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#endif
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/*
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* 4. Enter the no-fill cache mode (set the CD flag in CR0 to 1 and
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* the NW flag to 0)
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*/
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origcr0 = cr0 = rcr0();
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cr0 |= CR0_CD;
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cr0 &= ~CR0_NW;
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lcr0(cr0);
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/*
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* 5. Flush all caches using the WBINVD instruction.
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*/
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wbinvd();
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/*
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* 6. Clear the PGE flag in control register CR4 (if set).
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*/
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origcr4 = cr4 = rcr4();
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cr4 &= ~CR4_PGE;
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lcr4(cr4);
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/*
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* 7. Flush all TLBs (execute a MOV from control register CR3
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* to another register and then a move from that register back
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* to CR3)
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*/
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cr3 = rcr3();
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lcr3(cr3);
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/*
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* 8. Disable all range registers (by clearing the E flag in
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* register MTRRdefType. If only variable ranges are being
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* modified, software may clear the valid bits for the
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* affected register pairs instead.
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*/
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/* disable MTRRs (E = 0) */
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wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_I686_ENABLE_MASK);
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/*
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* 9. Update the MTRR's
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*/
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for (i = 0; i < nmtrr_raw; i++) {
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uint64_t val = mtrr_raw[i].msrval;
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uint32_t addr = mtrr_raw[i].msraddr;
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if (addr == MSR_MTRRdefType)
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val &= ~MTRR_I686_ENABLE_MASK;
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wrmsr(addr, val);
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}
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/*
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* 10. Enable all range registers (by setting the E flag in
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* register MTRRdefType). If only variable-range registers
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* were modified and their individual valid bits were cleared,
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* then set the valid bits for the affected ranges instead.
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*/
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wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_I686_ENABLE_MASK);
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/*
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* 11. Flush all caches and all TLB's a second time. (repeat
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* steps 5, 7)
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*/
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wbinvd();
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lcr3(cr3);
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/*
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* 12. Enter the normal cache mode to reenable caching (set the CD and
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* NW flags in CR0 to 0)
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*/
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lcr0(origcr0);
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/*
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* 13. Set the PGE flag in control register CR4, if previously
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* cleared.
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*/
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lcr4(origcr4);
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#ifdef MULTIPROCESSOR
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if (synch) {
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/*
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* 14. Wait for all processors to reach this point.
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*/
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i386_atomic_clearbits_l(&mtrr_waiting, mymask);
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while (mtrr_waiting != 0)
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DELAY(10);
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}
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#endif
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/*
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* 15. Enable interrupts.
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*/
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enable_intr();
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}
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static void
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i686_mtrr_reload_cpu(struct cpu_info *ci)
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{
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i686_mtrr_reload(1);
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}
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void
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i686_mtrr_init_first(void)
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{
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int i;
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for (i = 0; i < nmtrr_raw; i++)
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mtrr_raw[i].msrval = rdmsr(mtrr_raw[i].msraddr);
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i686_mtrr_cap = rdmsr(MSR_MTRRcap);
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#if 0
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mtrr_dump("init mtrr");
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#endif
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mtrr_fixed = (struct mtrr *)
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malloc(MTRR_I686_NFIXED_SOFT * sizeof (struct mtrr), M_TEMP,
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M_NOWAIT);
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if (mtrr_fixed == NULL)
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panic("can't allocate fixed MTRR array");
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mtrr_var = (struct mtrr *)
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malloc(MTRR_I686_NVAR * sizeof (struct mtrr), M_TEMP, M_NOWAIT);
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if (mtrr_var == NULL)
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panic("can't allocate variable MTRR array");
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mtrr_var_raw = &mtrr_raw[0];
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mtrr_fixed_raw = &mtrr_raw[MTRR_I686_NVAR * 2];
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i686_raw2soft();
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}
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static void
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i686_raw2soft(void)
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{
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int i, j, idx;
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struct mtrr *mtrrp;
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uint64_t base, mask;
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for (i = 0; i < MTRR_I686_NVAR; i++) {
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mtrrp = &mtrr_var[i];
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mtrrp->flags = 0;
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mtrrp->owner = 0;
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mask = mtrr_var_raw[i * 2 + 1].msrval;
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if (!mtrr_valid(mask))
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continue;
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base = mtrr_var_raw[i * 2].msrval;
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mtrrp->base = mtrr_base(base);
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mtrrp->type = mtrr_type(base);
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mtrrp->len = mtrr_len(mask);
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mtrrp->flags |= MTRR_VALID;
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}
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idx = 0;
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base = 0;
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for (i = 0; i < MTRR_I686_NFIXED_64K; i++, idx++) {
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mask = mtrr_fixed_raw[idx].msrval;
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for (j = 0; j < 8; j++) {
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mtrrp = &mtrr_fixed[idx * 8 + j];
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mtrrp->owner = 0;
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mtrrp->flags = MTRR_FIXED | MTRR_VALID;
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mtrrp->base = base;
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mtrrp->len = 65536;
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mtrrp->type = mask & 0xff;
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mask >>= 8;
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base += 65536;
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}
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}
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for (i = 0; i < MTRR_I686_NFIXED_16K; i++, idx++) {
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mask = mtrr_fixed_raw[idx].msrval;
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for (j = 0; j < 8; j++) {
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mtrrp = &mtrr_fixed[idx * 8 + j];
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mtrrp->owner = 0;
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mtrrp->flags = MTRR_FIXED | MTRR_VALID;
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mtrrp->base = base;
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mtrrp->len = 16384;
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mtrrp->type = mask & 0xff;
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mask >>= 8;
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base += 16384;
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}
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}
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for (i = 0; i < MTRR_I686_NFIXED_4K; i++, idx++) {
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mask = mtrr_fixed_raw[idx].msrval;
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for (j = 0; j < 8; j++) {
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mtrrp = &mtrr_fixed[idx * 8 + j];
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mtrrp->owner = 0;
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mtrrp->flags = MTRR_FIXED | MTRR_VALID;
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mtrrp->base = base;
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mtrrp->len = 4096;
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mtrrp->type = mask & 0xff;
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mask >>= 8;
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base += 4096;
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}
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}
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}
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static void
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i686_soft2raw(void)
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{
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int i, idx, j;
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uint64_t val;
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struct mtrr *mtrrp;
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for (i = 0; i < MTRR_I686_NVAR; i++) {
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mtrrp = &mtrr_var[i];
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mtrr_var_raw[i * 2].msrval = mtrr_base_value(mtrrp);
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mtrr_var_raw[i * 2 + 1].msrval = mtrr_mask_value(mtrrp);
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if (mtrrp->flags & MTRR_VALID)
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mtrr_var_raw[i * 2 + 1].msrval |= MTRR_I686_MASK_VALID;
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}
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idx = 0;
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for (i = 0; i < MTRR_I686_NFIXED_64K; i++, idx++) {
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val = 0;
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for (j = 0; j < 8; j++) {
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mtrrp = &mtrr_fixed[idx];
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val |= ((uint64_t)mtrrp->type << (j << 3));
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}
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mtrr_fixed_raw[idx].msrval = val;
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}
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for (i = 0; i < MTRR_I686_NFIXED_16K; i++, idx++) {
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val = 0;
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for (j = 0; j < 8; j++) {
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mtrrp = &mtrr_fixed[idx];
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val |= ((uint64_t)mtrrp->type << (j << 3));
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}
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mtrr_fixed_raw[idx].msrval = val;
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}
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for (i = 0; i < MTRR_I686_NFIXED_4K; i++, idx++) {
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val = 0;
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for (j = 0; j < 8; j++) {
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mtrrp = &mtrr_fixed[idx];
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val |= ((uint64_t)mtrrp->type << (j << 3));
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}
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mtrr_fixed_raw[idx].msrval = val;
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}
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}
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static void
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i686_mtrr_init_cpu(struct cpu_info *ci)
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{
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i686_mtrr_reload(0);
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#if 0
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mtrr_dump(ci->ci_dev->dv_xname);
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#endif
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}
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static int
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i686_mtrr_validate(struct mtrr *mtrrp, struct proc *p)
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{
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uint64_t high;
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/*
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* Must be at least page-aligned.
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*/
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if (mtrrp->base & 0xfff || mtrrp->len & 0xfff || mtrrp->len == 0)
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return EINVAL;
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/*
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* Private mappings are bound to a process.
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*/
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if (p == NULL && (mtrrp->flags & MTRR_PRIVATE))
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return EINVAL;
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high = mtrrp->base + mtrrp->len;
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/*
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* Check for bad types.
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*/
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if (mtrrp->type == MTRR_TYPE_UNDEF1 || mtrrp->type == MTRR_TYPE_UNDEF2
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|| mtrrp->type > MTRR_TYPE_WB)
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return EINVAL;
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/*
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* Only use fixed ranges < 1M.
|
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*/
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if ((mtrrp->flags & MTRR_FIXED) && high > 0x100000)
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return EINVAL;
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/*
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* Check for the right alignment and size for fixed ranges.
|
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* The requested range may span several actual MTRRs, but
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* it must be properly aligned.
|
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*/
|
||||
if (mtrrp->flags & MTRR_FIXED) {
|
||||
if (mtrrp->base < MTRR_I686_16K_START) {
|
||||
if (mtrrp->base != 0)
|
||||
return EINVAL;
|
||||
} else if (mtrrp->base < MTRR_I686_4K_START) {
|
||||
if (mtrrp->base != MTRR_I686_16K_START ||
|
||||
mtrrp->base != MTRR_I686_16K_START + 16384)
|
||||
return EINVAL;
|
||||
} else {
|
||||
if (mtrrp->len != 4096)
|
||||
return EINVAL;
|
||||
}
|
||||
if (high < MTRR_I686_16K_START)
|
||||
return EINVAL;
|
||||
else if (high < MTRR_I686_4K_START && (high & 0x3fff))
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Try to find a non-conflicting match on physical MTRRs for the
|
||||
* requested range. For fixed ranges, more than one actual MTRR
|
||||
* may be used.
|
||||
*/
|
||||
static int
|
||||
i686_mtrr_setone(struct mtrr *mtrrp, struct proc *p)
|
||||
{
|
||||
int i, error;
|
||||
struct mtrr *lowp, *highp, *mp, *freep;
|
||||
uint64_t low, high, curlow, curhigh;
|
||||
|
||||
/*
|
||||
* If explicitly requested, or if the range lies below 1M,
|
||||
* try the fixed range MTRRs.
|
||||
*/
|
||||
if (mtrrp->flags & MTRR_FIXED ||
|
||||
(mtrrp->base + mtrrp->len) < 0x100000) {
|
||||
lowp = highp = NULL;
|
||||
for (i = 0; i < MTRR_I686_NFIXED_SOFT; i++) {
|
||||
if (mtrr_fixed[i].base == mtrrp->base + mtrrp->len) {
|
||||
highp = &mtrr_fixed[i];
|
||||
break;
|
||||
}
|
||||
if (mtrr_fixed[i].base == mtrrp->base) {
|
||||
lowp = &mtrr_fixed[i];
|
||||
highp = &mtrr_fixed[i + 1];
|
||||
continue;
|
||||
}
|
||||
}
|
||||
error = 0;
|
||||
for (mp = lowp; mp < highp; mp++) {
|
||||
if ((mp->flags & MTRR_PRIVATE) && p != NULL
|
||||
&& p->p_pid != mp->owner) {
|
||||
error = EBUSY;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (error != 0) {
|
||||
if (mtrrp->flags & MTRR_FIXED)
|
||||
return error;
|
||||
} else {
|
||||
for (mp = lowp; mp < highp; mp++) {
|
||||
/*
|
||||
* Can't invalidate fixed ranges, so
|
||||
* just reset the 'private' flag,
|
||||
* making the range available for
|
||||
* changing again.
|
||||
*/
|
||||
if (!(mtrrp->flags & MTRR_VALID)) {
|
||||
mp->flags &= ~MTRR_PRIVATE;
|
||||
continue;
|
||||
}
|
||||
mp->type = mtrrp->type;
|
||||
if (mtrrp->flags & MTRR_PRIVATE) {
|
||||
mp->flags |= MTRR_PRIVATE;
|
||||
mp->owner = p->p_pid;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Try one of the variable range registers.
|
||||
* XXX could be more sophisticated here by merging ranges.
|
||||
*/
|
||||
low = mtrrp->base;
|
||||
high = low + mtrrp->len;
|
||||
freep = NULL;
|
||||
for (i = 0; i < MTRR_I686_NVAR; i++) {
|
||||
if (!(mtrr_var[i].flags & MTRR_VALID)) {
|
||||
freep = &mtrr_var[i];
|
||||
continue;
|
||||
}
|
||||
curlow = mtrr_var[i].base;
|
||||
curhigh = curlow + mtrr_var[i].len;
|
||||
if (low == curlow && high == curhigh &&
|
||||
(!(mtrr_var[i].flags & MTRR_PRIVATE) ||
|
||||
mtrr_var[i].owner == p->p_pid)) {
|
||||
freep = &mtrr_var[i];
|
||||
break;
|
||||
}
|
||||
if (((high >= curlow && high <= curhigh) ||
|
||||
(low >= curlow && low <= curhigh)) &&
|
||||
((mtrr_var[i].type != mtrrp->type) ||
|
||||
((mtrr_var[i].flags & MTRR_PRIVATE) &&
|
||||
mtrr_var[i].owner != p->p_pid)))
|
||||
return EBUSY;
|
||||
}
|
||||
if (freep == NULL)
|
||||
return EBUSY;
|
||||
mtrrp->flags &= ~MTRR_CANTSET;
|
||||
*freep = *mtrrp;
|
||||
freep->owner = mtrrp->flags & MTRR_PRIVATE ? p->p_pid : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
i686_mtrr_clean(struct proc *p)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MTRR_I686_NFIXED_SOFT; i++) {
|
||||
if ((mtrr_fixed[i].flags & MTRR_PRIVATE) &&
|
||||
(mtrr_fixed[i].owner == p->p_pid))
|
||||
mtrr_fixed[i].flags &= ~MTRR_PRIVATE;
|
||||
}
|
||||
|
||||
for (i = 0; i < MTRR_I686_NVAR; i++) {
|
||||
if ((mtrr_var[i].flags & MTRR_PRIVATE) &&
|
||||
(mtrr_var[i].owner == p->p_pid))
|
||||
mtrr_var[i].flags &= ~(MTRR_PRIVATE | MTRR_VALID);
|
||||
}
|
||||
|
||||
i686_mtrr_commit();
|
||||
}
|
||||
|
||||
static int
|
||||
i686_mtrr_set(struct mtrr *mtrrp, int *n, struct proc *p, int flags)
|
||||
{
|
||||
int i, error;
|
||||
struct mtrr mtrr;
|
||||
|
||||
for (i = 0; i < *n; i++) {
|
||||
if (flags & MTRR_GETSET_USER) {
|
||||
error = copyin(&mtrrp[i], &mtrr, sizeof mtrr);
|
||||
if (error != 0)
|
||||
break;
|
||||
} else
|
||||
mtrr = mtrrp[i];
|
||||
error = i686_mtrr_validate(&mtrr, p);
|
||||
if (error != 0)
|
||||
break;
|
||||
error = i686_mtrr_setone(&mtrr, p);
|
||||
if (error != 0)
|
||||
break;
|
||||
if (mtrr.flags & MTRR_PRIVATE)
|
||||
p->p_md.md_flags |= MDP_USEDMTRR;
|
||||
}
|
||||
*n = i;
|
||||
return error;
|
||||
}
|
||||
|
||||
static int
|
||||
i686_mtrr_get(struct mtrr *mtrrp, int *n, struct proc *p, int flags)
|
||||
{
|
||||
int idx, i, error;
|
||||
|
||||
if (mtrrp == NULL) {
|
||||
*n = MTRR_I686_NFIXED_SOFT + MTRR_I686_NVAR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (idx = i = 0; i < MTRR_I686_NFIXED_SOFT && idx < *n; idx++, i++) {
|
||||
if (flags & MTRR_GETSET_USER) {
|
||||
error = copyout(&mtrr_fixed[i], &mtrrp[idx],
|
||||
sizeof *mtrrp);
|
||||
if (error != 0)
|
||||
break;
|
||||
} else
|
||||
memcpy(&mtrrp[idx], &mtrr_fixed[i], sizeof *mtrrp);
|
||||
}
|
||||
if (error != 0) {
|
||||
*n = idx;
|
||||
return error;
|
||||
}
|
||||
|
||||
for (i = 0; i < MTRR_I686_NVAR && idx < *n; idx++, i++) {
|
||||
if (flags & MTRR_GETSET_USER) {
|
||||
error = copyout(&mtrr_var[i], &mtrrp[idx],
|
||||
sizeof *mtrrp);
|
||||
if (error != 0)
|
||||
break;
|
||||
} else
|
||||
memcpy(&mtrrp[idx], &mtrr_var[i], sizeof *mtrrp);
|
||||
}
|
||||
*n = idx;
|
||||
return error;
|
||||
}
|
||||
|
||||
static void
|
||||
i686_mtrr_commit(void)
|
||||
{
|
||||
i686_soft2raw();
|
||||
i686_mtrr_reload(1);
|
||||
}
|
||||
Loading…
Reference in New Issue