Implement gpio framework for the Samsung Exynos series.
Note that only the Exynos4 gpio registers are defined now and provision is taken to allow for seamlessness adding of Exynos5 values.
This commit is contained in:
reinoud
parent
aaace33d0e
commit
5ad8bd1845
@ -264,6 +264,7 @@
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EXYNOS4##p##_##n##_OFFSET, 0x10000
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static const struct exyo_locators exynos4_locators[] = {
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{ "exyogpio", 0, 0, NOPORT, NOINTR, 0 },
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{ "mct", OFFANDSIZE(,MCT), NOPORT, IRQ_G0_IRQ, 0 },
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{ "exyowdt", OFFANDSIZE(,WDT), NOPORT, IRQ_WDT, 0 },
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{ "sscom", OFFANDSIZE(,UART0), 0, IRQ_UART0, 0 },
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791
sys/arch/arm/samsung/exynos_gpio.c
Normal file
791
sys/arch/arm/samsung/exynos_gpio.c
Normal file
@ -0,0 +1,791 @@
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Reinoud Zandijk
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_exynos.h"
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#include "opt_arm_debug.h"
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#include "gpio.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.1 2014/05/09 21:49:43 reinoud Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kmem.h>
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#include <arm/samsung/exynos_reg.h>
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#include <arm/samsung/exynos_io.h>
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#include <arm/samsung/exynos_intr.h>
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#include <sys/gpio.h>
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#include <dev/gpio/gpiovar.h>
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static int exynos_gpio_match(device_t, cfdata_t, void *);
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static void exynos_gpio_attach(device_t, device_t, void *);
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static int exynos_gpio_pin_read(void *, int);
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static void exynos_gpio_pin_write(void *, int, int);
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static void exynos_gpio_pin_ctl(void *, int, int);
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struct exynos_gpio_pin_cfg {
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uint32_t cfg;
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uint32_t pud;
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uint32_t drv;
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uint32_t conpwd;
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uint32_t pudpwd;
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};
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struct exynos_gpio_pin_group {
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const char grp_name[6];
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const bus_addr_t grp_core_offset;
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const uint8_t grp_bits;
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uint8_t grp_pin_mask;
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uint8_t grp_pin_inuse_mask;
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bus_space_handle_t grp_bsh;
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struct exynos_gpio_pin_cfg grp_cfg;
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struct gpio_chipset_tag grp_gc_tag;
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};
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#define GPIO_OFFSET(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o))
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#define GPIO_GRP(v, s, o, n, b) \
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{ \
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.grp_name = #n, \
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.grp_core_offset = GPIO_OFFSET(v,s,o), \
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.grp_bits = b,\
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}
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#ifdef EXYNOS4
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/*
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* Exynos 4412 contains 304 multi-functional input/output port pins and 164
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* memory port pins. There are 37 general port groups and two memory port
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* groups. They are:
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*
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* GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow
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* control, and/or 2xI2C
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*
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* GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM
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*
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* GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C,
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* and/or SPI
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*
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* GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI
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*
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* GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F,
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* HSI, and/ or Trace I/F
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*
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* GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F
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*
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* GPJ0, GPJ1: 13 in/out ports-CAM I/F
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*
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* GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC
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* (8-bit MMC)), and/or GPS debugging I/F
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*
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* GPL0, GPL1: 11 in/out ports-GPS I/F
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*
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* GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F
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*
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* GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad
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* I/F
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*
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* GPZ: 7 in/out ports-low Power I2S and/or PCM
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*
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* GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One
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* NAND)
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*
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* GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information
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* about EBI configuration, refer to Chapter 5, and 6)
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*
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* MP1_0-MP1_9: 78 DRAM1 ports. NOTE: GPIO registers does not control these
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* ports.
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*
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* MP2_0-MP2_9: 78 DRAM2 ports. NOTE: GPIO registers does not control these
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* ports.
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*
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* ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK
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*
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* ETC7, ETC8 : 4 clock port for C2C
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*
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*/
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static struct exynos_gpio_pin_group exynos4_pin_groups[] = {
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GPIO_GRP(4, LEFT, 0x0000, GPA0, 8),
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GPIO_GRP(4, LEFT, 0x0020, GPA1, 6),
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GPIO_GRP(4, LEFT, 0x0040, GPB, 8),
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GPIO_GRP(4, LEFT, 0x0060, GPC0, 5),
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GPIO_GRP(4, LEFT, 0x0080, GPC1, 5),
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GPIO_GRP(4, LEFT, 0x00A0, GPD0, 4),
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GPIO_GRP(4, LEFT, 0x00C0, GPD1, 4),
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GPIO_GRP(4, LEFT, 0x0180, GPF0, 8),
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GPIO_GRP(4, LEFT, 0x01A0, GPF1, 8),
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GPIO_GRP(4, LEFT, 0x01C0, GPF2, 8),
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GPIO_GRP(4, LEFT, 0x01E0, GPF3, 8),
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GPIO_GRP(4, LEFT, 0x0240, GPJ0, 8),
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GPIO_GRP(4, LEFT, 0x0260, GPJ1, 5),
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/* EXTINT skipped */
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GPIO_GRP(4, RIGHT, 0x0040, GPK0, 8),
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GPIO_GRP(4, RIGHT, 0x0060, GPK1, 8),
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GPIO_GRP(4, RIGHT, 0x0080, GPK2, 7),
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GPIO_GRP(4, RIGHT, 0x00A0, GPK3, 7),
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GPIO_GRP(4, RIGHT, 0x00C0, GPL0, 7),
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GPIO_GRP(4, RIGHT, 0x00E0, GPL1, 2),
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GPIO_GRP(4, RIGHT, 0x0100, GPL2, 8),
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GPIO_GRP(4, RIGHT, 0x0120, GPY0, 6),
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GPIO_GRP(4, RIGHT, 0x0140, GPY1, 4),
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GPIO_GRP(4, RIGHT, 0x0160, GPY2, 6),
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GPIO_GRP(4, RIGHT, 0x0180, GPY3, 8),
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GPIO_GRP(4, RIGHT, 0x01A0, GPY4, 8),
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GPIO_GRP(4, RIGHT, 0x01C0, GPY5, 8),
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GPIO_GRP(4, RIGHT, 0x01E0, GPY6, 8),
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/* ETC0, ETC6 skipped */
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GPIO_GRP(4, RIGHT, 0x0260, GPM0, 8),
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GPIO_GRP(4, RIGHT, 0x0280, GPM1, 7),
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GPIO_GRP(4, RIGHT, 0x02A0, GPM2, 5),
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GPIO_GRP(4, RIGHT, 0x02C0, GPM3, 8),
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GPIO_GRP(4, RIGHT, 0x02E0, GPM4, 8),
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/* EXTINT skipped */
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GPIO_GRP(4, RIGHT, 0x0C00, GPX0, 8),
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GPIO_GRP(4, RIGHT, 0x0C20, GPX1, 8),
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GPIO_GRP(4, RIGHT, 0x0C40, GPX2, 8),
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GPIO_GRP(4, RIGHT, 0x0C60, GPX3, 8),
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/* EXTINT skipped */
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GPIO_GRP(4, I2C0, 0x0000, GPZ, 8),
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/* EXTINT skipped */
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GPIO_GRP(4, C2C, 0x0000, GPV0, 8),
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GPIO_GRP(4, C2C, 0x0020, GPV1, 8),
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/* ETC7 skipped */
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GPIO_GRP(4, C2C, 0x0060, GPV2, 8),
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GPIO_GRP(4, C2C, 0x0080, GPV3, 8),
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/* ETC8 skipped */
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GPIO_GRP(4, C2C, 0x00C0, GPV4, 2),
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/* EXTINT skipped */
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};
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#endif
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#ifdef EXYNOS5
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static struct exynos_gpio_pin_group exynos5_pin_groups[] = {
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};
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#endif
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struct exynos_gpio_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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};
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/* force these structures in DATA segment */
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static struct exynos_gpio_pin_group *exynos_pin_groups = NULL;
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static int exynos_n_pin_groups = 0;
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static struct exynos_gpio_softc exynos_gpio_sc = {};
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CFATTACH_DECL_NEW(exynos_gpio, sizeof(struct exynos_gpio_softc),
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exynos_gpio_match, exynos_gpio_attach, NULL, NULL);
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static int
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exynos_gpio_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct exyo_attach_args * const exyoaa = aux;
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struct exyo_locators *loc = &exyoaa->exyo_loc;
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/* no locators expected */
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KASSERT(loc->loc_offset == 0);
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KASSERT(loc->loc_size == 0);
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KASSERT(loc->loc_port == EXYOCF_PORT_DEFAULT);
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/* there can only be one */
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if (exynos_gpio_sc.sc_dev != NULL)
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return 0;
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return 1;
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}
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#if NGPIO > 0
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static void
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exynos_gpio_config_pins(device_t self)
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{
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struct exynos_gpio_softc * const sc = &exynos_gpio_sc;
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struct exynos_gpio_pin_group *grp;
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struct gpiobus_attach_args gba;
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gpio_pin_t *pin, *pins;
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size_t pin_count = 0;
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int i, bit, mask, pincaps, data;
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/* find out how many pins we can offer */
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pin_count = 0;
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for (i = 0; i < exynos_n_pin_groups; i++) {
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grp = &exynos_pin_groups[i];
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mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask;
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pin_count += popcount32(mask);
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}
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/* if no pins available, don't proceed */
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if (pin_count == 0)
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return;
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/* allocate pin data */
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pins = kmem_zalloc(sizeof(gpio_pin_t) * pin_count, KM_SLEEP);
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KASSERT(pins);
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pincaps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
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GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN;
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/* add all pins */
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pin = pins;
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for (i = 0; i < exynos_n_pin_groups; i++) {
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grp = &exynos_pin_groups[i];
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mask = grp->grp_pin_mask & ~grp->grp_pin_inuse_mask;
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if (mask == 0)
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continue;
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gba.gba_gc = &grp->grp_gc_tag;
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gba.gba_pins = pin;
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data = bus_space_read_1(sc->sc_bst, grp->grp_bsh,
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EXYNOS_GPIO_DAT);
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for (bit = 0; mask != 0; mask >>= 1, data >>= 1, bit++) {
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if (mask & 1) {
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pin->pin_num = bit + (i << 3);
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pin->pin_caps = pincaps;
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pin->pin_flags = pincaps;
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pin->pin_state = (data & 1) != 0;
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pin++;
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}
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}
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gba.gba_npins = pin - gba.gba_pins;
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config_found_ia(self, "gpiobus", &gba, gpiobus_print);
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}
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}
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#endif
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static void
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exynos_gpio_attach(device_t parent, device_t self, void *aux)
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{
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struct exynos_gpio_softc * const sc = &exynos_gpio_sc;
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struct exyo_attach_args * const exyoaa = aux;
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struct exynos_gpio_pin_group *grp;
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prop_dictionary_t dict = device_properties(self);
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uint32_t nc;
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char scrap[16];
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int i;
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KASSERT(exynos_pin_groups);
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KASSERT(exynos_n_pin_groups);
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/* construct softc */
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sc->sc_dev = self;
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/* we use the core bushandle here */
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sc->sc_bst = exyoaa->exyo_core_bst;
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sc->sc_bsh = exyoaa->exyo_core_bsh;
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aprint_naive("\n");
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aprint_normal("\n");
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/* go trough all pin groups */
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for (i = 0; i < exynos_n_pin_groups; i++) {
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grp = &exynos_pin_groups[i];
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snprintf(scrap, sizeof(scrap), "nc-%s", grp->grp_name);
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if (prop_dictionary_get_uint32(dict, scrap, &nc)) {
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KASSERT((~grp->grp_pin_mask & nc) == 0);
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KASSERT((grp->grp_pin_inuse_mask & ~nc) == 0);
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grp->grp_pin_mask &= ~nc;
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}
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}
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#if NGPIO > 0
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config_defer(self, exynos_gpio_config_pins);
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#endif
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}
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/* pin access functions */
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static u_int
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exynos_gpio_get_pin_func(const struct exynos_gpio_pin_cfg *cfg, int pin)
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{
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const u_int shift = (pin & 7) << 4;
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return (cfg->cfg >> shift) & 0x0f;
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}
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static void
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exynos_gpio_set_pin_func(struct exynos_gpio_pin_cfg *cfg,
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int pin, int func)
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{
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const u_int shift = (pin & 7) << 4;
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cfg->cfg &= ~(0x0f << shift);
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cfg->cfg |= func << shift;
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}
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static void
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exynos_gpio_set_pin_pull(struct exynos_gpio_pin_cfg *cfg, int pin, int pull)
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{
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const u_int shift = (pin & 7) << 1;
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cfg->pud &= ~(0x3 << shift);
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cfg->pud |= pull << shift;
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}
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static int
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exynos_gpio_pin_read(void *cookie, int pin)
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{
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struct exynos_gpio_pin_group * const grp = cookie;
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KASSERT(pin < grp->grp_bits);
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return (bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh,
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EXYNOS_GPIO_DAT) >> pin) & 1;
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}
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static void
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exynos_gpio_pin_write(void *cookie, int pin, int value)
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{
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struct exynos_gpio_pin_group * const grp = cookie;
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int val;
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KASSERT(pin < grp->grp_bits);
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val = bus_space_read_1(exynos_gpio_sc.sc_bst, grp->grp_bsh,
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EXYNOS_GPIO_DAT);
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val &= ~__BIT(pin);
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if (value)
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val |= __BIT(pin);
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bus_space_write_1(exynos_gpio_sc.sc_bst, grp->grp_bsh,
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EXYNOS_GPIO_DAT, val);
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}
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static void
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exynos_gpio_update_cfg_regs(struct exynos_gpio_pin_group *grp,
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const struct exynos_gpio_pin_cfg *ncfg)
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{
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bus_space_tag_t bst = &exynos_bs_tag;
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if (grp->grp_cfg.cfg != ncfg->cfg) {
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bus_space_write_4(bst, grp->grp_bsh,
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EXYNOS_GPIO_CON, ncfg->cfg);
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grp->grp_cfg.cfg = ncfg->cfg;
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}
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if (grp->grp_cfg.pud != ncfg->pud) {
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bus_space_write_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_PUD, ncfg->pud);
|
||||
grp->grp_cfg.pud = ncfg->pud;
|
||||
}
|
||||
|
||||
/* the following attributes are not yet setable */
|
||||
#if 0
|
||||
if (grp->grp_cfg.drv != ncfg->drv) {
|
||||
bus_space_write_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_DRV, ncfg->drv);
|
||||
grp->grp_cfg.drv = ncfg->drv;
|
||||
}
|
||||
if (grp->grp_cfg.conpwd != ncfg->conpwd) {
|
||||
bus_space_write_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_CONPWD, ncfg->conpwd);
|
||||
grp->grp_cfg.conpwd = ncfg->conpwd;
|
||||
}
|
||||
if (grp->grp_cfg.pudpwd != ncfg->pudpwd) {
|
||||
bus_space_write_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_PUDPWD, ncfg->pudpwd);
|
||||
grp->grp_cfg.pudpwd = ncfg->pudpwd;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
exynos_gpio_pin_ctl(void *cookie, int pin, int flags)
|
||||
{
|
||||
struct exynos_gpio_pin_group * const grp = cookie;
|
||||
struct exynos_gpio_pin_cfg ncfg = grp->grp_cfg;
|
||||
int pull;
|
||||
|
||||
/* honour pullup requests */
|
||||
pull = EXYNOS_GPIO_PIN_FLOAT;
|
||||
if (flags & GPIO_PIN_PULLUP)
|
||||
pull = EXYNOS_GPIO_PIN_PULL_UP;
|
||||
if (flags & GPIO_PIN_PULLDOWN)
|
||||
pull = EXYNOS_GPIO_PIN_PULL_DOWN;
|
||||
exynos_gpio_set_pin_pull(&ncfg, pin, pull);
|
||||
|
||||
/* honour i/o */
|
||||
if (flags & GPIO_PIN_INPUT)
|
||||
exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_INPUT);
|
||||
if (flags & GPIO_PIN_OUTPUT)
|
||||
exynos_gpio_set_pin_func(&ncfg, pin, EXYNOS_GPIO_FUNC_OUTPUT);
|
||||
|
||||
/* update any config registers that changed */
|
||||
exynos_gpio_update_cfg_regs(grp, &ncfg);
|
||||
}
|
||||
|
||||
|
||||
bool
|
||||
exynos_gpio_pinset_available(const struct exynos_gpio_pinset *req)
|
||||
{
|
||||
struct exynos_gpio_pin_group *grp;
|
||||
int i, n, inuse;
|
||||
|
||||
KASSERT(req);
|
||||
|
||||
/* we need a pinset group */
|
||||
if (strlen(req->pinset_group) == 0)
|
||||
return false;
|
||||
|
||||
/* determine which group is requested */
|
||||
grp = NULL;
|
||||
for (i = 0; i < exynos_n_pin_groups; i++) {
|
||||
grp = &exynos_pin_groups[i];
|
||||
if (strcmp(req->pinset_group, grp->grp_name) == 0)
|
||||
break;
|
||||
}
|
||||
/* found? */
|
||||
if (i == exynos_n_pin_groups)
|
||||
return false;
|
||||
KASSERT(grp);
|
||||
|
||||
/* fail unconnected pins */
|
||||
if (req->pinset_mask & ~grp->grp_pin_mask)
|
||||
return false;
|
||||
|
||||
/* if none in use, they are available */
|
||||
if (req->pinset_mask & ~grp->grp_pin_inuse_mask)
|
||||
return true;
|
||||
|
||||
/* OK, so some are in use; now see if the request is compatible */
|
||||
inuse = req->pinset_mask & grp->grp_pin_inuse_mask;
|
||||
for (i = 0; inuse; i++, inuse >>= 1) {
|
||||
/* try to be smart by skipping zero's */
|
||||
n = ffs(inuse) -1;
|
||||
i += n;
|
||||
inuse >>= n;
|
||||
/* this pin is in use, check its usage */
|
||||
if (exynos_gpio_get_pin_func(&grp->grp_cfg, i) != req->pinset_func)
|
||||
return false;
|
||||
}
|
||||
|
||||
/* seems to be OK */
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *req)
|
||||
{
|
||||
struct exynos_gpio_pin_group *grp;
|
||||
struct exynos_gpio_pin_cfg ncfg;
|
||||
int i, n, todo;
|
||||
|
||||
KASSERT(req);
|
||||
KASSERT(exynos_gpio_pinset_available(req));
|
||||
|
||||
/* determine which group is requested */
|
||||
grp = NULL;
|
||||
for (i = 0; i < exynos_n_pin_groups; i++) {
|
||||
grp = &exynos_pin_groups[i];
|
||||
if (strcmp(req->pinset_group, grp->grp_name) == 0)
|
||||
break;
|
||||
}
|
||||
KASSERT(grp);
|
||||
|
||||
/* check if all the pins have the right function */
|
||||
if ((req->pinset_mask & ~grp->grp_pin_inuse_mask) == 0)
|
||||
return;
|
||||
|
||||
/* copy current config for update routine */
|
||||
ncfg = grp->grp_cfg;
|
||||
|
||||
/* update the function of each pin that is not in use */
|
||||
todo = req->pinset_mask & grp->grp_pin_inuse_mask;
|
||||
for (i = 0; todo; i++, todo >>= 1) {
|
||||
/* try to be smart by skipping zero's */
|
||||
n = ffs(todo) -1;
|
||||
i += n;
|
||||
todo >>= n;
|
||||
/* change the function of this pin */
|
||||
exynos_gpio_set_pin_func(&ncfg, i, req->pinset_func);
|
||||
}
|
||||
|
||||
/* update config registers */
|
||||
exynos_gpio_update_cfg_regs(grp, &ncfg);
|
||||
|
||||
/* mark pins in use */
|
||||
grp->grp_pin_inuse_mask |= req->pinset_mask;
|
||||
}
|
||||
|
||||
|
||||
/* XXXRPZ This release doesn't grock multiple usages! */
|
||||
void
|
||||
exynos_gpio_pinset_release(const struct exynos_gpio_pinset *req)
|
||||
{
|
||||
struct exynos_gpio_pin_group *grp;
|
||||
int i;
|
||||
|
||||
KASSERT(!exynos_gpio_pinset_available(req));
|
||||
|
||||
/* determine which group is requested */
|
||||
grp = NULL;
|
||||
for (i = 0; i < exynos_n_pin_groups; i++) {
|
||||
grp = &exynos_pin_groups[i];
|
||||
if (strcmp(req->pinset_group, grp->grp_name) == 0)
|
||||
break;
|
||||
}
|
||||
KASSERT(grp);
|
||||
|
||||
/* bluntly mark as not being in use */
|
||||
grp->grp_pin_inuse_mask &= ~req->pinset_mask;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* name convention :
|
||||
* pin = <func><groupname><pinnr>[<pud>]
|
||||
* func = '<' | '>'
|
||||
* pinnr = '['['0'-'7']']'
|
||||
* pud = 'F' | 'U' | 'D'
|
||||
*
|
||||
* example "<GPC1[0]", ">GPB[0]"
|
||||
*/
|
||||
|
||||
bool
|
||||
exynos_gpio_pin_reserve(const char *name, struct exynos_gpio_pindata *pd)
|
||||
{
|
||||
struct exynos_gpio_softc * const sc = &exynos_gpio_sc;
|
||||
struct exynos_gpio_pin_group *grp;
|
||||
struct exynos_gpio_pin_cfg ncfg;
|
||||
prop_dictionary_t dict = device_properties(sc->sc_dev);
|
||||
const char *pin_data;
|
||||
char grp_name[15], *pos;
|
||||
int func, pud, pinnr;
|
||||
int pi, i;
|
||||
|
||||
/* do we have a named pin description? */
|
||||
if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data))
|
||||
return false;
|
||||
|
||||
KASSERT(strlen(pin_data) < 10);
|
||||
if (!(pin_data[0] == '>' || pin_data[1] == '<')) {
|
||||
printf("%s: malformed pin data in '%s', missing direction\n",
|
||||
__func__, pin_data);
|
||||
return false;
|
||||
}
|
||||
|
||||
func = (pin_data[0] == '<') ?
|
||||
EXYNOS_GPIO_FUNC_INPUT : EXYNOS_GPIO_FUNC_OUTPUT;
|
||||
|
||||
/* find groupname */
|
||||
pi = 1; pos = grp_name;
|
||||
while (pin_data[pi] && pin_data[pi] != '[') {
|
||||
*pos++ = pin_data[pi++];
|
||||
}
|
||||
if (pin_data[pi] != '[') {
|
||||
printf("%s: malformed pin data in '%s', missing '['\n",
|
||||
__func__, pin_data);
|
||||
return false;
|
||||
}
|
||||
*pos++ = (char) 0;
|
||||
|
||||
/* skip '[' */
|
||||
pi++;
|
||||
if (!(pin_data[pi] >= '0' && pin_data[pi] <= '7')) {
|
||||
printf("%s: malformed pin data in '%s', bad pin number\n",
|
||||
__func__, pin_data);
|
||||
return false;
|
||||
}
|
||||
pinnr = pin_data[pi] - '0';
|
||||
|
||||
/* skip digit */
|
||||
pi++;
|
||||
if ((pin_data[pi] != ']')) {
|
||||
printf("%s: malformed pin data in '%s', missing end ']'\n",
|
||||
__func__, pin_data);
|
||||
return false;
|
||||
}
|
||||
|
||||
/* skip ']' */
|
||||
pi++;
|
||||
pud = EXYNOS_GPIO_PIN_FLOAT;
|
||||
switch (tolower(pin_data[pi])) {
|
||||
case (char) 0:
|
||||
break;
|
||||
case 'f':
|
||||
pud = EXYNOS_GPIO_PIN_FLOAT;
|
||||
break;
|
||||
case 'u':
|
||||
pud = EXYNOS_GPIO_PIN_PULL_UP;
|
||||
break;
|
||||
case 'd':
|
||||
pud = EXYNOS_GPIO_PIN_PULL_DOWN;
|
||||
break;
|
||||
default:
|
||||
printf("%s: malformed pin data in '%s', expecting "
|
||||
"optional pull up/down or float argument\n",
|
||||
__func__, pin_data);
|
||||
return false;
|
||||
}
|
||||
|
||||
/* determine which group is requested */
|
||||
grp = NULL;
|
||||
for (i = 0; i < exynos_n_pin_groups; i++) {
|
||||
grp = &exynos_pin_groups[i];
|
||||
if (strcmp(grp_name, grp->grp_name) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
/* found? */
|
||||
if (i >= exynos_n_pin_groups) {
|
||||
printf("%s: malformed pin data in '%s', "
|
||||
"no such pin group name\n",
|
||||
__func__, grp_name);
|
||||
return false;
|
||||
}
|
||||
KASSERT(grp);
|
||||
|
||||
KASSERT(pinnr < grp->grp_bits);
|
||||
KASSERT(grp->grp_pin_mask & __BIT(pinnr));
|
||||
KASSERT((grp->grp_pin_inuse_mask & __BIT(pinnr)) == 0);
|
||||
|
||||
/* update our pin configuration */
|
||||
ncfg = grp->grp_cfg;
|
||||
exynos_gpio_set_pin_func(&ncfg, pinnr, func);
|
||||
exynos_gpio_set_pin_pull(&ncfg, pinnr, pud);
|
||||
exynos_gpio_update_cfg_regs(grp, &ncfg);
|
||||
|
||||
grp->grp_pin_inuse_mask &= ~__BIT(pinnr);
|
||||
|
||||
pd->pd_gc = &grp->grp_gc_tag;
|
||||
pd->pd_pin = pinnr;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/* bootstrapping */
|
||||
void
|
||||
exynos_gpio_bootstrap(void)
|
||||
{
|
||||
bus_space_tag_t bst = &exynos_bs_tag;
|
||||
struct exynos_gpio_pin_group *grp;
|
||||
struct gpio_chipset_tag *gc_tag;
|
||||
int i, j, func, mask;
|
||||
|
||||
/* determine what we're running on */
|
||||
#ifdef EXYNOS4
|
||||
if (IS_EXYNOS4_P()) {
|
||||
exynos_pin_groups = exynos4_pin_groups;
|
||||
exynos_n_pin_groups = __arraycount(exynos4_pin_groups);
|
||||
}
|
||||
#endif
|
||||
#ifdef EXYNOS5
|
||||
if (IS_EXYNOS5_P()) {
|
||||
exynos_pin_groups = exynos5_pin_groups;
|
||||
exynos_n_pin_groups = __arraycount(exynos5_pin_groups);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef VERBOSE_INIT_ARM
|
||||
printf("gpio");
|
||||
#endif
|
||||
if (exynos_n_pin_groups == 0) {
|
||||
#ifdef VERBOSE_INIT_ARM
|
||||
printf(" (disabled)\n");
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef VERBOSE_INIT_ARM
|
||||
printf(" free");
|
||||
#endif
|
||||
/* init groups */
|
||||
for (i = 0; i < exynos_n_pin_groups; i++) {
|
||||
grp = &exynos_pin_groups[i];
|
||||
gc_tag = &grp->grp_gc_tag;
|
||||
|
||||
bus_space_subregion(&exynos_bs_tag, exynos_core_bsh,
|
||||
grp->grp_core_offset, EXYNOS_GPIO_GRP_SIZE,
|
||||
&grp->grp_bsh);
|
||||
grp->grp_pin_mask = __BIT(grp->grp_bits) - 1;
|
||||
grp->grp_pin_inuse_mask = 0;
|
||||
|
||||
gc_tag->gp_cookie = grp;
|
||||
gc_tag->gp_pin_read = exynos_gpio_pin_read;
|
||||
gc_tag->gp_pin_write = exynos_gpio_pin_write;
|
||||
gc_tag->gp_pin_ctl = exynos_gpio_pin_ctl;
|
||||
|
||||
/* read in our initial settings */
|
||||
grp->grp_cfg.cfg = bus_space_read_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_CON);
|
||||
grp->grp_cfg.pud = bus_space_read_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_PUD);
|
||||
grp->grp_cfg.drv = bus_space_read_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_DRV);
|
||||
grp->grp_cfg.conpwd = bus_space_read_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_CONPWD);
|
||||
grp->grp_cfg.pudpwd = bus_space_read_4(bst, grp->grp_bsh,
|
||||
EXYNOS_GPIO_PUDPWD);
|
||||
|
||||
/* count number of busy pins */
|
||||
for (j = 0, mask = 1;
|
||||
(mask & grp->grp_pin_mask) != 0;
|
||||
j++, mask <<= 1) {
|
||||
func = exynos_gpio_get_pin_func(&grp->grp_cfg, j);
|
||||
if (func > EXYNOS_GPIO_FUNC_INPUT) {
|
||||
grp->grp_pin_inuse_mask |= mask;
|
||||
}
|
||||
}
|
||||
#ifdef VERBOSE_INIT_ARM
|
||||
printf(" P%s = %d", grp->grp_name,
|
||||
popcount32(grp->grp_pin_mask & ~grp->grp_pin_inuse_mask));
|
||||
#endif
|
||||
}
|
||||
#ifdef VERBOSE_INIT_ARM
|
||||
printf("\n");
|
||||
#if 0
|
||||
/* enable this for default NC pins list generation */
|
||||
for (i = 0; i < exynos_n_pin_groups; i++) {
|
||||
grp = &exynos_pin_groups[i];
|
||||
printf("prop_dictionary_set_uint32(dict, \"nc-%s\", 0x%02x - 0x00);\n",
|
||||
grp->grp_name, grp->grp_pin_mask);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_soc.c,v 1.7 2014/04/29 16:47:10 reinoud Exp $ */
|
||||
/* $NetBSD: exynos_soc.c,v 1.8 2014/05/09 21:49:43 reinoud Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
@ -33,7 +33,7 @@
|
||||
#define _ARM32_BUS_DMA_PRIVATE
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.7 2014/04/29 16:47:10 reinoud Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.8 2014/05/09 21:49:43 reinoud Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/bus.h>
|
||||
@ -234,6 +234,9 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
|
||||
|
||||
/* init bus dma tags */
|
||||
exynos_dma_bootstrap(physmem * PAGE_SIZE);
|
||||
|
||||
/* init gpio structures */
|
||||
exynos_gpio_bootstrap();
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: exynos_var.h,v 1.4 2014/04/29 16:47:10 reinoud Exp $ */
|
||||
/* $NetBSD: exynos_var.h,v 1.5 2014/05/09 21:49:43 reinoud Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
@ -37,10 +37,9 @@
|
||||
#include <sys/types.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/gpio.h>
|
||||
#include <dev/gpio/gpiovar.h>
|
||||
#include <arm/samsung/exynos_reg.h>
|
||||
|
||||
//#include <dev/gpio/gpiovar.h>
|
||||
|
||||
extern uint32_t exynos_soc_id;
|
||||
extern uint32_t exynos_pop_id;
|
||||
|
||||
@ -95,6 +94,17 @@ struct exyo_attach_args {
|
||||
bus_dma_tag_t exyo_coherent_dmat;
|
||||
};
|
||||
|
||||
struct exynos_gpio_pinset {
|
||||
char pinset_group[10];
|
||||
uint8_t pinset_func;
|
||||
uint32_t pinset_mask;
|
||||
};
|
||||
|
||||
struct exynos_gpio_pindata {
|
||||
gpio_chipset_tag_t pd_gc;
|
||||
int pd_pin;
|
||||
};
|
||||
|
||||
|
||||
extern struct bus_space exynos_bs_tag;
|
||||
extern struct bus_space exynos_a4x_bs_tag;
|
||||
@ -104,10 +114,29 @@ extern struct arm32_bus_dma_tag exynos_coherent_bus_dma_tag;
|
||||
extern bus_space_handle_t exynos_core_bsh;
|
||||
|
||||
extern void exynos_bootstrap(vaddr_t, vaddr_t);
|
||||
extern void exynos_dma_bootstrap(psize_t memsize);
|
||||
extern void exynos_gpio_bootstrap(void);
|
||||
|
||||
extern void exynos_device_register(device_t self, void *aux);
|
||||
extern void exyo_device_register(device_t self, void *aux);
|
||||
extern void exynos_wdt_reset(void);
|
||||
extern void exynos_dma_bootstrap(psize_t memsize);
|
||||
|
||||
extern bool exynos_gpio_pinset_available(const struct exynos_gpio_pinset *);
|
||||
extern void exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *);
|
||||
extern void exynos_gpio_pinset_release(const struct exynos_gpio_pinset *);
|
||||
extern bool exynos_gpio_pin_reserve(const char *, struct exynos_gpio_pindata *);
|
||||
|
||||
static inline void
|
||||
exynos_gpio_pindata_write(const struct exynos_gpio_pindata *pd, int value)
|
||||
{
|
||||
gpiobus_pin_write(pd->pd_gc, pd->pd_pin, value);
|
||||
}
|
||||
|
||||
static inline int
|
||||
exynos_gpio_pindata_read(const struct exynos_gpio_pindata *pd)
|
||||
{
|
||||
return gpiobus_pin_read(pd->pd_gc, pd->pd_pin);
|
||||
}
|
||||
|
||||
|
||||
#ifdef ARM_TRUSTZONE_FIRMWARE
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# $NetBSD: files.exynos,v 1.5 2014/05/05 20:31:03 reinoud Exp $
|
||||
# $NetBSD: files.exynos,v 1.6 2014/05/09 21:49:43 reinoud Exp $
|
||||
#
|
||||
# Configuration info for Samsung Exynos SoC ARM Peripherals
|
||||
#
|
||||
@ -45,7 +45,7 @@ defflag opt_exynos.h EXYNOS5440: EXYNOS5
|
||||
defflag opt_exynos.h EXYNOS5422: EXYNOS5
|
||||
|
||||
# SoC I/O attach point
|
||||
device exyo { [port=-1] } : bus_space_generic
|
||||
device exyo { [port=-1], [intr=-1] } : bus_space_generic
|
||||
attach exyo at mainbus with exyo_io
|
||||
file arch/arm/samsung/exynos_io.c exyo_io
|
||||
file arch/arm/samsung/exynos4_loc.c exyo_io & exynos4
|
||||
@ -69,6 +69,11 @@ file arch/arm/samsung/exynos_sscom.c exynos_sscom
|
||||
defflag opt_sscom.h SSCOM0CONSOLE SSCOM1CONSOLE
|
||||
defparam opt_sscom.h SSCOM_FREQ
|
||||
|
||||
# GPIO
|
||||
device exyogpio : gpiobus
|
||||
attach exyogpio at exyo with exynos_gpio
|
||||
file arch/arm/samsung/exynos_gpio.c exynos_gpio | exyo_io needs-flag
|
||||
|
||||
# USB2 Host Controller (EHCI/OHCI)
|
||||
device exyousb { }
|
||||
attach exyousb at exyo with exyo_usb
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#
|
||||
# $NetBSD: ODROID-U,v 1.4 2014/05/05 20:31:03 reinoud Exp $
|
||||
# $NetBSD: ODROID-U,v 1.5 2014/05/09 21:49:43 reinoud Exp $
|
||||
#
|
||||
# ODROID-U -- ODROID-U series Exynos Kernel
|
||||
#
|
||||
@ -192,6 +192,10 @@ sscom1 at exyo0 port 1 # UART1
|
||||
# Exynos Watchdog Timer
|
||||
exyowdt0 at exyo0 flags 1 # watchdog
|
||||
|
||||
# GPIO
|
||||
exyogpio0 at exyo0
|
||||
gpio* at exyogpio?
|
||||
|
||||
# On-board USB
|
||||
exyousb* at exyo0
|
||||
ohci* at exyousb?
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: odroid_machdep.c,v 1.8 2014/04/19 19:47:55 matt Exp $ */
|
||||
/* $NetBSD: odroid_machdep.c,v 1.9 2014/05/09 21:49:43 reinoud Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 The NetBSD Foundation, Inc.
|
||||
@ -31,7 +31,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.8 2014/04/19 19:47:55 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.9 2014/05/09 21:49:43 reinoud Exp $");
|
||||
|
||||
#include "opt_evbarm_boardtype.h"
|
||||
#include "opt_exynos.h"
|
||||
@ -469,6 +469,75 @@ consinit(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#ifdef EXYNOS4
|
||||
static void
|
||||
odroid_exynos4_gpio_ncs(device_t self, prop_dictionary_t dict) {
|
||||
/*
|
||||
* These pins have no connections; the 1st is a raw values that is
|
||||
* generated by the gpio bootstrap and the values substracted are
|
||||
* explicitly allowed
|
||||
*/
|
||||
prop_dictionary_set_uint32(dict, "nc-GPA0", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPA1", 0x3f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPB", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPC0", 0x1f - 0x00);
|
||||
/* blue led at bit 0 : */
|
||||
prop_dictionary_set_uint32(dict, "nc-GPC1", 0x1f - 0x01);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPD0", 0x0f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPD1", 0x0f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPF0", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPF1", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPF2", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPF3", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPJ0", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPJ1", 0x1f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPK0", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPK1", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPK2", 0x7f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPK3", 0x7f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPL0", 0x7f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPL1", 0x03 - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPL2", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPY0", 0x3f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPY1", 0x0f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPY2", 0x3f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPY3", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPY4", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPY5", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPY6", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPM0", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPM1", 0x7f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPM2", 0x1f - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPM3", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPM4", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPX0", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPX1", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPX2", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPX3", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPZ", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPV0", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPV1", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPV2", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPV3", 0xff - 0x00);
|
||||
prop_dictionary_set_uint32(dict, "nc-GPV4", 0x03 - 0x00);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef EXYNOS5
|
||||
static void
|
||||
odroid_exynos5_gpio_ncs(device_t self, prop_dictionary_t dict) {
|
||||
/*
|
||||
* These pins have no connections; the 1st is a raw values that is
|
||||
* generated by the gpio bootstrap and the values substracted are
|
||||
* explicitly allowed
|
||||
*/
|
||||
/* TBD: generate these values, see exynos_gpio.c boostrap */
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
odroid_device_register(device_t self, void *aux)
|
||||
{
|
||||
@ -480,5 +549,26 @@ odroid_device_register(device_t self, void *aux)
|
||||
if (use_fb_console)
|
||||
prop_dictionary_set_bool(dict, "is_console", false);
|
||||
}
|
||||
|
||||
if (device_is_a(self, "mct"))
|
||||
prop_dictionary_set_cstring(dict, "blinkled", "led0");
|
||||
|
||||
if (device_is_a(self, "exyogpio")) {
|
||||
#ifdef EXYNOS4
|
||||
if (IS_EXYNOS4_P()) {
|
||||
/* unused bits */
|
||||
odroid_exynos4_gpio_ncs(self, dict);
|
||||
/* explicit pin settings */
|
||||
prop_dictionary_set_cstring(dict, "led0", ">GPC1[0]");
|
||||
}
|
||||
#endif
|
||||
#ifdef EXYNOS5
|
||||
if (IS_EXYNOS5_P()) {
|
||||
/* unused bits */
|
||||
odroid_exynos5_gpio_ncs(self, dict);
|
||||
/* explicit pin settings */
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user