- Add wm_write_smbus_addr() to set SMBus address by software.
- Modify wm_gmii_hv_{read,write}reg_locked() to make them access HV_SMB_ADDR
correctly.
- Enable wm_init_lcd_from_nvm() again. Tested by Thinkpad X220.
This commit is contained in:
msaitoh
parent
4cca5c5584
commit
5a852cf570
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@ -1,4 +1,4 @@
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/* $NetBSD: ihphyreg.h,v 1.1 2010/11/27 20:15:27 christos Exp $ */
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/* $NetBSD: ihphyreg.h,v 1.2 2017/07/18 08:22:55 msaitoh Exp $ */
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/*-
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* Copyright (c) 2010 The NetBSD Foundation, Inc.
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@ -108,4 +108,15 @@
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/* Diagnostics Status Register */
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#define IHPHY_MII_DSR BME1000_REG(0, 31)
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/*
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* XXX I21[789] documents say that the SMBus Address register is at
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* PHY address 01, Page 0 (not 768), Register 26.
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*/
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#define HV_SMB_ADDR BME1000_REG(768, 26)
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#define HV_SMB_ADDR_ADDR 0x007f
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#define HV_SMB_ADDR_VALID (1 << 7)
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#define HV_SMB_ADDR_FREQ_LOW (1 << 8)
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#define HV_SMB_ADDR_PEC_EN (1 << 9)
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#define HV_SMB_ADDR_FREQ_HIGH (1 << 12)
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#endif /* _DEV_IHPHY_MIIREG_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.527 2017/07/18 08:05:03 msaitoh Exp $ */
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/* $NetBSD: if_wm.c,v 1.528 2017/07/18 08:22:55 msaitoh Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -83,7 +83,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.527 2017/07/18 08:05:03 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.528 2017/07/18 08:22:55 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_net_mpsafe.h"
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@ -134,6 +134,7 @@ __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.527 2017/07/18 08:05:03 msaitoh Exp $");
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#include <dev/mii/igphyreg.h>
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#include <dev/mii/igphyvar.h>
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#include <dev/mii/inbmphyreg.h>
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#include <dev/mii/ihphyreg.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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@ -679,6 +680,7 @@ static void wm_get_auto_rd_done(struct wm_softc *);
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static void wm_lan_init_done(struct wm_softc *);
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static void wm_get_cfg_done(struct wm_softc *);
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static void wm_phy_post_reset(struct wm_softc *);
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static void wm_write_smbus_addr(struct wm_softc *);
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static void wm_init_lcd_from_nvm(struct wm_softc *);
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static void wm_initialize_hardware_bits(struct wm_softc *);
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static uint32_t wm_rxpbs_adjust_82580(uint32_t);
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@ -3705,16 +3707,57 @@ wm_phy_post_reset(struct wm_softc *sc)
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/* Configure the LCD with the OEM bits in NVM */
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}
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/* Only for PCH and newer */
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static void
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wm_write_smbus_addr(struct wm_softc *sc)
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{
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uint32_t strap, freq;
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uint32_t phy_data;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
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device_xname(sc->sc_dev), __func__));
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strap = CSR_READ(sc, WMREG_STRAP);
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freq = __SHIFTOUT(strap, STRAP_FREQ);
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phy_data = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, HV_SMB_ADDR);
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phy_data &= ~HV_SMB_ADDR_ADDR;
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phy_data |= __SHIFTOUT(strap, STRAP_SMBUSADDR);
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phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
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if (sc->sc_phytype == WMPHY_I217) {
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/* Restore SMBus frequency */
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if (freq --) {
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phy_data &= ~(HV_SMB_ADDR_FREQ_LOW
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| HV_SMB_ADDR_FREQ_HIGH);
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phy_data |= __SHIFTIN((freq & 0x01) != 0,
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HV_SMB_ADDR_FREQ_LOW);
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phy_data |= __SHIFTIN((freq & 0x02) != 0,
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HV_SMB_ADDR_FREQ_HIGH);
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} else {
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DPRINTF(WM_DEBUG_INIT,
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("%s: %s Unsupported SMB frequency in PHY\n",
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device_xname(sc->sc_dev), __func__));
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}
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}
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wm_gmii_hv_writereg_locked(sc->sc_dev, 2, HV_SMB_ADDR, phy_data);
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}
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void
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wm_init_lcd_from_nvm(struct wm_softc *sc)
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{
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#if 0
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uint32_t extcnfctr, sw_cfg_mask, cnf_size, word_addr, i, reg;
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uint16_t phy_page = 0;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
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device_xname(sc->sc_dev), __func__));
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switch (sc->sc_type) {
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case WM_T_ICH8:
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if (sc->sc_phytype != WMPHY_IGP_3)
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if ((sc->sc_phytype == WMPHY_UNKNOWN)
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|| (sc->sc_phytype != WMPHY_IGP_3))
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return;
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if ((sc->sc_pcidevid == PCI_PRODUCT_INTEL_82801H_AMT)
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@ -3748,6 +3791,8 @@ wm_init_lcd_from_nvm(struct wm_softc *sc)
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&& ((extcnfctr & EXTCNFCTR_PCIE_WRITE_ENABLE) != 0))
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goto release;
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DPRINTF(WM_DEBUG_INIT, ("%s: %s: Configure LCD by software\n",
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device_xname(sc->sc_dev), __func__));
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/* word_addr is in DWORD */
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word_addr = __SHIFTOUT(extcnfctr, EXTCNFCTR_EXT_CNF_POINTER) << 1;
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@ -3762,8 +3807,9 @@ wm_init_lcd_from_nvm(struct wm_softc *sc)
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* LCD Write Enable bits are set in the NVM. When both NVM bits
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* are cleared, SW will configure them instead.
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*/
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device_printf(sc->sc_dev, "%s: need write_smbus()\n",
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__func__);
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DPRINTF(WM_DEBUG_INIT, ("%s: %s: Configure SMBus and LED\n",
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device_xname(sc->sc_dev), __func__));
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wm_write_smbus_addr(sc);
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reg = CSR_READ(sc, WMREG_LEDCTL);
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wm_gmii_hv_writereg_locked(sc->sc_dev, 1, HV_LED_CONFIG, reg);
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@ -3793,7 +3839,6 @@ wm_init_lcd_from_nvm(struct wm_softc *sc)
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release:
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sc->phy.release(sc);
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return;
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#endif
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}
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@ -10135,6 +10180,13 @@ wm_gmii_hv_readreg_locked(device_t dev, int phy, int reg)
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return 0;
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}
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/*
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* XXX I21[789] documents say that the SMBus Address register is at
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* PHY address 01, Page 0 (not 768), Register 26.
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*/
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if (page == HV_INTC_FC_PAGE_START)
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page = 0;
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if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
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wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
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page << BME1000_PAGE_SHIFT);
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@ -10196,6 +10248,13 @@ wm_gmii_hv_writereg_locked(device_t dev, int phy, int reg, int val)
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}
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{
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/*
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* XXX I21[789] documents say that the SMBus Address register
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* is at PHY address 01, Page 0 (not 768), Register 26.
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*/
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if (page == HV_INTC_FC_PAGE_START)
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page = 0;
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/*
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* XXX Workaround MDIO accesses being disabled after entering
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* IEEE Power Down (whenever bit 11 of the PHY control
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