Added Ricoh 5U822/5U823 SD/MMC Controller support.
This commit is contained in:
nonaka
parent
583c0ba939
commit
5a4d57175c
@ -1,4 +1,4 @@
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/* $NetBSD: sdhc_pci.c,v 1.6 2012/02/02 22:49:17 nonaka Exp $ */
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/* $NetBSD: sdhc_pci.c,v 1.7 2012/03/02 18:20:33 nonaka Exp $ */
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/* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */
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/*
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@ -18,7 +18,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.6 2012/02/02 22:49:17 nonaka Exp $");
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__KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.7 2012/03/02 18:20:33 nonaka Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_sdmmc.h"
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@ -79,9 +79,10 @@ static const struct sdhc_pci_quirk {
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u_int function;
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uint32_t flags;
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#define SDHC_PCI_QUIRK_FORCE_DMA (1U << 0)
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#define SDHC_PCI_QUIRK_TI_HACK (1U << 1)
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#define SDHC_PCI_QUIRK_NO_PWR0 (1U << 2)
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#define SDHC_PCI_QUIRK_FORCE_DMA (1U << 0)
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#define SDHC_PCI_QUIRK_TI_HACK (1U << 1)
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#define SDHC_PCI_QUIRK_NO_PWR0 (1U << 2)
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#define SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK (1U << 3)
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} sdhc_pci_quirk_table[] = {
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{
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PCI_VENDOR_TI,
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@ -109,9 +110,19 @@ static const struct sdhc_pci_quirk {
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0,
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SDHC_PCI_QUIRK_NO_PWR0
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},
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{
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PCI_VENDOR_RICOH,
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PCI_PRODUCT_RICOH_Rx5U823,
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0xffff,
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0xffff,
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0,
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SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK
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},
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};
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static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *);
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static void sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *);
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static uint32_t
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sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa)
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@ -133,7 +144,7 @@ sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa)
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if ((q->subvendor == 0xffff)
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&& (q->subproduct == 0xffff))
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return q->flags;
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return (q->flags);
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id = pci_conf_read(pa->pa_pc, pa->pa_tag,
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PCI_SUBSYS_ID_REG);
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@ -144,18 +155,17 @@ sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa)
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&& (q->subproduct != 0xffff)) {
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if ((vendor == q->subvendor)
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&& (product == q->subproduct))
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return q->flags;
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return (q->flags);
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} else if (q->subvendor != 0xffff) {
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if (product == q->subproduct)
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return q->flags;
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return (q->flags);
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} else {
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if (vendor == q->subvendor)
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return q->flags;
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return (q->flags);
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}
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}
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}
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return 0;
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return (0);
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}
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static int
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@ -165,9 +175,12 @@ sdhc_pci_match(device_t parent, cfdata_t cf, void *aux)
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC)
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return 1;
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return 0;
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return (1);
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
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(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U822 ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U823))
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return (1);
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return (0);
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}
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static void
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@ -203,6 +216,8 @@ sdhc_pci_attach(device_t parent, device_t self, void *aux)
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SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA);
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if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0))
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SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0);
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if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK))
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sdhc_pci_quirk_ricoh_lower_freq_hack(pa);
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/*
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* Map and attach all hosts supported by the host controller.
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@ -276,6 +291,17 @@ err:
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free(sc->sc.sc_host, M_DEVBUF);
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}
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static void
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sdhc_pci_conf_write(struct pci_attach_args *pa, int reg, uint8_t val)
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{
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pcireg_t r;
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r = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
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r &= ~(0xff << ((reg & 0x3) * 8));
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r |= (val << ((reg & 0x3) * 8));
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pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, r);
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}
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/* TI specific register */
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#define SDHC_PCI_GENERAL_CTL 0x4c
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#define MMC_SD_DIS 0x02
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@ -309,3 +335,29 @@ sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa)
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reg |= MMC_SD_DIS;
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pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg);
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}
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/* Ricoh specific register */
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#define SDHC_PCI_MODE_KEY 0xf9
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#define SDHC_PCI_MODE 0x150
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#define SDHC_PCI_MODE_SD20 0x10
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#define SDHC_PCI_BASE_FREQ_KEY 0xfc
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#define SDHC_PCI_BASE_FREQ 0xe1
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/* Some RICOH controllers need to be bumped into the right mode. */
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static void
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sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *pa)
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{
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/* Enable SD2.0 mode. */
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sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0xfc);
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sdhc_pci_conf_write(pa, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20);
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sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0x00);
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/*
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* Some SD/MMC cards don't work with the default base
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* clock frequency of 200MHz. Lower it to 50Hz.
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*/
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sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x01);
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sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ, 50);
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sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x00);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: sdhc.c,v 1.11 2012/02/23 21:06:21 matt Exp $ */
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/* $NetBSD: sdhc.c,v 1.12 2012/03/02 18:20:33 nonaka Exp $ */
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/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
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/*
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@ -23,7 +23,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.11 2012/02/23 21:06:21 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.12 2012/03/02 18:20:33 nonaka Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_sdmmc.h"
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@ -79,6 +79,8 @@ struct sdhc_host {
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struct kmutex intr_mtx;
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struct kcondvar intr_cv;
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int specver; /* spec. version */
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uint32_t flags; /* flags for this host */
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#define SHF_USE_DMA 0x0001
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#define SHF_USE_4BIT_MODE 0x0002
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@ -90,18 +92,18 @@ struct sdhc_host {
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static uint8_t
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hread1(struct sdhc_host *hp, bus_size_t reg)
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{
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if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
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return bus_space_read_1(hp->iot, hp->ioh, reg);
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return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3));
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}
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static uint16_t
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hread2(struct sdhc_host *hp, bus_size_t reg)
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{
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if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
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return bus_space_read_2(hp->iot, hp->ioh, reg);
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return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2));
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}
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@ -114,6 +116,7 @@ hread2(struct sdhc_host *hp, bus_size_t reg)
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static void
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hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val)
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{
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if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
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bus_space_write_1(hp->iot, hp->ioh, o, val);
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} else {
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@ -128,6 +131,7 @@ hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val)
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static void
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hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val)
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{
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if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
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bus_space_write_2(hp->iot, hp->ioh, o, val);
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} else {
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@ -223,25 +227,29 @@ sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
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struct sdmmcbus_attach_args saa;
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struct sdhc_host *hp;
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uint32_t caps;
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#ifdef SDHC_DEBUG
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uint16_t sdhcver;
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sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION);
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aprint_normal_dev(sc->sc_dev, "SD Host Specification/Vendor Version ");
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aprint_normal_dev(sc->sc_dev, "SD Host Specification ");
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switch (SDHC_SPEC_VERSION(sdhcver)) {
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case 0x00:
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aprint_normal("1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver));
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case SDHC_SPEC_VERS_100:
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aprint_normal("1.0");
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break;
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case 0x01:
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aprint_normal("2.0/%u\n", SDHC_VENDOR_VERSION(sdhcver));
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case SDHC_SPEC_VERS_200:
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aprint_normal("2.0");
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break;
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case SDHC_SPEC_VERS_300:
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aprint_normal("3.0");
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break;
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default:
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aprint_normal(">2.0/%u\n", SDHC_VENDOR_VERSION(sdhcver));
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aprint_normal("unknown version(0x%x)",
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SDHC_SPEC_VERSION(sdhcver));
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break;
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}
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#endif
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aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver));
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/* Allocate one more host structure. */
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hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO);
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@ -257,6 +265,7 @@ sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
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hp->iot = iot;
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hp->ioh = ioh;
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hp->dmat = sc->sc_dmat;
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hp->specver = SDHC_SPEC_VERSION(sdhcver);
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mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC);
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mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC);
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@ -285,12 +294,12 @@ sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
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/*
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* Determine the base clock frequency. (2.2.24)
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*/
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if (SDHC_BASE_FREQ_KHZ(caps) != 0)
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hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
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hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
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if (hp->clkbase == 0) {
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if (sc->sc_clkbase == 0) {
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/* The attachment driver must tell us. */
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aprint_error_dev(sc->sc_dev,"unknown base clock frequency\n");
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aprint_error_dev(sc->sc_dev,
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"unknown base clock frequency\n");
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goto err;
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}
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hp->clkbase = sc->sc_clkbase;
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@ -419,6 +428,7 @@ sdhc_suspend(device_t dev, const pmf_qual_t *qual)
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{
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struct sdhc_softc *sc = device_private(dev);
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struct sdhc_host *hp;
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size_t i;
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/* XXX poll for command completion or suspend command
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* in progress */
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@ -427,15 +437,15 @@ sdhc_suspend(device_t dev, const pmf_qual_t *qual)
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for (size_t n = 0; n < sc->sc_nhosts; n++) {
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hp = sc->sc_host[n];
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if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
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for (size_t i = 0; i < sizeof hp->regs; i += 4) {
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for (i = 0; i < sizeof hp->regs; i += 4) {
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uint32_t v = HREAD4(hp, i);
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hp->regs[i+0] = (v >> 0);
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hp->regs[i+1] = (v >> 8);
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hp->regs[i+2] = (v >> 16);
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hp->regs[i+3] = (v >> 24);
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hp->regs[i + 0] = (v >> 0);
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hp->regs[i + 1] = (v >> 8);
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hp->regs[i + 2] = (v >> 16);
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hp->regs[i + 3] = (v >> 24);
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}
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} else {
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for (size_t i = 0; i < sizeof hp->regs; i++) {
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for (i = 0; i < sizeof hp->regs; i++) {
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hp->regs[i] = HREAD1(hp, i);
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}
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}
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@ -448,21 +458,22 @@ sdhc_resume(device_t dev, const pmf_qual_t *qual)
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{
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struct sdhc_softc *sc = device_private(dev);
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struct sdhc_host *hp;
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size_t i;
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/* Restore the host controller state. */
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for (size_t n = 0; n < sc->sc_nhosts; n++) {
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hp = sc->sc_host[n];
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(void)sdhc_host_reset(hp);
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if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
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for (size_t i = 0; i < sizeof hp->regs; i += 4) {
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for (i = 0; i < sizeof hp->regs; i += 4) {
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HWRITE4(hp, i,
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(hp->regs[i+0] << 0)
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|(hp->regs[i+1] << 8)
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|(hp->regs[i+2] << 16)
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|(hp->regs[i+3] << 24));
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(hp->regs[i + 0] << 0)
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| (hp->regs[i + 1] << 8)
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| (hp->regs[i + 2] << 16)
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| (hp->regs[i + 3] << 24));
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}
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} else {
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for (size_t i = 0; i < sizeof hp->regs; i++) {
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for (i = 0; i < sizeof hp->regs; i++) {
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HWRITE1(hp, i, hp->regs[i]);
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}
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}
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@ -601,9 +612,7 @@ sdhc_write_protect(sdmmc_chipset_handle_t sch)
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r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH);
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mutex_exit(&hp->host_mtx);
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if (!r)
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return 1;
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return 0;
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return r ? 0 : 1;
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}
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/*
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@ -722,7 +731,6 @@ sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp)
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}
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}
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}
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/* No divisor found. */
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return false;
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}
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@ -739,18 +747,17 @@ sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
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u_int timo;
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int error = 0;
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#ifdef DIAGNOSTIC
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bool ispresent;
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#endif
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bool present;
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#ifdef DIAGNOSTIC
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mutex_enter(&hp->host_mtx);
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ispresent = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK);
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present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK);
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mutex_exit(&hp->host_mtx);
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/* Must not stop the clock if commands are in progress. */
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if (ispresent && sdhc_card_detect(hp))
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if (present && sdhc_card_detect(hp)) {
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printf("%s: sdhc_sdclk_frequency_select: command in progress\n",
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device_xname(hp->sc->sc_dev));
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}
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#endif
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mutex_enter(&hp->host_mtx);
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@ -790,11 +797,13 @@ sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
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*/
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if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
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sdmmc_delay(10000);
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HSET4(hp, SDHC_CLOCK_CTL, 8|SDHC_INTCLK_ENABLE|SDHC_INTCLK_STABLE);
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HSET4(hp, SDHC_CLOCK_CTL,
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8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE);
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} else {
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HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE);
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for (timo = 1000; timo > 0; timo--) {
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if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE))
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if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL),
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SDHC_INTCLK_STABLE))
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break;
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sdmmc_delay(10);
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}
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@ -819,6 +828,7 @@ sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
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sdmmc_delay(10);
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}
|
||||
DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo));
|
||||
|
||||
/*
|
||||
* Enable SD clock.
|
||||
*/
|
||||
@ -865,11 +875,11 @@ sdhc_bus_width(sdmmc_chipset_handle_t sch, int width)
|
||||
mutex_enter(&hp->host_mtx);
|
||||
reg = HREAD1(hp, SDHC_HOST_CTL);
|
||||
if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
|
||||
reg &= ~(SDHC_4BIT_MODE|SDHC_8BIT_MODE);
|
||||
reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE);
|
||||
if (width == 4)
|
||||
reg |= SDHC_4BIT_MODE;
|
||||
else if (width == 8)
|
||||
reg |= SDHC_8BIT_MODE;
|
||||
reg |= SDHC_ESDHC_8BIT_MODE;
|
||||
} else {
|
||||
reg &= ~SDHC_4BIT_MODE;
|
||||
if (width == 4)
|
||||
@ -1086,8 +1096,7 @@ sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
|
||||
/*
|
||||
* Prepare command register value. (2.2.6)
|
||||
*/
|
||||
command =
|
||||
(cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT;
|
||||
command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT;
|
||||
|
||||
if (ISSET(cmd->c_flags, SCF_RSP_CRC))
|
||||
command |= SDHC_CRC_CHECK_ENABLE;
|
||||
@ -1224,11 +1233,11 @@ static int
|
||||
sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd)
|
||||
{
|
||||
uint8_t *data = cmd->c_data;
|
||||
void (*pio_func)(struct sdhc_host *, uint8_t *, u_int);
|
||||
u_int len, datalen;
|
||||
u_int imask;
|
||||
u_int pmask;
|
||||
int error = 0;
|
||||
void (*pio_func)(struct sdhc_host *, uint8_t *, u_int);
|
||||
|
||||
if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
|
||||
imask = SDHC_BUFFER_READ_READY;
|
||||
@ -1366,22 +1375,22 @@ sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
|
||||
{
|
||||
uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS);
|
||||
uint32_t v;
|
||||
|
||||
while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
|
||||
uint32_t v = HREAD4(hp, SDHC_DATA);
|
||||
v = HREAD4(hp, SDHC_DATA);
|
||||
v = le32toh(v);
|
||||
*(uint32_t *)data = v;
|
||||
data += 4;
|
||||
datalen -= 4;
|
||||
status = HREAD2(hp, SDHC_NINTR_STATUS);
|
||||
}
|
||||
|
||||
if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
|
||||
uint32_t v = HREAD4(hp, SDHC_DATA);
|
||||
v = HREAD4(hp, SDHC_DATA);
|
||||
v = le32toh(v);
|
||||
do {
|
||||
*data++ = v;
|
||||
@ -1394,8 +1403,10 @@ static void
|
||||
esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
|
||||
{
|
||||
uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS);
|
||||
uint32_t v;
|
||||
|
||||
while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
|
||||
uint32_t v = *(uint32_t *)data;
|
||||
v = *(uint32_t *)data;
|
||||
v = htole32(v);
|
||||
HWRITE4(hp, SDHC_DATA, v);
|
||||
data += 4;
|
||||
@ -1403,7 +1414,7 @@ esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
|
||||
status = HREAD2(hp, SDHC_NINTR_STATUS);
|
||||
}
|
||||
if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
|
||||
uint32_t v = *(uint32_t *)data;
|
||||
v = *(uint32_t *)data;
|
||||
v = htole32(v);
|
||||
HWRITE4(hp, SDHC_DATA, v);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: sdhcreg.h,v 1.5 2012/02/01 22:53:19 matt Exp $ */
|
||||
/* $NetBSD: sdhcreg.h,v 1.6 2012/03/02 18:20:34 nonaka Exp $ */
|
||||
/* $OpenBSD: sdhcreg.h,v 1.4 2006/07/30 17:20:40 fgsch Exp $ */
|
||||
|
||||
/*
|
||||
@ -73,7 +73,7 @@
|
||||
#define SDHC_CMD_INHIBIT_MASK 0x0003
|
||||
#define SDHC_HOST_CTL 0x28
|
||||
#define SDHC_HIGH_SPEED (1<<2)
|
||||
#define SDHC_8BIT_MODE (1<<2) /* ESDHC */
|
||||
#define SDHC_ESDHC_8BIT_MODE (1<<2) /* eSDHC */
|
||||
#define SDHC_4BIT_MODE (1<<1)
|
||||
#define SDHC_LED_ON (1<<0)
|
||||
#define SDHC_POWER_CTL 0x29
|
||||
@ -167,6 +167,11 @@
|
||||
#define SDHC_DMA_CTL 0x40c /* eSDHC */
|
||||
#define SDHC_DMA_SNOOP 0x40
|
||||
|
||||
/* SDHC_SPEC_VERS */
|
||||
#define SDHC_SPEC_VERS_100 0x00
|
||||
#define SDHC_SPEC_VERS_200 0x01
|
||||
#define SDHC_SPEC_VERS_300 0x02
|
||||
|
||||
/* SDHC_CAPABILITIES decoding */
|
||||
#define SDHC_BASE_FREQ_KHZ(cap) \
|
||||
((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK) * 1000)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user