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- Rename some of TLB ops to have handy abbrivations hired from VAX and 

ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
  which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

- XXX XXX XXX
  it's less-than-optimal and likely a mistake to have TLBUpdate().
  It's costy to try to invalidate a single TLB entry whenver a certain
  PTE is going to be modified by traversing the entire TLB looking
  for the modified PTE because the PTE in question is not in TLB in
  most cases.  ASID bump could do the invalidation smartly.  Solution
  is planned for now.
This commit is contained in:
nisimura 2000-03-27 05:23:42 +00:00
parent cbab853044
commit 5987070300
3 changed files with 53 additions and 66 deletions
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15
sys/arch/mips/include/locore.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.h,v 1.26 2000/03/23 14:49:29 soren Exp $ */ /* $NetBSD: locore.h,v 1.27 2000/03/27 05:23:42 nisimura Exp $ */
/* /*
* Copyright 1996 The Board of Trustees of The Leland Stanford * Copyright 1996 The Board of Trustees of The Leland Stanford
@ -60,10 +60,11 @@ extern void mips1_FlushDCache __P((vaddr_t addr, vsize_t len));
extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len)); extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len));
extern void mips1_ForceCacheUpdate __P((void)); extern void mips1_ForceCacheUpdate __P((void));
extern void mips1_SetPID __P((int pid)); extern void mips1_SetPID __P((int pid));
extern void mips1_clean_tlb __P((void));
extern void mips1_TLBFlush __P((int numtlb)); extern void mips1_TBIA __P((int));
extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */ extern void mips1_TBIAP __P((int));
(vaddr_t addr)); extern void mips1_TBIS __P((vaddr_t));
extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int)); extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
extern void mips1_TLBWriteIndexed __P((u_int index, u_int high, extern void mips1_TLBWriteIndexed __P((u_int index, u_int high,
u_int low)); u_int low));
@ -179,8 +180,8 @@ extern mips_locore_jumpvec_t r4000_locore_vec;
#define MachFlushICache mips1_FlushICache #define MachFlushICache mips1_FlushICache
#define MachForceCacheUpdate mips1_ForceCacheUpdate #define MachForceCacheUpdate mips1_ForceCacheUpdate
#define MachSetPID mips1_SetPID #define MachSetPID mips1_SetPID
#define MachTLBFlush() mips1_TLBFlush(MIPS1_TLB_NUM_TLB_ENTRIES) #define MachTLBFlush() mips1_TBIAP(MIPS1_TLB_NUM_TLB_ENTRIES)
#define MachTLBFlushAddr mips1_TLBFlushAddr #define MachTLBFlushAddr mips1_TBIS
#define MachTLBUpdate mips1_TLBUpdate #define MachTLBUpdate mips1_TLBUpdate
#define wbflush() mips1_wbflush() #define wbflush() mips1_wbflush()
#define proc_trampoline mips1_proc_trampoline #define proc_trampoline mips1_proc_trampoline

47
sys/arch/mips/mips/locore_mips1.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_mips1.S,v 1.23 2000/03/04 11:37:31 nisimura Exp $ */ /* $NetBSD: locore_mips1.S,v 1.24 2000/03/27 05:23:43 nisimura Exp $ */
/* /*
* Copyright (c) 1992, 1993 * Copyright (c) 1992, 1993
@ -1038,24 +1038,12 @@ LEAF(mips1_TLBFlushPID)
END(mips1_TLBFlushPID) END(mips1_TLBFlushPID)
#endif #endif
/*-------------------------------------------------------------------------- /*
* void mips1_TBIS(vaddr_t va)
* *
* mips1_TLBFlushAddr -- * Invalidate a TLB entry for given virtual address if found in TLB.
*
* Flush any TLB entries for the given address and TLB PID.
*
* mips1_TLBFlushAddr(highreg)
* unsigned highreg;
*
* Results:
* None.
*
* Side effects:
* The process's page is flushed from the TLB.
*
*--------------------------------------------------------------------------
*/ */
LEAF(mips1_TLBFlushAddr) LEAF(mips1_TBIS)
mfc0 v1, MIPS_COP_0_STATUS # Save the status register. mfc0 v1, MIPS_COP_0_STATUS # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
mfc0 t0, MIPS_COP_0_TLB_HI # Get current PID mfc0 t0, MIPS_COP_0_TLB_HI # Get current PID
@ -1075,7 +1063,7 @@ LEAF(mips1_TLBFlushAddr)
mtc0 t0, MIPS_COP_0_TLB_HI # restore PID mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
j ra j ra
mtc0 v1, MIPS_COP_0_STATUS # Restore the status register mtc0 v1, MIPS_COP_0_STATUS # Restore the status register
END(mips1_TLBFlushAddr) END(mips1_TBIS)
/*-------------------------------------------------------------------------- /*--------------------------------------------------------------------------
* *
@ -1837,18 +1825,17 @@ LEAF_NOPROFILE(mips1_cpu_switch_resume)
END(mips1_cpu_switch_resume) END(mips1_cpu_switch_resume)
/* /*
* void mips1_purge_perprocess_tlb(void) * void mips1_TBIAP(int sizeofTLB)
* *
* Purge all TLB entries belong to per process user spaces. Entries for * Invalidate TLB entries belong to per process user spaces while
* kernel space are preserved. * retaining entries for kernel space marked global.
*/ */
LEAF(mips1_purge_perprocess_tlb) LEAF(mips1_TBIAP)
ALEAF(mips1_TLBFlush)
mfc0 v1, MIPS_COP_0_STATUS # save status register mfc0 v1, MIPS_COP_0_STATUS # save status register
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
li t1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT li t1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT
li t2, MIPS1_TLB_NUM_TLB_ENTRIES << MIPS1_TLB_INDEX_SHIFT sll t2, a0, MIPS1_TLB_INDEX_SHIFT
li v0, MIPS_KSEG0_START li v0, MIPS_KSEG0_START
# Align the starting value (t1) and the upper bound (t2) # Align the starting value (t1) and the upper bound (t2)
@ -1871,14 +1858,14 @@ ALEAF(mips1_TLBFlush)
j ra # new TLBPID will be set soon j ra # new TLBPID will be set soon
mtc0 v1, MIPS_COP_0_STATUS # restore status register mtc0 v1, MIPS_COP_0_STATUS # restore status register
END(mips1_purge_perprocess_tlb) END(mips1_TBIAP)
/* /*
* void mips1_clean_tlb(void) * void mips1_TBIA(int sizeofTLB)
* *
* Clense the entire TLB at early stage of processor initialization. * Invalidate TLB entirely.
*/ */
LEAF(mips1_clean_tlb) LEAF(mips1_TBIA)
mfc0 v1, MIPS_COP_0_STATUS # save the status register. mfc0 v1, MIPS_COP_0_STATUS # save the status register.
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
@ -1888,7 +1875,7 @@ LEAF(mips1_clean_tlb)
# Align the starting value (t1) and the upper bound (t2). # Align the starting value (t1) and the upper bound (t2).
move t1, zero move t1, zero
li t2, MIPS1_TLB_NUM_TLB_ENTRIES << MIPS1_TLB_INDEX_SHIFT sll t2, a0, MIPS1_TLB_INDEX_SHIFT
1: 1:
mtc0 t1, MIPS_COP_0_TLB_INDEX # set TLB index mtc0 t1, MIPS_COP_0_TLB_INDEX # set TLB index
addu t1, t1, 1 << MIPS1_TLB_INDEX_SHIFT # increment index addu t1, t1, 1 << MIPS1_TLB_INDEX_SHIFT # increment index
@ -1897,7 +1884,7 @@ LEAF(mips1_clean_tlb)
j ra j ra
mtc0 v1, MIPS_COP_0_STATUS # restore status register mtc0 v1, MIPS_COP_0_STATUS # restore status register
END(mips1_clean_tlb) END(mips1_TBIA)
.data .data
mips1_excausesw: mips1_excausesw:

57
sys/arch/mips/mips/mips_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.70 2000/03/27 02:55:16 nisimura Exp $ */ /* $NetBSD: mips_machdep.c,v 1.71 2000/03/27 05:23:42 nisimura Exp $ */
/*- /*-
* Copyright (c) 1998 The NetBSD Foundation, Inc. * Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -52,7 +52,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.70 2000/03/27 02:55:16 nisimura Exp $"); __KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.71 2000/03/27 05:23:42 nisimura Exp $");
#include "opt_compat_netbsd.h" #include "opt_compat_netbsd.h"
#include "opt_compat_ultrix.h" #include "opt_compat_ultrix.h"
@ -134,8 +134,8 @@ mips_locore_jumpvec_t mips1_locore_vec =
mips1_FlushICache, mips1_FlushICache,
/*mips1_FlushICache*/ mips1_FlushCache, /*mips1_FlushICache*/ mips1_FlushCache,
mips1_SetPID, mips1_SetPID,
mips1_TLBFlush, mips1_TBIAP,
mips1_TLBFlushAddr, mips1_TBIS,
mips1_TLBUpdate, mips1_TLBUpdate,
mips1_wbflush, mips1_wbflush,
mips1_proc_trampoline, mips1_proc_trampoline,
@ -439,7 +439,7 @@ mips_vector_init()
switch (cpu_arch) { switch (cpu_arch) {
#ifdef MIPS1 #ifdef MIPS1
case 1: case 1:
mips1_clean_tlb(); mips1_TBIA(MIPS1_TLB_NUM_TLB_ENTRIES);
mips1_vector_init(); mips1_vector_init();
break; break;
#endif #endif
@ -470,41 +470,40 @@ mips_set_wbflush(flush_fn)
struct pridtab { struct pridtab {
int cpu_imp; int cpu_imp;
char *cpu_name; char *cpu_name;
int cpu_isa;
}; };
struct pridtab cputab[] = { struct pridtab cputab[] = {
{ MIPS_R2000, "MIPS R2000 CPU", 1 }, { MIPS_R2000, "MIPS R2000 CPU", },
{ MIPS_R3000, "MIPS R3000 CPU", 1 }, { MIPS_R3000, "MIPS R3000 CPU", },
{ MIPS_R6000, "MIPS R6000 CPU", 2 }, { MIPS_R6000, "MIPS R6000 CPU", },
{ MIPS_R4000, "MIPS R4000 CPU", 3 }, { MIPS_R4000, "MIPS R4000 CPU", },
{ MIPS_R3LSI, "LSI Logic R3000 derivative", 1 }, { MIPS_R3LSI, "LSI Logic R3000 derivative", },
{ MIPS_R6000A, "MIPS R6000A CPU", 2 }, { MIPS_R6000A, "MIPS R6000A CPU", },
{ MIPS_R3IDT, "IDT R3041 or RC36100 CPU", 1 }, { MIPS_R3IDT, "IDT R3041 or RC36100 CPU", },
{ MIPS_R10000, "MIPS R10000/T5 CPU", 4 }, { MIPS_R10000, "MIPS R10000/T5 CPU", },
{ MIPS_R4200, "NEC VR4200 CPU", 3 }, { MIPS_R4200, "NEC VR4200 CPU", },
{ MIPS_R4300, "NEC VR4300 CPU", 3 }, { MIPS_R4300, "NEC VR4300 CPU", },
{ MIPS_R4100, "NEC VR4100 CPU", 3 }, { MIPS_R4100, "NEC VR4100 CPU", },
{ MIPS_R8000, "MIPS R8000 Blackbird/TFP CPU", 4 }, { MIPS_R8000, "MIPS R8000 Blackbird/TFP CPU", },
{ MIPS_R4600, "QED R4600 Orion CPU", 3 }, { MIPS_R4600, "QED R4600 Orion CPU", },
{ MIPS_R4700, "QED R4700 Orion CPU", 3 }, { MIPS_R4700, "QED R4700 Orion CPU", },
#ifdef ENABLE_MIPS_TX3900 #ifdef ENABLE_MIPS_TX3900
{ MIPS_TX3900, "Toshiba TX3900 CPU", 1 }, /* see below */ { MIPS_TX3900, "Toshiba TX3900 CPU", }, /* see below */
#else #else
{ MIPS_TX3900, "Toshiba TX3900 or QED R4650 CPU", 1 }, /* see below */ { MIPS_TX3900, "Toshiba TX3900 or QED R4650 CPU", }, /* see below */
#endif #endif
{ MIPS_R5000, "MIPS R5000 CPU", 4 }, { MIPS_R5000, "MIPS R5000 CPU", },
{ MIPS_RC32364, "IDT RC32364 CPU", 3 }, { MIPS_RC32364, "IDT RC32364 CPU", },
{ MIPS_RM5230, "QED RM5200 CPU", 4 }, { MIPS_RM5230, "QED RM5200 CPU", },
{ MIPS_RC64470, "IDT RC64474/RC64475 CPU", 3 }, { MIPS_RC64470, "IDT RC64474/RC64475 CPU", },
{ MIPS_R5400, "NEC VR5400 CPU", 4 }, { MIPS_R5400, "NEC VR5400 CPU", },
#if 0 /* ID crashs */ #if 0 /* ID crashs */
/* /*
* According to documents from Toshiba and QED, PRid 0x22 is * According to documents from Toshiba and QED, PRid 0x22 is
* used by both of TX3900 (ISA-I) and QED4640/4650 (ISA-III). * used by both of TX3900 (ISA-I) and QED4640/4650 (ISA-III).
* Two PRid conflicts below have not been confirmed this time. * Two PRid conflicts below have not been confirmed this time.
*/ */
{ MIPS_R3SONY, "SONY R3000 derivative", 1}, /* 0x21; crash R4700? */ { MIPS_R3SONY, "SONY R3000 derivative", }, /* 0x21; crash R4700? */
{ MIPS_R3NKK, "NKK R3000 derivative", 1}, /* 0x23; crash R5000? */ { MIPS_R3NKK, "NKK R3000 derivative", }, /* 0x23; crash R5000? */
#endif #endif
}; };
struct pridtab fputab[] = { struct pridtab fputab[] = {