The AMD-K5 Model 0 gets the PGE bit in the CPU features word wrong
using the APIC bit instead, according to the AMD Processor Recognition App. Note. Add a fixup routine to patch up cpu_feature in this case. XXX Need a way to kick the pmap to enable pmap_pg_g -- look at how the MP branch deals with this.
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.440 2001/05/03 16:55:32 thorpej Exp $ */
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/* $NetBSD: machdep.c,v 1.441 2001/05/04 03:19:33 thorpej Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998, 2000 The NetBSD Foundation, Inc.
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@ -255,6 +255,7 @@ static int exec_nomid __P((struct proc *, struct exec_package *));
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void cyrix6x86_cpu_setup __P((void));
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void winchip_cpu_setup __P((void));
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void amd_family5_setup __P((void));
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void intel_cpuid_cpu_cacheinfo __P((struct cpu_info *));
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void amd_cpuid_cpu_cacheinfo __P((struct cpu_info *));
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@ -718,7 +719,7 @@ const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
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"K6-2+/III+", 0, 0,
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"K5 or K6" /* Default */
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},
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NULL,
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amd_family5_setup,
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amd_cpuid_cpu_cacheinfo,
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},
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/* Family 6 */
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@ -914,6 +915,29 @@ winchip_cpu_setup()
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#endif
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}
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void
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amd_family5_setup(void)
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{
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extern int cpu_id;
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switch (CPUID2MODEL(cpu_id)) {
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case 0: /* AMD-K5 Model 0 */
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/*
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* According to the AMD Processor Recognition App Note,
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* the AMD-K5 Model 0 uses the wrong bit to indicate
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* support for global PTEs, instead using bit 9 (APIC)
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* rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!).
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*/
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if (cpu_feature & CPUID_APIC)
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cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE;
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/*
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* XXX But pmap_pg_g is already initialized -- need to kick
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* XXX the pmap somehow. How does the MP branch do this?
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*/
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break;
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}
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}
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static const struct i386_cache_info *
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cache_info_lookup(const struct i386_cache_info *cai, int count, u_int8_t desc)
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{
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