Fix two cases of handling stale page table information:
1. when reading the referenced/modified bits the TLB entry must be flushed before reading the in-core version. 2. when wrapping up an entire segment in pmap_page_protect(), flush the PTPs from the TLB to prevent a table-walking operation to pick up stale - or possibly bogus - PTEs. (hopefully I'll get a few of my hairs back now..)
This commit is contained in:
pk
parent
eb46d3c03e
commit
57e61589e7
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.61 1996/05/27 01:12:34 pk Exp $ */
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/* $NetBSD: pmap.c,v 1.62 1996/05/29 20:58:38 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -1015,18 +1015,18 @@ mmu_reservemon4m(kpmap, kmemtop)
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te = lda(ctxtblptr, ASI_BYPASS);
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switch (te & SRMMU_TETYPE) {
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case SRMMU_TEINVALID:
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case SRMMU_TEINVALID:
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ctx_phys_tbl[0] = SRMMU_TEINVALID;
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panic("mmu_reservemon4m: no existing L0 mapping! (How are we running?");
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break;
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case SRMMU_TEPTE:
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case SRMMU_TEPTE:
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#ifdef DEBUG
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printf("mmu_reservemon4m: trying to remap 4G segment!\n");
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#endif
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panic("mmu_reservemon4m: can't handle ROM 4G page size");
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/* XXX: Should make this work, however stupid it is */
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break;
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case SRMMU_TEPTD:
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case SRMMU_TEPTD:
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tableptr = (caddr_t) roundup((u_int) *kmemtop,
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SRMMU_L1SIZE * sizeof(long));
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*kmemtop = tableptr + (SRMMU_L1SIZE * sizeof(long));
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@ -1037,7 +1037,7 @@ mmu_reservemon4m(kpmap, kmemtop)
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kpmap->pm_reg_ptps_pa = VA2PA(tableptr);
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mmu_setup4m_L1(te, tableptr, kpmap, kmemtop);
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break;
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default:
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default:
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panic("mmu_reservemon4m: unknown pagetable entry type");
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}
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@ -1076,10 +1076,10 @@ mmu_setup4m_L1(regtblptd, newtableptr, kpmap, kmemtop)
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i++, regtblrover += sizeof(long)) {
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te = lda(regtblrover, ASI_BYPASS);
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switch(te & SRMMU_TETYPE) {
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case SRMMU_TEINVALID:
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case SRMMU_TEINVALID:
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((int *)newtableptr)[i] = SRMMU_TEINVALID;
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break;
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case SRMMU_TEPTE:
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case SRMMU_TEPTE:
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#ifdef DEBUG
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printf("mmu_reservemon4m: converting region 0x%x from L1->L3\n",i);
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#endif
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@ -1124,7 +1124,7 @@ mmu_setup4m_L1(regtblptd, newtableptr, kpmap, kmemtop)
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}
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}
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break;
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case SRMMU_TEPTD:
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case SRMMU_TEPTD:
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thisregmap = &kpmap->pm_regmap[i];
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bzero(thisregmap, sizeof(struct regmap));
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segtblptr = (caddr_t) roundup((u_int)*kmemtop,
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@ -1140,7 +1140,7 @@ mmu_setup4m_L1(regtblptd, newtableptr, kpmap, kmemtop)
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SRMMU_TEPTD;
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mmu_setup4m_L2(te, segtblptr, thisregmap, kmemtop, segmaps);
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break;
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default:
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default:
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panic("mmu_setup4m_L1: unknown pagetable entry type");
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}
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}
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@ -1164,10 +1164,10 @@ mmu_setup4m_L2(segtblptd, newtableptr, pregmap, kmemtop, segmaps)
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for (i = 0; i < SRMMU_L2SIZE; i++, segtblrover += sizeof(long)) {
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te = lda(segtblrover, ASI_BYPASS);
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switch(te & SRMMU_TETYPE) {
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case SRMMU_TEINVALID:
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case SRMMU_TEINVALID:
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((int *)newtableptr)[i] = SRMMU_TEINVALID;
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break;
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case SRMMU_TEPTE:
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case SRMMU_TEPTE:
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#ifdef DEBUG
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printf("mmu_reservemon4m: converting L2 entry at segment 0x%x to L3\n",i);
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#endif
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@ -1195,7 +1195,7 @@ mmu_setup4m_L2(segtblptd, newtableptr, pregmap, kmemtop, segmaps)
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SRMMU_TEPTE;
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}
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break;
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case SRMMU_TEPTD:
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case SRMMU_TEPTD:
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pregmap->rg_nsegmap++;
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thissegmap = &segmaps[i];
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pagtblptr = (caddr_t) roundup((u_int) *kmemtop,
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@ -1208,7 +1208,7 @@ mmu_setup4m_L2(segtblptd, newtableptr, pregmap, kmemtop, segmaps)
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thissegmap->sg_pte = (int *) pagtblptr;
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thissegmap->sg_npte += mmu_setup4m_L3(te, pagtblptr);
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break;
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default:
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default:
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panic("mmu_setup4m_L2: unknown pagetable entry type");
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}
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}
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@ -1227,16 +1227,16 @@ mmu_setup4m_L3(pagtblptd, newtableptr)
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for (i = 0; i < SRMMU_L3SIZE; i++, pagtblrover += sizeof(long)) {
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te = lda(pagtblrover, ASI_BYPASS);
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switch(te & SRMMU_TETYPE) {
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case SRMMU_TEINVALID:
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case SRMMU_TEINVALID:
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((int *)newtableptr)[i] = SRMMU_TEINVALID;
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break;
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case SRMMU_TEPTE:
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case SRMMU_TEPTE:
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((int *)newtableptr)[i] = te | PPROT_U2S_OMASK;
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n++;
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break;
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case SRMMU_TEPTD:
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case SRMMU_TEPTD:
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panic("mmu_setup4m_L3: PTD found in L3 page table");
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default:
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default:
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panic("mmu_setup4m_L3: unknown pagetable entry type");
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}
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}
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@ -2404,22 +2404,26 @@ pv_syncflags4m(pv0)
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if (sp->sg_pte == NULL) /* invalid */
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continue;
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tpte = getptesw4m(pm, va);
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/*
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* We need the PTE from memory as the TLB version will
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* always have the SRMMU_PG_R bit on.
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*/
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if (CTX_USABLE(pm,rp)) {
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setcontext(pm->pm_ctxnum);
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if (vactype != VAC_NONE && (tpte & SRMMU_PG_M))
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cache_flush_page(va); /* XXX: do we need this?*/
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tlb_flush_page(va);
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}
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tpte = getptesw4m(pm, va);
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if ((tpte & SRMMU_TETYPE) == SRMMU_TEPTE && /* if valid pte */
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(tpte & (SRMMU_PG_M|SRMMU_PG_R))) { /* and mod/refd */
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flags |= (tpte >> PG_M_SHIFT4M) &
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(PV_MOD4M|PV_REF4M|PV_C4M);
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tpte &= ~(SRMMU_PG_M | SRMMU_PG_R);
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if (CTX_USABLE(pm,rp))
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setpte4m(va, tpte); /* flushes cache too */
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else
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setptesw4m(pm, va, tpte);
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/* TLB has been invalidated, so just update memory */
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setptesw4m(pm, va, tpte);
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if (vactype != VAC_NONE &&
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CTX_USABLE(pm,rp) && (tpte & SRMMU_PG_M))
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cache_flush_page(va); /* XXX: do we need this?*/
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}
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}
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pv0->pv_flags = flags;
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@ -4849,6 +4853,8 @@ pmap_page_protect4m(pa, prot)
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/* if we're done with a region, leave it */
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} else { /* User mode mapping */
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if (CTX_USABLE(pm,rp))
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tlb_flush_segment(vr, vs);
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rp->rg_seg_ptps[vs] = SRMMU_TEINVALID;
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free(sp->sg_pte, M_VMPMAP);
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sp->sg_pte = NULL;
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