When overwriting the cache line size configuration, do not use the magic
value 0x10, but instead calculate a line size that is properly aligned to the IOMMU strbuf cache and our external cache line size. From FreeBSD.
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_machdep.c,v 1.36 2003/05/04 21:36:26 martin Exp $ */
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/* $NetBSD: pci_machdep.c,v 1.37 2003/05/05 07:51:26 martin Exp $ */
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/*
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* Copyright (c) 1999, 2000 Matthew R. Green
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@ -56,7 +56,6 @@ int sparc_pci_debug = 0x0;
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/openfirm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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@ -66,6 +65,7 @@ int sparc_pci_debug = 0x0;
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#include <sparc64/dev/iommuvar.h>
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#include <sparc64/dev/psychoreg.h>
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#include <sparc64/dev/psychovar.h>
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#include <sparc64/sparc64/cache.h>
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/* this is a base to be copied */
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struct sparc_pci_chipset _sparc_pci_chipset = {
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@ -286,7 +286,7 @@ pci_enumerate_bus(struct pci_softc *sc,
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pcitag_t tag;
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pcireg_t class, csr, bhlc, ic;
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int node, b, d, f, ret;
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int bus_frequency, lt, cl;
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int bus_frequency, lt, cl, cacheline;
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char name[30];
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extern int pci_config_dump;
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@ -297,6 +297,15 @@ pci_enumerate_bus(struct pci_softc *sc,
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bus_frequency = pci_bus_frequency(node);
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/*
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* Make sure the cache line size is at least as big as the
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* ecache line and the streaming cache (64 byte).
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*/
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cacheline = max(cacheinfo.ec_linesize, 64);
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KASSERT((cacheline/64)*64 == cacheline &&
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(cacheline/cacheinfo.ec_linesize)*cacheinfo.ec_linesize == cacheline &&
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(cacheline/4)*4 == cacheline);
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/* Turn on parity for the bus. */
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tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
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csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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@ -362,7 +371,7 @@ pci_enumerate_bus(struct pci_softc *sc,
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cl = PCI_CACHELINE(bhlc);
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if (cl == 0)
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cl = 0x10;
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cl = cacheline;
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bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
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(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
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