Wrap seeq and hpc register reads and writes in macros for
readability. While here, engage in some KNF and 80-column policing. No functional changes intended.
This commit is contained in:
rumble
parent
28b908ca06
commit
57329acafa
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@ -1,4 +1,4 @@
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/* $NetBSD: if_sq.c,v 1.23 2004/12/29 06:57:52 rumble Exp $ */
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/* $NetBSD: if_sq.c,v 1.24 2004/12/30 02:26:20 rumble Exp $ */
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/*
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* Copyright (c) 2001 Rafal K. Boni
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.23 2004/12/29 06:57:52 rumble Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.24 2004/12/30 02:26:20 rumble Exp $");
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#include "bpfilter.h"
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@ -127,6 +127,16 @@ CFATTACH_DECL(sq, sizeof(struct sq_softc),
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#define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
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#define sq_seeq_read(sc, off) \
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bus_space_read_1(sc->sc_regt, sc->sc_regh, off)
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#define sq_seeq_write(sc, off, val) \
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bus_space_write_1(sc->sc_regt, sc->sc_regh, off, val)
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#define sq_hpc_read(sc, off) \
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bus_space_read_4(sc->sc_hpct, sc->sc_hpch, off)
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#define sq_hpc_write(sc, off, val) \
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, off, val)
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static int
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sq_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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@ -255,12 +265,12 @@ sq_attach(struct device *parent, struct device *self, void *aux)
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* If it's zero, we have an 80c03, because we will have read
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* the TxCollLSB register.
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*/
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bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCOLLS0, 0xa5);
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if (bus_space_read_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCOLLS0) == 0)
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sq_seeq_write(sc, SEEQ_TXCOLLS0, 0xa5);
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if (sq_seeq_read(sc, SEEQ_TXCOLLS0) == 0)
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sc->sc_type = SQ_TYPE_80C03;
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else
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sc->sc_type = SQ_TYPE_8003;
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bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCOLLS0, 0x00);
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sq_seeq_write(sc, SEEQ_TXCOLLS0, 0x00);
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printf(": SGI Seeq %s\n",
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sc->sc_type == SQ_TYPE_80C03 ? "80c03" : "8003");
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@ -340,12 +350,11 @@ sq_init(struct ifnet *ifp)
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SQ_TRACE(SQ_RESET, sc, 0, 0);
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/* Set into 8003 mode, bank 0 to program ethernet address */
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bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCMD, TXCMD_BANK0);
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sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_BANK0);
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/* Now write the address */
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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bus_space_write_1(sc->sc_regt, sc->sc_regh, i,
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sc->sc_enaddr[i]);
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sq_seeq_write(sc, i, sc->sc_enaddr[i]);
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sc->sc_rxcmd = RXCMD_IE_CRC |
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RXCMD_IE_DRIB |
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@ -362,32 +371,27 @@ sq_init(struct ifnet *ifp)
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sq_set_filter(sc);
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/* Set up Seeq transmit command register */
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bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCMD,
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TXCMD_IE_UFLOW |
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sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_IE_UFLOW |
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TXCMD_IE_COLL |
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TXCMD_IE_16COLL |
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TXCMD_IE_GOOD);
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/* Now write the receive command register. */
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bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_RXCMD, sc->sc_rxcmd);
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sq_seeq_write(sc, SEEQ_RXCMD, sc->sc_rxcmd);
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/* Set up HPC ethernet DMA config */
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if (sc->hpc_regs->revision == 3) {
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reg = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETR_DMACFG);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETR_DMACFG,
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reg | ENETR_DMACFG_FIX_RXDC |
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reg = sq_hpc_read(sc, HPC_ENETR_DMACFG);
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sq_hpc_write(sc, HPC_ENETR_DMACFG, reg | ENETR_DMACFG_FIX_RXDC |
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ENETR_DMACFG_FIX_INTR |
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ENETR_DMACFG_FIX_EOP);
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}
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/* Pass the start of the receive ring to the HPC */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_ndbp,
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SQ_CDRXADDR(sc, 0));
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sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0));
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/* And turn on the HPC ethernet receive channel */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_ctl,
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sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
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sc->hpc_regs->enetr_ctl_active);
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/*
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@ -395,8 +399,7 @@ sq_init(struct ifnet *ifp)
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* (see Hollywood HPC Specification 2.1.4.3)
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*/
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if (sc->hpc_regs->revision != 3)
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC1_ENET_INTDELAY,
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HPC1_ENET_INTDELAYVAL);
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sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAYVAL);
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ifp->if_flags |= IFF_RUNNING;
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ifp->if_flags &= ~IFF_OACTIVE;
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@ -706,8 +709,7 @@ sq_start(struct ifnet *ifp)
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* are more packets to send and restarting the HPC DMA
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* engine, rather than mucking with the DMA state here.
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*/
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetx_ctl);
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status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl);
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if ((status & sc->hpc_regs->enetx_ctl_active) != 0) {
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SQ_TRACE(SQ_ADD_TO_DMA, sc, firsttx, status);
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@ -725,12 +727,11 @@ sq_start(struct ifnet *ifp)
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} else if (sc->hpc_regs->revision == 3) {
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SQ_TRACE(SQ_START_DMA, sc, firsttx, status);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETX_NDBP, SQ_CDTXADDR(sc, firsttx));
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sq_hpc_write(sc, HPC_ENETX_NDBP, SQ_CDTXADDR(sc,
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firsttx));
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/* Kick DMA channel into life */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETX_CTL, ENETX_CTL_ACTIVE);
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sq_hpc_write(sc, HPC_ENETX_CTL, ENETX_CTL_ACTIVE);
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} else {
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/*
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* In the HPC1 case where transmit DMA is
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@ -743,17 +744,16 @@ sq_start(struct ifnet *ifp)
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if (ofree == SQ_NTXDESC) {
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SQ_TRACE(SQ_START_DMA, sc, firsttx, status);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC1_ENETX_NDBP,
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sq_hpc_write(sc, HPC1_ENETX_NDBP,
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SQ_CDTXADDR(sc, firsttx));
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sq_hpc_write(sc, HPC1_ENETX_CFXBP,
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SQ_CDTXADDR(sc, firsttx));
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sq_hpc_write(sc, HPC1_ENETX_CBP,
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SQ_CDTXADDR(sc, firsttx));
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC1_ENETX_CFXBP, SQ_CDTXADDR(sc, firsttx));
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC1_ENETX_CBP, SQ_CDTXADDR(sc, firsttx));
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/* Kick DMA channel into life */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC1_ENETX_CTL, HPC1_ENETX_CTL_ACTIVE);
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sq_hpc_write(sc, HPC1_ENETX_CTL,
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HPC1_ENETX_CTL_ACTIVE);
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} else
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sq_txring_hpc1(sc);
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}
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@ -778,8 +778,8 @@ sq_stop(struct ifnet *ifp, int disable)
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}
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/* Clear Seeq transmit/receive command registers */
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bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCMD, 0);
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bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_RXCMD, 0);
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sq_seeq_write(sc, SEEQ_TXCMD, 0);
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sq_seeq_write(sc, SEEQ_RXCMD, 0);
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sq_reset(sc);
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@ -794,8 +794,7 @@ sq_watchdog(struct ifnet *ifp)
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u_int32_t status;
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struct sq_softc *sc = ifp->if_softc;
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetx_ctl);
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status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl);
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log(LOG_ERR, "%s: device timeout (prev %d, next %d, free %d, "
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"status %08x)\n", sc->sc_dev.dv_xname, sc->sc_prevtx,
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sc->sc_nexttx, sc->sc_nfreetx, status);
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@ -846,16 +845,14 @@ sq_intr(void * arg)
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int handled = 0;
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u_int32_t stat;
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stat = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_reset);
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stat = sq_hpc_read(sc, sc->hpc_regs->enetr_reset);
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if ((stat & 2) == 0) {
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printf("%s: Unexpected interrupt!\n", sc->sc_dev.dv_xname);
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return 0;
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}
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_reset, (stat | 2));
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sq_hpc_write(sc, sc->hpc_regs->enetr_reset, (stat | 2));
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/*
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* If the interface isn't running, the interrupt couldn't
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@ -896,9 +893,12 @@ sq_rxintr(struct sq_softc *sc)
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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for (i = sc->sc_nextrx;; i = SQ_NEXTRX(i)) {
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SQ_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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SQ_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD |
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BUS_DMASYNC_POSTWRITE);
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/* If this is a CPU-owned buffer, we're at the end of the list */
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/*
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* If this is a CPU-owned buffer, we're at the end of the list.
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*/
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if (sc->hpc_regs->revision == 3)
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ctl_reg = sc->sc_rxdesc[i].hpc3_hdd_ctl & HDD_CTL_OWN;
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else
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@ -909,8 +909,7 @@ sq_rxintr(struct sq_softc *sc)
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#if defined(SQ_DEBUG)
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u_int32_t reg;
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reg = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_ctl);
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reg = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl);
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SQ_DPRINTF(("%s: rxintr: done at %d (ctl %08x)\n",
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sc->sc_dev.dv_xname, i, reg));
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#endif
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@ -996,18 +995,17 @@ sq_rxintr(struct sq_softc *sc)
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sc->sc_nextrx = i;
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}
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_ctl);
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status = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl);
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/* If receive channel is stopped, restart it... */
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if ((status & sc->hpc_regs->enetr_ctl_active) == 0) {
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/* Pass the start of the receive ring to the HPC */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, sc->sc_nextrx));
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sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc,
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sc->sc_nextrx));
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/* And turn on the HPC ethernet receive channel */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetr_ctl, sc->hpc_regs->enetr_ctl_active);
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sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
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sc->hpc_regs->enetr_ctl_active);
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}
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return count;
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@ -1017,18 +1015,18 @@ static int
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sq_txintr(struct sq_softc *sc)
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{
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int shift = 0;
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u_int32_t status;
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u_int32_t status, tmp;
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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if (sc->hpc_regs->revision != 3)
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shift = 16;
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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sc->hpc_regs->enetx_ctl) >> shift;
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status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl) >> shift;
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SQ_TRACE(SQ_TXINTR_ENTER, sc, sc->sc_prevtx, status);
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if ((status & ( (sc->hpc_regs->enetx_ctl_active >> shift) | TXSTAT_GOOD)) == 0) {
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tmp = (sc->hpc_regs->enetx_ctl_active >> shift) | TXSTAT_GOOD;
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if ((status & tmp) == 0) {
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if (status & TXSTAT_COLL)
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ifp->if_collisions++;
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@ -1087,14 +1085,12 @@ sq_txring_hpc1(struct sq_softc *sc)
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int reclaimall, i = sc->sc_prevtx;
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch, HPC1_ENETX_CTL);
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status = sq_hpc_read(sc, HPC1_ENETX_CTL);
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if (status & HPC1_ENETX_CTL_ACTIVE) {
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SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status);
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return;
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} else {
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reclaimto = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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HPC1_ENETX_NDBP);
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}
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} else
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reclaimto = sq_hpc_read(sc, HPC1_ENETX_NDBP);
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if (sc->sc_nfreetx == 0 && SQ_CDTXADDR(sc, i) == reclaimto)
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reclaimall = 1;
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@ -1129,14 +1125,11 @@ sq_txring_hpc1(struct sq_softc *sc)
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KASSERT(reclaimto == SQ_CDTXADDR(sc, i));
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC1_ENETX_CFXBP,
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reclaimto);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC1_ENETX_CBP,
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reclaimto);
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sq_hpc_write(sc, HPC1_ENETX_CFXBP, reclaimto);
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sq_hpc_write(sc, HPC1_ENETX_CBP, reclaimto);
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/* Kick DMA channel into life */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC1_ENETX_CTL,
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HPC1_ENETX_CTL_ACTIVE);
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sq_hpc_write(sc, HPC1_ENETX_CTL, HPC1_ENETX_CTL_ACTIVE);
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/*
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* Set a watchdog timer in case the chip
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@ -1172,8 +1165,7 @@ sq_txring_hpc3(struct sq_softc *sc)
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* the buffer not being finished while the DMA channel
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* has gone idle.
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*/
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status = bus_space_read_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETX_CTL);
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status = sq_hpc_read(sc, HPC_ENETX_CTL);
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SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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@ -1183,12 +1175,12 @@ sq_txring_hpc3(struct sq_softc *sc)
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if ((status & ENETX_CTL_ACTIVE) == 0) {
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SQ_TRACE(SQ_RESTART_DMA, sc, i, status);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETX_NDBP, SQ_CDTXADDR(sc, i));
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sq_hpc_write(sc, HPC_ENETX_NDBP,
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SQ_CDTXADDR(sc, i));
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/* Kick DMA channel into life */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch,
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HPC_ENETX_CTL, ENETX_CTL_ACTIVE);
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sq_hpc_write(sc, HPC_ENETX_CTL,
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ENETX_CTL_ACTIVE);
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/*
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* Set a watchdog timer in case the chip
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@ -1222,12 +1214,12 @@ void
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sq_reset(struct sq_softc *sc)
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{
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/* Stop HPC dma channels */
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_ctl, 0);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetx_ctl, 0);
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sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 0);
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sq_hpc_write(sc, sc->hpc_regs->enetx_ctl, 0);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_reset, 3);
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sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 3);
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delay(20);
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bus_space_write_4(sc->sc_hpct, sc->sc_hpch, sc->hpc_regs->enetr_reset, 0);
|
||||
sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 0);
|
||||
}
|
||||
|
||||
/* sq_add_rxbuf: Add a receive buffer to the indicated descriptor. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue