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Sprinkle keyword volatile around device register accesses.

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This commit is contained in:
tsutsui 2009-07-20 16:25:22 +00:00
parent 35bdca4d17
commit 5651717f26
5 changed files with 85 additions and 78 deletions
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8
sys/arch/pmax/pmax/dec_3100.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_3100.c,v 1.47 2009/03/16 23:11:14 dsl Exp $ */
/* $NetBSD: dec_3100.c,v 1.48 2009/07/20 16:25:22 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -105,7 +105,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: dec_3100.c,v 1.47 2009/03/16 23:11:14 dsl Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_3100.c,v 1.48 2009/07/20 16:25:22 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -274,11 +274,11 @@ dec_3100_errintr()
{
u_int16_t csr;
csr = *(u_int16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
csr = *(volatile u_int16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
if (csr & KN01_CSR_MERR) {
printf("Memory error at 0x%x\n",
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR));
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR));
panic("Mem error interrupt");
}
csr = (csr & ~KN01_CSR_MBZ) | 0xff;

29
sys/arch/pmax/pmax/dec_3max.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_3max.c,v 1.48 2009/03/16 23:11:14 dsl Exp $ */
/* $NetBSD: dec_3max.c,v 1.49 2009/07/20 16:25:22 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -106,7 +106,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.48 2009/03/16 23:11:14 dsl Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.49 2009/07/20 16:25:22 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -167,7 +167,7 @@ dec_3max_init()
/* no high resolution timer available */
/* clear any memory errors */
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
kn02_wbflush();
ipl2spl_table = dec_3max_ipl2spl_table;
@ -179,9 +179,9 @@ dec_3max_init()
* Enable ECC memory correction, turn off LEDs, and
* disable all TURBOchannel interrupts.
*/
csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
csr &= ~(KN02_CSR_WRESERVED|KN02_CSR_IOINTEN|KN02_CSR_CORRECT|0xff);
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
kn02_wbflush();
strcpy(cpu_model, "DECstation 5000/200 (3MAX)");
@ -197,10 +197,10 @@ dec_3max_bus_reset()
* Reset interrupts, clear any errors from newconf probes
*/
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
kn02_wbflush();
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0;
kn02_wbflush();
}
@ -263,9 +263,10 @@ found:
intrtab[(int)cookie].ih_func = handler;
intrtab[(int)cookie].ih_arg = arg;
csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) & 0x00ffff00;
csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) &
0x00ffff00;
csr |= (kn02intrs[i].intrbit << 16);
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
kn02_wbflush();
}
@ -286,7 +287,7 @@ dec_3max_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
if (ipending & MIPS_INT_MASK_1) {
struct clockframe cf;
csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
if ((csr & KN02_CSR_PSWARN) && !warned) {
warned = 1;
printf("WARNING: power supply is overheating!\n");
@ -310,7 +311,7 @@ dec_3max_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
_splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_1));
if (ipending & MIPS_INT_MASK_0) {
csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
csr &= (csr >> KN02_CSR_IOINTEN_SHIFT);
if (csr & (KN02_IP_DZ | KN02_IP_LANCE | KN02_IP_SCSI)) {
if (csr & KN02_IP_DZ)
@ -349,11 +350,11 @@ dec_3max_errintr()
u_int32_t erradr, errsyn, csr;
/* Fetch error address, ECC chk/syn bits, clear interrupt */
erradr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR);
erradr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR);
errsyn = MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN);
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
kn02_wbflush();
csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
/* Send to kn02/kn03 memory subsystem handler */
dec_mtasic_err(erradr, errsyn, csr & KN02_CSR_BNK32M);

47
sys/arch/pmax/pmax/dec_3maxplus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_3maxplus.c,v 1.61 2009/03/16 23:11:14 dsl Exp $ */
/* $NetBSD: dec_3maxplus.c,v 1.62 2009/07/20 16:25:22 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -106,7 +106,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.61 2009/03/16 23:11:14 dsl Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.62 2009/07/20 16:25:22 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -179,7 +179,7 @@ dec_3maxplus_init()
platform.tc_init = dec_3maxplus_tc_init;
/* clear any memory errors */
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
kn03_wbflush();
ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
@ -189,24 +189,24 @@ dec_3maxplus_init()
/* calibrate cpu_mhz value */
mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1);
*(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
*(volatile u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(volatile u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
#if 0
*(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
*(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
*(volatile u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(volatile u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
*(volatile u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
#endif
/* XXX hard-reset LANCE */
*(u_int32_t *)(ioasic_base + IOASIC_CSR) |= 0x100;
*(volatile u_int32_t *)(ioasic_base + IOASIC_CSR) |= 0x100;
/* sanitize interrupt mask */
kn03_tc3_imask = KN03_INTR_PSWARN;
*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask;
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask;
kn03_wbflush();
prodtype = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_REG_INTR);
prodtype = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_REG_INTR);
prodtype &= KN03_INTR_PROD_JUMPER;
/* the bit persists even if INTR register is assigned value 0 */
if (prodtype)
@ -227,10 +227,10 @@ dec_3maxplus_bus_reset()
* Reset interrupts, clear any errors from newconf probes
*/
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
kn03_wbflush();
*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
kn03_wbflush();
}
@ -301,7 +301,7 @@ dec_3maxplus_intr_establish(struct device *dev, void *cookie, int level, int (*h
intrtab[(int)cookie].ih_func = handler;
intrtab[(int)cookie].ih_arg = arg;
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask;
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask;
kn03_wbflush();
}
@ -362,8 +362,10 @@ dec_3maxplus_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipendin
do {
ifound = 0;
imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK);
intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR);
imsk =
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK);
intr =
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR);
can_serve = intr & imsk;
CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0);
@ -405,7 +407,8 @@ dec_3maxplus_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipendin
xxxintr = can_serve & (ERRORS | PTRLOAD);
if (xxxintr) {
ifound = 1;
*(u_int32_t *)(ioasic_base + IOASIC_INTR)
*(volatile u_int32_t *)
(ioasic_base + IOASIC_INTR)
= intr &~ xxxintr;
}
} while (ifound);
@ -429,11 +432,11 @@ dec_3maxplus_errintr()
u_int32_t erradr, errsyn, csr;
/* Fetch error address, ECC chk/syn bits, clear interrupt */
erradr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR);
erradr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR);
errsyn = MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN);
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
kn03_wbflush();
csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_CSR);
csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_CSR);
/* Send to kn02/kn03 memory subsystem handler */
dec_mtasic_err(erradr, errsyn, csr & KN03_CSR_BNK32M);
@ -453,7 +456,7 @@ kn03_wbflush()
static unsigned
dec_3maxplus_get_timecount(struct timecounter *tc)
{
return *(u_int32_t*)(ioasic_base + IOASIC_CTR);
return *(volatile u_int32_t *)(ioasic_base + IOASIC_CTR);
}
static void

40
sys/arch/pmax/pmax/dec_3min.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_3min.c,v 1.63 2009/03/16 23:11:14 dsl Exp $ */
/* $NetBSD: dec_3min.c,v 1.64 2009/07/20 16:25:22 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -106,7 +106,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.63 2009/03/16 23:11:14 dsl Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.64 2009/07/20 16:25:22 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -176,7 +176,7 @@ dec_3min_init()
platform.tc_init = dec_3min_tc_init;
/* clear any memory errors */
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
kn02ba_wbflush();
ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC);
@ -184,22 +184,22 @@ dec_3min_init()
ipl2spl_table = dec_3min_ipl2spl_table;
/* enable posting of MIPS_INT_MASK_3 to CAUSE register */
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK;
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK;
/* calibrate cpu_mhz value */
mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3);
*(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
*(volatile u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(volatile u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
#if 0
*(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
*(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
*(volatile u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(volatile u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
*(volatile u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
#endif
/* sanitize interrupt mask */
kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT);
*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask;
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask;
/*
* The kmin memory hardware seems to wrap memory addresses
@ -228,10 +228,10 @@ dec_3min_bus_reset()
* Reset interrupts, clear any errors from newconf probes
*/
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
kn02ba_wbflush();
*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
kn02ba_wbflush();
}
@ -335,7 +335,7 @@ dec_3min_intr_establish(struct device *dev, void *cookie, int level, int (*handl
break;
}
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask;
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask;
kn02ba_wbflush();
}
@ -356,7 +356,7 @@ dec_3min_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
u_int32_t old_mask;
intr_depth++;
old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK);
old_mask = *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK);
if (ipending & MIPS_INT_MASK_4)
prom_haltbutton();
@ -367,8 +367,8 @@ dec_3min_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
u_int32_t intr, imsk, can_serve, turnoff;
turnoff = 0;
intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR);
imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK);
intr = *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR);
imsk = *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK);
can_serve = intr & imsk;
if (intr & IOASIC_INTR_SCSI_PTR_LOAD) {
@ -385,7 +385,7 @@ dec_3min_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
turnoff |= IOASIC_INTR_LANCE_READ_E;
if (turnoff)
*(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff;
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff;
if (intr & KMIN_INTR_TIMEOUT) {
kn02ba_errintr();
@ -407,7 +407,7 @@ dec_3min_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
/* If clock interrupts were enabled, re-enable them ASAP. */
if (old_mask & KMIN_INTR_CLOCK) {
/* ioctl interrupt mask to splclock and higher */
*(u_int32_t *)(ioasic_base + IOASIC_IMSK)
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK)
= old_mask &
~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 |
IOASIC_INTR_LANCE|IOASIC_INTR_SCSI);
@ -465,7 +465,7 @@ done:
/* restore entry state */
splhigh();
intr_depth--;
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask;
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask;
_splset(MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK));
}

39
sys/arch/pmax/pmax/dec_maxine.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_maxine.c,v 1.56 2009/03/18 10:22:33 cegger Exp $ */
/* $NetBSD: dec_maxine.c,v 1.57 2009/07/20 16:25:22 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -106,7 +106,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.56 2009/03/18 10:22:33 cegger Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.57 2009/07/20 16:25:22 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -174,7 +174,7 @@ dec_maxine_init(void)
/* MAXINE has 1 microsec. free-running high resolution timer */
/* clear any memory errors */
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
kn02ca_wbflush();
ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC);
@ -184,19 +184,19 @@ dec_maxine_init(void)
/* calibrate cpu_mhz value */
mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1);
*(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
*(volatile u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(volatile u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
#if 0
*(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(u_int32_t *)(ioasic_base + IOASIC_DTOP_DECODE) = 10;
*(u_int32_t *)(ioasic_base + IOASIC_FLOPPY_DECODE) = 13;
*(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00001fc1;
*(volatile u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(volatile u_int32_t *)(ioasic_base + IOASIC_DTOP_DECODE) = 10;
*(volatile u_int32_t *)(ioasic_base + IOASIC_FLOPPY_DECODE) = 13;
*(volatile u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00001fc1;
#endif
/* sanitize interrupt mask */
xine_tc3_imask = 0;
*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask;
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask;
kn02ca_wbflush();
sprintf(cpu_model, "Personal DECstation 5000/%d (MAXINE)", cpu_mhz);
@ -212,10 +212,10 @@ dec_maxine_bus_reset(void)
* Reset interrupts, clear any errors from newconf probes
*/
*(u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
kn02ca_wbflush();
*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
kn02ca_wbflush();
}
@ -298,7 +298,7 @@ dec_maxine_intr_establish(struct device *dev, void *cookie, int level, int (*han
intrtab[(int)cookie].ih_func = handler;
intrtab[(int)cookie].ih_arg = arg;
*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask;
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask;
kn02ca_wbflush();
}
@ -340,8 +340,10 @@ dec_maxine_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
do {
ifound = 0;
intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR);
imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK);
intr =
*(volatile u_int32_t *)(ioasic_base + IOASIC_INTR);
imsk =
*(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK);
can_serve = intr & imsk;
CHECKINTR(SYS_DEV_DTOP, XINE_INTR_DTOP);
@ -377,7 +379,8 @@ dec_maxine_intr(unsigned status, unsigned cause, unsigned pc, unsigned ipending)
xxxintr = can_serve & (ERRORS | PTRLOAD);
if (xxxintr) {
ifound = 1;
*(u_int32_t *)(ioasic_base + IOASIC_INTR)
*(volatile u_int32_t *)
(ioasic_base + IOASIC_INTR)
= intr &~ xxxintr;
}
} while (ifound);
@ -401,7 +404,7 @@ kn02ca_wbflush()
static uint32_t
dec_maxine_get_timecount(struct timecounter *tc)
{
return *(u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR);
return *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR);
}
static void