Cleanup, use obio_find_mapping() instead of xxx_va
This commit is contained in:
gwr
parent
52ef17d342
commit
552b122850
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 1994 Gordon W. Ross
|
||||
* Copyright (c) 1993 Adam Glass
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -13,22 +14,21 @@
|
|||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Adam Glass.
|
||||
* 4. The name of the Author may not be used to endorse or promote products
|
||||
* 4. The name of the authors may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Adam Glass ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $Id: autoconf.c,v 1.12 1994/07/27 04:51:58 gwr Exp $
|
||||
* $Id: autoconf.c,v 1.13 1994/09/20 16:52:21 gwr Exp $
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -57,6 +57,10 @@
|
|||
|
||||
extern void mainbusattach __P((struct device *, struct device *, void *));
|
||||
|
||||
void conf_init(), swapgeneric();
|
||||
void swapconf(), dumpconf();
|
||||
|
||||
|
||||
struct mainbus_softc {
|
||||
struct device mainbus_dev;
|
||||
};
|
||||
|
|
@ -92,14 +96,25 @@ void configure()
|
|||
int root_found;
|
||||
extern int soft1intr();
|
||||
|
||||
isr_init();
|
||||
/* General device autoconfiguration. */
|
||||
root_found = config_rootfound("mainbus", NULL);
|
||||
if (!root_found)
|
||||
panic("configure: autoconfig failed, no device tree root found");
|
||||
|
||||
/* Install non-device interrupt handlers. */
|
||||
isr_add(7, nmi_intr, 0);
|
||||
isr_add(1, soft1intr, 0);
|
||||
isr_cleanup();
|
||||
|
||||
/* Build table for CHR-to-BLK translation, etc. */
|
||||
conf_init();
|
||||
|
||||
#ifdef GENERIC
|
||||
/* Choose root and swap devices. */
|
||||
swapgeneric();
|
||||
#endif
|
||||
swapconf();
|
||||
dumpconf();
|
||||
}
|
||||
|
||||
int always_match(parent, cf, args)
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Id: clock.c,v 1.16 1994/06/01 15:45:39 gwr Exp $
|
||||
* $Id: clock.c,v 1.17 1994/09/20 16:52:22 gwr Exp $
|
||||
*/
|
||||
/*
|
||||
* machine-dependent clock routines; intersil7170
|
||||
|
|
@ -55,19 +55,24 @@
|
|||
#include "intersil7170.h"
|
||||
#include "interreg.h"
|
||||
|
||||
#define intersil_clock ((volatile struct intersil7170 *) CLOCK_VA)
|
||||
extern volatile u_char *interrupt_reg;
|
||||
volatile char *clock_va;
|
||||
|
||||
#define intersil_clock ((volatile struct intersil7170 *) clock_va)
|
||||
|
||||
#define intersil_command(run, interrupt) \
|
||||
(run | interrupt | INTERSIL_CMD_FREQ_32K | INTERSIL_CMD_24HR_MODE | \
|
||||
INTERSIL_CMD_NORMAL_MODE)
|
||||
|
||||
#define intersil_disable() \
|
||||
intersil_clock->command_reg = \
|
||||
intersil_clock->clk_cmd_reg = \
|
||||
intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE)
|
||||
|
||||
#define intersil_enable() \
|
||||
intersil_clock->command_reg = \
|
||||
intersil_clock->clk_cmd_reg = \
|
||||
intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE)
|
||||
#define intersil_clear() intersil_clock->interrupt_reg
|
||||
|
||||
#define intersil_clear() intersil_clock->clk_intr_reg
|
||||
|
||||
|
||||
#define SECS_HOUR (60*60)
|
||||
|
|
@ -101,42 +106,47 @@ struct cfdriver clockcd =
|
|||
{ NULL, "clock", always_match, clockattach, DV_DULL,
|
||||
sizeof(struct clock_softc), 0};
|
||||
|
||||
void clock_init()
|
||||
{
|
||||
clock_va = obio_find_mapping(OBIO_CLOCK, OBIO_CLOCK_SIZE);
|
||||
if (!clock_va)
|
||||
mon_panic("clock VA not found\n");
|
||||
}
|
||||
|
||||
int clockmatch(parent, cf, args)
|
||||
struct device *parent;
|
||||
struct cfdata *cf;
|
||||
void *args;
|
||||
{
|
||||
caddr_t intersil_addr;
|
||||
struct obio_cf_loc *obio_loc = (struct obio_cf_loc *) CFDATA_LOC(cf);
|
||||
|
||||
intersil_addr =
|
||||
OBIO_DEFAULT_PARAM(caddr_t, obio_loc->obio_addr, OBIO_CLOCK);
|
||||
return /* probe */ 1;
|
||||
return (1);
|
||||
}
|
||||
#if 0 /* Adam's */
|
||||
void set_clock_level(level_code, enable_clock)
|
||||
unsigned int level_code;
|
||||
int enable_clock;
|
||||
|
||||
void clockattach(parent, self, args)
|
||||
struct device *parent;
|
||||
struct device *self;
|
||||
void *args;
|
||||
{
|
||||
unsigned int val, stupid_thing;
|
||||
vm_offset_t pte;
|
||||
struct clock_softc *clock = (struct clock_softc *) self;
|
||||
struct obio_cf_loc *obio_loc = OBIO_LOC(self);
|
||||
int clock_addr;
|
||||
int clock_intr();
|
||||
void level5intr_clock();
|
||||
|
||||
val = get_interrupt_reg(); /* get interrupt register value */
|
||||
val &= ~(IREG_ALL_ENAB);
|
||||
set_interrupt_reg(val); /* disable all "interrupts" */
|
||||
intersil_disable(); /* turn off clock interrupt source */
|
||||
stupid_thing = intersil_clear(); /* torch peinding interrupts on clock*/
|
||||
stupid_thing++; /* defeat compiler? */
|
||||
val &= ~(IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5);
|
||||
set_interrupt_reg(val); /* clear any pending interrupts */
|
||||
val |= level_code;
|
||||
set_interrupt_reg(val); /* enable requested interrupt level if any */
|
||||
val |= IREG_ALL_ENAB;
|
||||
set_interrupt_reg(val); /* enable all interrupts */
|
||||
if (enable_clock)
|
||||
intersil_enable();
|
||||
clock_addr = OBIO_CLOCK;
|
||||
clock->clock_level = OBIO_DEFAULT_PARAM(int, obio_loc->obio_level, 5);
|
||||
clock->clock_va = (caddr_t) clock_va;
|
||||
obio_print(clock_addr, clock->clock_level);
|
||||
if (clock->clock_level != 5) {
|
||||
printf(": level != 5\n");
|
||||
return;
|
||||
}
|
||||
intersil_softc = clock;
|
||||
intersil_disable();
|
||||
set_clk_mode(0, IREG_CLOCK_ENAB_7, 0);
|
||||
isr_add_custom(clock->clock_level, level5intr_clock);
|
||||
set_clk_mode(IREG_CLOCK_ENAB_5, 0, 0);
|
||||
printf("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set and/or clear the desired clock bits in the interrupt
|
||||
|
|
@ -148,7 +158,6 @@ set_clk_mode(on, off, enable)
|
|||
int enable;
|
||||
{
|
||||
register u_char interreg, dummy;
|
||||
extern char *interrupt_reg;
|
||||
/*
|
||||
* make sure that we are only playing w/
|
||||
* clock interrupt register bits
|
||||
|
|
@ -170,9 +179,9 @@ set_clk_mode(on, off, enable)
|
|||
* to clear any pending signals there.
|
||||
*/
|
||||
*interrupt_reg &= ~(IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5);
|
||||
intersil_clock->command_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
intersil_clock->clk_cmd_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
INTERSIL_CMD_IDISABLE);
|
||||
dummy = intersil_clock->interrupt_reg; /* clear clock */
|
||||
dummy = intersil_clock->clk_intr_reg; /* clear clock */
|
||||
#ifdef lint
|
||||
dummy = dummy;
|
||||
#endif
|
||||
|
|
@ -185,45 +194,12 @@ set_clk_mode(on, off, enable)
|
|||
*/
|
||||
*interrupt_reg |= (interreg | on); /* enable flip-flops */
|
||||
if (enable)
|
||||
intersil_clock->command_reg =
|
||||
intersil_clock->clk_cmd_reg =
|
||||
intersil_command(INTERSIL_CMD_RUN,
|
||||
INTERSIL_CMD_IENABLE);
|
||||
*interrupt_reg |= IREG_ALL_ENAB; /* enable interrupts */
|
||||
}
|
||||
|
||||
void clockattach(parent, self, args)
|
||||
struct device *parent;
|
||||
struct device *self;
|
||||
void *args;
|
||||
{
|
||||
struct clock_softc *clock = (struct clock_softc *) self;
|
||||
struct obio_cf_loc *obio_loc = OBIO_LOC(self);
|
||||
caddr_t clock_addr;
|
||||
int clock_intr();
|
||||
void level5intr_clock();
|
||||
vm_offset_t pte;
|
||||
|
||||
clock_addr = (caddr_t) OBIO_CLOCK;
|
||||
clock->clock_level = OBIO_DEFAULT_PARAM(int, obio_loc->obio_level, 5);
|
||||
clock->clock_va = (caddr_t) CLOCK_VA;
|
||||
if (!clock->clock_va) {
|
||||
printf(": not enough obio space\n");
|
||||
return;
|
||||
}
|
||||
obio_print(clock_addr, clock->clock_level);
|
||||
if (clock->clock_level != 5) {
|
||||
printf(": level != 5\n");
|
||||
return;
|
||||
}
|
||||
intersil_softc = clock;
|
||||
intersil_disable();
|
||||
set_clk_mode(0, IREG_CLOCK_ENAB_7, 0);
|
||||
isr_add_custom(clock->clock_level, level5intr_clock);
|
||||
set_clk_mode(IREG_CLOCK_ENAB_5, 0, 0);
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
#if 1 /* XXX - This stuff OK? -gwr */
|
||||
/*
|
||||
* Set up the real-time clock. Leave stathz 0 since there is no secondary
|
||||
* clock available.
|
||||
|
|
@ -242,8 +218,8 @@ cpu_initclocks(void)
|
|||
|
||||
dummy = intersil_clear();
|
||||
dummy++;
|
||||
intersil_clock->interrupt_reg = INTERSIL_INTER_CSECONDS;
|
||||
intersil_clock->command_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
intersil_clock->clk_intr_reg = INTERSIL_INTER_CSECONDS;
|
||||
intersil_clock->clk_cmd_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
INTERSIL_CMD_IENABLE);
|
||||
}
|
||||
|
||||
|
|
@ -258,8 +234,6 @@ setstatclockrate(newhz)
|
|||
/* nothing */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void startrtclock()
|
||||
{
|
||||
char dummy;
|
||||
|
|
@ -267,8 +241,8 @@ void startrtclock()
|
|||
if (!intersil_softc)
|
||||
panic("clock: not initialized");
|
||||
|
||||
intersil_clock->interrupt_reg = INTERSIL_INTER_CSECONDS;
|
||||
intersil_clock->command_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
intersil_clock->clk_intr_reg = INTERSIL_INTER_CSECONDS;
|
||||
intersil_clock->clk_cmd_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
INTERSIL_CMD_IDISABLE);
|
||||
dummy = intersil_clear();
|
||||
}
|
||||
|
|
@ -280,8 +254,8 @@ void enablertclock()
|
|||
|
||||
dummy = intersil_clear();
|
||||
dummy++;
|
||||
intersil_clock->interrupt_reg = INTERSIL_INTER_CSECONDS;
|
||||
intersil_clock->command_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
intersil_clock->clk_intr_reg = INTERSIL_INTER_CSECONDS;
|
||||
intersil_clock->clk_cmd_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
INTERSIL_CMD_IENABLE);
|
||||
}
|
||||
|
||||
|
|
@ -443,7 +417,7 @@ void resettodr()
|
|||
struct intersil_map hdw_format;
|
||||
|
||||
timeval_to_intersil(time, &hdw_format);
|
||||
intersil_clock->command_reg = intersil_command(INTERSIL_CMD_STOP,
|
||||
intersil_clock->clk_cmd_reg = intersil_command(INTERSIL_CMD_STOP,
|
||||
INTERSIL_CMD_IDISABLE);
|
||||
|
||||
intersil_clock->counters.csecs = hdw_format.csecs ;
|
||||
|
|
@ -455,7 +429,7 @@ void resettodr()
|
|||
intersil_clock->counters.year = hdw_format.year ;
|
||||
intersil_clock->counters.day = hdw_format.day ;
|
||||
|
||||
intersil_clock->command_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
intersil_clock->clk_cmd_reg = intersil_command(INTERSIL_CMD_RUN,
|
||||
INTERSIL_CMD_IENABLE);
|
||||
}
|
||||
|
||||
|
|
@ -477,5 +451,3 @@ void microtime(tvp)
|
|||
lasttime = *tvp;
|
||||
splx(s);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Header: /cvsroot/src/sys/arch/sun3/sun3/interreg.h,v 1.3 1994/02/04 08:20:55 glass Exp $
|
||||
* $Id: interreg.h,v 1.4 1994/09/20 16:52:24 gwr Exp $
|
||||
*/
|
||||
#define IREG_CLOCK_ENAB_7 0x80
|
||||
#define IREG_RESERVED 0x40
|
||||
|
|
@ -39,4 +39,6 @@
|
|||
#define IREG_SOFT_ENAB_1 0x02
|
||||
#define IREG_ALL_ENAB 0x01
|
||||
|
||||
#define IREG_BITS "\20\8CLOCK_7\7RESERVED\6CLOCK_5\5VIDEO\4SOFT_3\3SOFT_2\2SOFT_1\1ALL\n"
|
||||
#define IREG_BITS "\20\8CLK7\7RSV6\6CLK5\5VIDEO\4SOFT3\3SOFT2\2SOFT1\1ALL\n"
|
||||
|
||||
int set_clk_mode(u_char on, u_char off, int enable);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 1994 Gordon W. Ross
|
||||
* Copyright (c) 1993 Adam Glass
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -13,22 +14,21 @@
|
|||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Adam Glass.
|
||||
* 4. The name of the Author may not be used to endorse or promote products
|
||||
* 4. The name of the authors may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Adam Glass ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $Id: interrupt.s,v 1.12 1994/07/25 18:28:01 gwr Exp $
|
||||
* $Id: interrupt.s,v 1.13 1994/09/20 16:52:25 gwr Exp $
|
||||
*/
|
||||
|
||||
.data
|
||||
|
|
@ -88,14 +88,16 @@ _level5intr:
|
|||
INTERRUPT_HANDLE(5)
|
||||
|
||||
/* clock */
|
||||
.globl _level5intr_clock, _interrupt_reg, _clock_intr
|
||||
.globl _level5intr_clock, _interrupt_reg, _clock_intr, _clock_va
|
||||
.align 4
|
||||
_level5intr_clock:
|
||||
tstb CLOCK_VA+INTERSIL_INTR_OFFSET
|
||||
andb #~IREG_CLOCK_ENAB_5, INTERREG_VA
|
||||
orb #IREG_CLOCK_ENAB_5, INTERREG_VA
|
||||
tstb CLOCK_VA+INTERSIL_INTR_OFFSET
|
||||
INTERRUPT_SAVEREG | save a0, a1, d0, d1
|
||||
movl _clock_va, a0
|
||||
movl _interrupt_reg, a1
|
||||
tstb a0@(INTERSIL_INTR_OFFSET)
|
||||
andb #~IREG_CLOCK_ENAB_5, a1@
|
||||
orb #IREG_CLOCK_ENAB_5, a1@
|
||||
tstb a0@(INTERSIL_INTR_OFFSET)
|
||||
|
||||
#undef CLOCK_DEBUG /* XXX - Broken anyway... -gwr */
|
||||
#ifdef CLOCK_DEBUG
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Header: /cvsroot/src/sys/arch/sun3/sun3/Attic/intersil7170.h,v 1.4 1994/02/04 08:20:57 glass Exp $
|
||||
* $Id: intersil7170.h,v 1.5 1994/09/20 16:52:26 gwr Exp $
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -52,9 +52,9 @@ struct intersil_map { /* from p. 7 of 10 */
|
|||
|
||||
struct intersil7170 {
|
||||
struct intersil_map counters;
|
||||
struct intersil_map ram; /* should be ok as both are word aligned */
|
||||
unsigned char interrupt_reg;
|
||||
unsigned char command_reg;
|
||||
struct intersil_map clk_ram; /* should be ok as both are word aligned */
|
||||
unsigned char clk_intr_reg;
|
||||
unsigned char clk_cmd_reg;
|
||||
};
|
||||
|
||||
/* bit assignments for command register, p. 6 of 10, write-only */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 1994 Gordon W. Ross
|
||||
* Copyright (c) 1993 Adam Glass
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -13,22 +14,21 @@
|
|||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Adam Glass.
|
||||
* 4. The name of the Author may not be used to endorse or promote products
|
||||
* 4. The name of the authors may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Adam Glass ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $Id: isr.c,v 1.10 1994/07/25 18:28:04 gwr Exp $
|
||||
* $Id: isr.c,v 1.11 1994/09/20 16:52:27 gwr Exp $
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
|
|
@ -37,7 +37,10 @@
|
|||
#include <sys/vmmeter.h>
|
||||
|
||||
#include <net/netisr.h>
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/mon.h>
|
||||
#include <machine/obio.h>
|
||||
#include <machine/isr.h>
|
||||
|
||||
#include "vector.h"
|
||||
|
|
@ -52,7 +55,7 @@
|
|||
*
|
||||
*/
|
||||
|
||||
extern char *interrupt_reg;
|
||||
volatile u_char *interrupt_reg;
|
||||
|
||||
extern void level0intr(), level1intr(), level2intr(), level3intr(),
|
||||
level4intr(), level5intr(), level6intr(), level7intr();
|
||||
|
|
@ -80,6 +83,10 @@ void isr_init()
|
|||
|
||||
for (i = 0; i < NISR; i++)
|
||||
isr_array[i] = NULL;
|
||||
|
||||
interrupt_reg = obio_find_mapping(OBIO_INTERREG, 1);
|
||||
if (!interrupt_reg)
|
||||
mon_panic("interrupt reg VA not found\n");
|
||||
}
|
||||
|
||||
void isr_add_custom(level, handler)
|
||||
|
|
@ -289,6 +296,8 @@ soft1intr(fp)
|
|||
if (sun3sir.sir_which[SIR_SPARE3]) {
|
||||
sun3sir.sir_which[SIR_SPARE3] = 0;
|
||||
/* spare3intr(); */
|
||||
/* XXX - For testing (db> w sun3sir 1) */
|
||||
sun3_rom_abort();
|
||||
}
|
||||
}
|
||||
return (1);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 1994 Gordon W. Ross
|
||||
* Copyright (c) 1993 Adam Glass
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -13,36 +14,47 @@
|
|||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Adam Glass.
|
||||
* 4. The name of the Author may not be used to endorse or promote products
|
||||
* 4. The name of the authors may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Adam Glass ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $Header: /cvsroot/src/sys/arch/sun3/sun3/locore.s,v 1.19 1994/07/11 03:41:29 gwr Exp $
|
||||
* $Id: locore.s,v 1.20 1994/09/20 16:52:28 gwr Exp $
|
||||
*/
|
||||
|
||||
#include "assym.s"
|
||||
#include <machine/trap.h>
|
||||
#include <machine/asm.h>
|
||||
#include <sys/syscall.h>
|
||||
| remember this is a fun project :)
|
||||
|
||||
| remember this is a fun project :)
|
||||
|
||||
| Internal stack used during process switch.
|
||||
.globl tmpstk
|
||||
.data
|
||||
tmpstk_low:
|
||||
.space NBPG
|
||||
tmpstk:
|
||||
tmpstk: |tmpstk_end
|
||||
|
||||
| This is where the UPAGES get mapped.
|
||||
.set _kstack,MONSHORTSEG
|
||||
.globl _kstack
|
||||
|
||||
| Some other handy addresses, mostly so DDB can print meaningful things.
|
||||
.set _prom_start,MONSTART
|
||||
.globl _prom_start
|
||||
.set _prom_base,PROM_BASE
|
||||
.globl _prom_base
|
||||
|
||||
.text
|
||||
.globl start; .globl _start
|
||||
|
||||
|
|
@ -60,10 +72,10 @@ start: _start:
|
|||
movsb d0, CONTEXT_REG | now in context 0
|
||||
|
||||
/*
|
||||
* In order to "move" the kernel to high memory, we are going to copy
|
||||
* the first 8 Mb of pmegs such that we will be mapped at the linked address.
|
||||
* This is all done by playing with the segment map, and then propigating it
|
||||
* to the other contexts.
|
||||
* In order to "move" the kernel to high memory, we are going to copy the
|
||||
* first 4 Mb of pmegs such that we will be mapped at the linked address.
|
||||
* This is all done by playing with the segment map, and then propagating
|
||||
* it to the other contexts.
|
||||
* We will unscramble which pmegs we actually need later.
|
||||
*
|
||||
*/
|
||||
|
|
@ -73,14 +85,12 @@ percontext: |loop among the contexts
|
|||
movl #(SEGMAP_BASE+KERNBASE), a0 | base index into seg map
|
||||
|
||||
perpmeg:
|
||||
|
||||
movsb d1, a0@ | establish mapping
|
||||
addql #1, d1
|
||||
addl #NBSG, a0
|
||||
cmpl #(MAINMEM_MONMAP / NBSG), d1 | are we done
|
||||
cmpl #(0x400000 / NBSG), d1 | up to 4MB yet?
|
||||
bne perpmeg
|
||||
|
||||
|
||||
addql #1, d0 | next context ....
|
||||
cmpl #CONTEXT_NUM, d0
|
||||
bne percontext
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 1994 Gordon W. Ross
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
* Copyright (c) 1980, 1990 The Regents of the University of California.
|
||||
* All rights reserved.
|
||||
|
|
@ -36,10 +37,9 @@
|
|||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: Utah $Hdr: locore.s 1.58 91/04/22$
|
||||
*
|
||||
* from: @(#)locore.s 7.11 (Berkeley) 5/9/91
|
||||
* locore.s,v 1.2 1993/05/22 07:57:30 cgd Exp
|
||||
* $Id: softint.s,v 1.6 1994/06/29 05:34:16 gwr Exp $
|
||||
*
|
||||
* $Id: softint.s,v 1.7 1994/09/20 16:52:29 gwr Exp $
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -61,10 +61,6 @@
|
|||
* necessitating a stack cleanup.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SSIR /* Now using isr_soft_request() */
|
||||
.comm _ssir,1
|
||||
#endif /* NEED_SSIR */
|
||||
|
||||
.globl _astpending
|
||||
rei:
|
||||
#ifdef STACKCHECK
|
||||
|
|
@ -114,40 +110,7 @@ Laststkadj:
|
|||
#endif
|
||||
|
||||
Lchksir:
|
||||
#ifdef NEED_SSIR /* Now using isr_soft_request() */
|
||||
tstb _ssir | SIR pending?
|
||||
jeq Ldorte | no, all done
|
||||
movl d0,sp@- | need a scratch register
|
||||
movw sp@(4),d0 | get SR
|
||||
andw #PSL_IPL7,d0 | mask all but IPL
|
||||
jne Lnosir | came from interrupt, no can do
|
||||
movl sp@+,d0 | restore scratch register
|
||||
Lgotsir:
|
||||
movw #SPL1,sr | prevent others from servicing int
|
||||
tstb _ssir | too late?
|
||||
jeq Ldorte | yes, oh well...
|
||||
clrl sp@- | stack adjust
|
||||
moveml #0xFFFF,sp@- | save all registers
|
||||
movl usp,a1 | including
|
||||
movl a1,sp@(FR_SP) | the users SP
|
||||
clrl sp@- | VA == none
|
||||
clrl sp@- | code == none
|
||||
movl #T_SSIR,sp@- | type == software interrupt
|
||||
jbsr _trap | go handle it
|
||||
lea sp@(12),sp | pop value args
|
||||
movl sp@(FR_SP),a0 | restore
|
||||
movl a0,usp | user SP
|
||||
moveml sp@+,#0x7FFF | and all remaining registers
|
||||
addql #8,sp | pop SP and stack adjust
|
||||
#ifdef STACKCHECK
|
||||
jra Ldorte
|
||||
#else
|
||||
rte
|
||||
#endif
|
||||
Lnosir:
|
||||
movl sp@+,d0 | restore scratch register
|
||||
#endif /* NEED_SSIR */
|
||||
|
||||
| Sun3 has real interrupt register (no need for simulated one).
|
||||
Ldorte:
|
||||
#ifdef STACKCHECK
|
||||
movw #SPL6,sr | avoid trouble
|
||||
|
|
@ -187,25 +150,16 @@ Ldorte1:
|
|||
#endif
|
||||
rte | real return
|
||||
|
||||
/* this code is un-altered from the hp300 version */
|
||||
/*
|
||||
* Set processor priority level calls. Most are implemented with
|
||||
* inline asm expansions. However, spl0 requires special handling
|
||||
* as we need to check for our emulated software interrupts.
|
||||
*/
|
||||
|
||||
ENTRY(spl0)
|
||||
moveq #0,d0
|
||||
movw sr,d0 | get old SR for return
|
||||
movw #PSL_LOWIPL,sr | restore new SR
|
||||
#ifdef NEED_SSIR /* Now using isr_soft_request() */
|
||||
tstb _ssir | software interrupt pending?
|
||||
jeq Lspldone | no, all done
|
||||
subql #4,sp | make room for RTE frame
|
||||
movl sp@(4),sp@(2) | position return address
|
||||
clrw sp@(6) | set frame type 0
|
||||
movw #PSL_LOWIPL,sp@ | and new SR
|
||||
jra Lgotsir | go handle it
|
||||
Lspldone:
|
||||
#endif /* NEED_SSIR */
|
||||
| Set processor priority level calls. Most are implemented with
|
||||
| inline asm expansions. However, we need one instantiation here
|
||||
| in case some non-optimized code makes external references.
|
||||
| Most places will use the inlined function param.h supplies.
|
||||
.globl __spl
|
||||
__spl:
|
||||
movl sp@(4),d1
|
||||
clrl d0
|
||||
movw sr,d0
|
||||
movw d1,sr
|
||||
rts
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 1994 Gordon W. Ross
|
||||
* Copyright (c) 1993 Adam Glass
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
* Copyright (c) 1982, 1986, 1990, 1993
|
||||
|
|
@ -38,7 +39,7 @@
|
|||
*
|
||||
* from: Utah Hdr: trap.c 1.37 92/12/20
|
||||
* from: @(#)trap.c 8.5 (Berkeley) 1/4/94
|
||||
* $Id: trap.c,v 1.27 1994/07/19 02:45:55 gwr Exp $
|
||||
* $Id: trap.c,v 1.28 1994/09/20 16:52:30 gwr Exp $
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
|
|
@ -353,39 +354,7 @@ trap(type, code, v, frame)
|
|||
|
||||
case T_ASTFLT|T_USER: /* user async trap */
|
||||
astpending = 0;
|
||||
#ifdef NEED_SSIR /* Now using isr_soft_request() */
|
||||
/*
|
||||
* We check for software interrupts first. This is because
|
||||
* they are at a higher level than ASTs, and on a VAX would
|
||||
* interrupt the AST. We assume that if we are processing
|
||||
* an AST that we must be at IPL0 so we don't bother to
|
||||
* check. Note that we ensure that we are at least at SIR
|
||||
* IPL while processing the SIR.
|
||||
*/
|
||||
spl1();
|
||||
/*FALLTHROUGH*/
|
||||
|
||||
case T_SSIR: /* software interrupt */
|
||||
case T_SSIR|T_USER:
|
||||
if (ssir & SIR_NET) {
|
||||
siroff(SIR_NET);
|
||||
cnt.v_soft++;
|
||||
netintr();
|
||||
}
|
||||
if (ssir & SIR_CLOCK) {
|
||||
siroff(SIR_CLOCK);
|
||||
cnt.v_soft++;
|
||||
softclock();
|
||||
}
|
||||
/*
|
||||
* If this was not an AST trap, we are all done.
|
||||
*/
|
||||
if (type != (T_ASTFLT|T_USER)) {
|
||||
cnt.v_trap--;
|
||||
return;
|
||||
}
|
||||
spl0();
|
||||
#endif /* NEED_SSIR */
|
||||
/* T_SSIR is not used on a Sun3. */
|
||||
if (p->p_flag & P_OWEUPC) {
|
||||
p->p_flag &= ~P_OWEUPC;
|
||||
ADDUPROF(p);
|
||||
|
|
|
|||
Loading…
Reference in New Issue