- The Captured Slot Power Limit value is only for device which has upsteam
port.
- The following three registers are the same encoding, so use the same
function:
- the Captured Slot Power Limit in the Device Capability register of PICe
capability.
- the Slot Power Limit in Slot Capability register of PCIe capability.
- the Base Power and Data Scale in the Data Register of Power Budgeting
capability.
- Fix the alternative encoding check of power limit as document. Add check if
scale equals to 0.
This commit is contained in:
msaitoh
parent
3029325a38
commit
551ee3e68c
@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.180 2017/05/09 11:17:07 msaitoh Exp $ */
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/* $NetBSD: pci_subr.c,v 1.181 2017/05/22 04:21:20 msaitoh Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.180 2017/05/09 11:17:07 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.181 2017/05/22 04:21:20 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_pci.h"
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@ -71,6 +71,7 @@ __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.180 2017/05/09 11:17:07 msaitoh Exp $
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#endif
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static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *);
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static void pci_conf_print_pcie_power(uint8_t, unsigned int);
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/*
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* Descriptions of known PCI classes and subclasses.
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@ -1651,6 +1652,7 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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bool check_link = true;
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bool check_slot = false;
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bool check_rootport = false;
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bool check_upstreamport = false;
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unsigned int pciever;
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unsigned int i;
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@ -1664,9 +1666,11 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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switch ((reg & 0x00f00000) >> 20) {
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case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */
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printf("PCI Express Endpoint device\n");
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check_upstreamport = true;
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break;
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case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */
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printf("Legacy PCI Express Endpoint device\n");
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check_upstreamport = true;
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break;
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case PCIE_XCAP_TYPE_ROOT: /* 0x4 */
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printf("Root Port of PCI Express Root Complex\n");
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@ -1675,6 +1679,7 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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break;
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case PCIE_XCAP_TYPE_UP: /* 0x5 */
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printf("Upstream Port of PCI Express Switch\n");
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check_upstreamport = true;
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break;
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case PCIE_XCAP_TYPE_DOWN: /* 0x6 */
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printf("Downstream Port of PCI Express Switch\n");
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@ -1683,9 +1688,11 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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break;
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case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */
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printf("PCI Express to PCI/PCI-X Bridge\n");
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check_upstreamport = true;
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break;
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case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */
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printf("PCI/PCI-X to PCI Express Bridge\n");
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/* Upstream port is not PCIe */
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check_slot = true;
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break;
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case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
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@ -1735,10 +1742,12 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);
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onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);
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onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT);
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printf(" Captured Slot Power Limit Value: %u\n",
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(unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL));
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printf(" Captured Slot Power Limit Scale: %u\n",
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(unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE));
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if (check_upstreamport) {
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printf(" Captured Slot Power Limit: ");
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pci_conf_print_pcie_power(
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__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL),
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__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE));
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}
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onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR);
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/* Device Control Register */
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@ -1882,10 +1891,9 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP);
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onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);
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onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);
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printf(" Slot Power Limit Value: %d\n",
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(unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7);
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printf(" Slot Power Limit Scale: %d\n",
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(unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15);
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printf(" Slot Power Limit Value: ");
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pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV),
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__SHIFTOUT(reg, PCIE_SLCAP_SPLS));
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onoff("Electromechanical Interlock Present", reg,
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PCIE_SLCAP_EIP);
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onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS);
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@ -2700,40 +2708,47 @@ pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff)
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" VC", varbsel, varbsize);
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}
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/*
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* Print Power limit. This encoding is the same among the following registers:
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* - The Captured Slot Power Limit in the PCIe Device Capability Register.
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* - The Slot Power Limit in the PCIe Slot Capability Register.
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* - The Base Power in the Data register of Power Budgeting capability.
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*/
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static void
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pci_conf_print_pwrbdgt_base_power(uint8_t base, unsigned int scale)
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pci_conf_print_pcie_power(uint8_t base, unsigned int scale)
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{
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if (base <= 0xef) {
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unsigned int sdiv = 1;
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for (unsigned int i = scale; i > 0; i--)
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sdiv *= 10;
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unsigned int sdiv = 1;
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printf("%u", base / sdiv);
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if ((scale == 0) && (base > 0xef)) {
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const char *s;
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if (scale != 0) {
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printf(".%u", base % sdiv);
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switch (base) {
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case 0xf0:
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s = "239W < x <= 250W";
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break;
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case 0xf1:
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s = "250W < x <= 275W";
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break;
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case 0xf2:
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s = "275W < x <= 300W";
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break;
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default:
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s = "reserved for above 300W";
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break;
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}
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printf ("W\n");
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return;
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printf("%s\n", s);
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}
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const char *s;
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for (unsigned int i = scale; i > 0; i--)
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sdiv *= 10;
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switch (base) {
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case 0xf0:
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s = "239W < x <= 250W";
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break;
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case 0xf1:
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s = "250W < x <= 275W";
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break;
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case 0xf2:
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s = "275W < x <= 300W";
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break;
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default:
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s = "reserved for above 300W";
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break;
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printf("%u", base / sdiv);
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if (scale != 0) {
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printf(".%u", base % sdiv);
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}
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printf("%s\n", s);
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printf ("W\n");
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return;
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}
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static const char *
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@ -2782,7 +2797,6 @@ static void
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pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff)
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{
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pcireg_t reg;
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unsigned int scale;
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printf("\n Power Budgeting\n");
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@ -2791,9 +2805,10 @@ pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff)
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reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)];
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printf(" Data register: 0x%08x\n", reg);
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scale = __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE);
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printf(" Base Power: ");
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pci_conf_print_pwrbdgt_base_power((uint8_t)reg, scale);
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pci_conf_print_pcie_power(
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__SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR),
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__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE));
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printf(" PM Sub State: 0x%hhx\n",
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(uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT));
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printf(" PM State: D%u\n",
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