remove cache_flush_virt() and PADDRT, they're no longer used.
allocate a stack frame for blast_dcache() when profiling so it shows up. in dcache_flush_page(), use a stride of 32 instead of 16 to match the cache line size. correct various comments.
This commit is contained in:
chs
parent
2db3939de3
commit
5500ae7993
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.h,v 1.6 2002/09/29 04:12:03 chs Exp $ */
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/* $NetBSD: cache.h,v 1.7 2004/12/03 02:04:00 chs Exp $ */
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/*
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* Copyright (c) 1996
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@ -79,7 +79,6 @@ void blast_dcache __P((void)); /* Clear entire D$ */
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void blast_icache __P((void)); /* Clear entire I$ */
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/* The following flush a range from the D$ and I$ but not E$. */
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void cache_flush_virt __P((vaddr_t, vsize_t));
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void cache_flush_phys __P((paddr_t, psize_t, int));
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/*
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.36 2004/03/26 23:18:42 petrov Exp $
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# $NetBSD: genassym.cf,v 1.37 2004/12/03 02:04:00 chs Exp $
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#
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# Copyright (c) 1997 The NetBSD Foundation, Inc.
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@ -116,7 +116,6 @@ endif
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# general constants
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define BSD BSD
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define USRSTACK USRSTACK
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define PADDRT sizeof(paddr_t)
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define PAGE_SIZE PAGE_SIZE
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# Important offsets into the lwp and proc structs & associated constants
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.200 2004/11/08 08:55:43 petrov Exp $ */
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/* $NetBSD: locore.s,v 1.201 2004/12/03 02:04:00 chs Exp $ */
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/*
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* Copyright (c) 1996-2002 Eduardo Horvath
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@ -858,33 +858,33 @@ _C_LABEL(trapbase):
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UTRAP(T_ECCERR) ! We'll implement this one later
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ufast_IMMU_miss: ! 064 = fast instr access MMU miss
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TRACEFLT ! DEBUG
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ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
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ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
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#ifdef NO_TSB
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ba,a %icc, instr_miss;
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ba,a %icc, instr_miss
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#endif
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ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
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ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 !Load TSB tag:data into %g4:%g5
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brgez,pn %g5, instr_miss ! Entry invalid? Punt
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cmp %g1, %g4 ! Compare TLB tags
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bne,pn %xcc, instr_miss ! Got right tag?
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ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
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ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag:data into %g4:%g5
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brgez,pn %g5, instr_miss ! Entry invalid? Punt
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cmp %g1, %g4 ! Compare TLB tags
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bne,pn %xcc, instr_miss ! Got right tag?
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nop
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CLRTT
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stxa %g5, [%g0] ASI_IMMU_DATA_IN! Enter new mapping
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retry ! Try new mapping
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stxa %g5, [%g0] ASI_IMMU_DATA_IN ! Enter new mapping
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retry ! Try new mapping
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1:
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sir
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TA32
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ufast_DMMU_miss: ! 068 = fast data access MMU miss
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TRACEFLT ! DEBUG
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ldxa [%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
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ldxa [%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
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#ifdef NO_TSB
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ba,a %icc, data_miss;
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ba,a %icc, data_miss
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#endif
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ldxa [%g0] ASI_DMMU, %g1 ! Hard coded for unified 8K TSB Load DMMU tag target register
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ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag and data into %g4 and %g5
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brgez,pn %g5, data_miss ! Entry invalid? Punt
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cmp %g1, %g4 ! Compare TLB tags
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bnz,pn %xcc, data_miss ! Got right tag?
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ldxa [%g0] ASI_DMMU, %g1 ! Load DMMU tag target register
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ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag and data into %g4 and %g5
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brgez,pn %g5, data_miss ! Entry invalid? Punt
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cmp %g1, %g4 ! Compare TLB tags
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bnz,pn %xcc, data_miss ! Got right tag?
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nop
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CLRTT
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#ifdef TRAPSTATS
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@ -893,8 +893,8 @@ ufast_DMMU_miss: ! 068 = fast data access MMU miss
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inc %g2
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stw %g2, [%g1+%lo(_C_LABEL(udhit))]
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#endif
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stxa %g5, [%g0] ASI_DMMU_DATA_IN! Enter new mapping
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retry ! Try new mapping
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stxa %g5, [%g0] ASI_DMMU_DATA_IN ! Enter new mapping
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retry ! Try new mapping
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1:
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sir
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TA32
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@ -1101,33 +1101,33 @@ kdatafault:
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UTRAP(T_ECCERR) ! We'll implement this one later
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kfast_IMMU_miss: ! 064 = fast instr access MMU miss
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TRACEFLT ! DEBUG
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ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
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ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
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#ifdef NO_TSB
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ba,a %icc, instr_miss;
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ba,a %icc, instr_miss
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#endif
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ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
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ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 !Load TSB tag:data into %g4:%g5
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brgez,pn %g5, instr_miss ! Entry invalid? Punt
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cmp %g1, %g4 ! Compare TLB tags
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bne,pn %xcc, instr_miss ! Got right tag?
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ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
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ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag:data into %g4:%g5
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brgez,pn %g5, instr_miss ! Entry invalid? Punt
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cmp %g1, %g4 ! Compare TLB tags
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bne,pn %xcc, instr_miss ! Got right tag?
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nop
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CLRTT
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stxa %g5, [%g0] ASI_IMMU_DATA_IN! Enter new mapping
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retry ! Try new mapping
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stxa %g5, [%g0] ASI_IMMU_DATA_IN ! Enter new mapping
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retry ! Try new mapping
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1:
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sir
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TA32
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kfast_DMMU_miss: ! 068 = fast data access MMU miss
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TRACEFLT ! DEBUG
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ldxa [%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
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ldxa [%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
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#ifdef NO_TSB
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ba,a %icc, data_miss;
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ba,a %icc, data_miss
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#endif
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ldxa [%g0] ASI_DMMU, %g1 ! Hard coded for unified 8K TSB Load DMMU tag target register
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ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag and data into %g4 and %g5
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brgez,pn %g5, data_miss ! Entry invalid? Punt
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cmp %g1, %g4 ! Compare TLB tags
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bnz,pn %xcc, data_miss ! Got right tag?
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ldxa [%g0] ASI_DMMU, %g1 ! Load DMMU tag target register
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ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag and data into %g4 and %g5
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brgez,pn %g5, data_miss ! Entry invalid? Punt
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cmp %g1, %g4 ! Compare TLB tags
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bnz,pn %xcc, data_miss ! Got right tag?
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nop
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CLRTT
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#ifdef TRAPSTATS
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@ -1136,8 +1136,8 @@ kfast_DMMU_miss: ! 068 = fast data access MMU miss
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inc %g2
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stw %g2, [%g1+%lo(_C_LABEL(kdhit))]
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#endif
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stxa %g5, [%g0] ASI_DMMU_DATA_IN! Enter new mapping
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retry ! Try new mapping
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stxa %g5, [%g0] ASI_DMMU_DATA_IN ! Enter new mapping
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retry ! Try new mapping
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1:
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sir
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TA32
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@ -2095,8 +2095,8 @@ dmmu_write_fault:
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and %g6, PTMASK, %g6
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add %g5, %g4, %g5
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brz,pn %g4, winfix ! NULL entry? check somewhere else
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nop
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ldxa [%g5] ASI_PHYS_CACHED, %g4
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sll %g6, 3, %g6
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brz,pn %g4, winfix ! NULL entry? check somewhere else
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@ -2126,9 +2126,8 @@ dmmu_write_fault:
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ldxa [%g0] ASI_DMMU_8KPTR, %g2 ! Load DMMU 8K TSB pointer
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andcc %g5, 0x3, %g5 ! 8K?
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bnz,pn %icc, winfix ! We punt to the pmap code since we can't handle policy
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ldxa [%g0] ASI_DMMU, %g1 ! Hard coded for unified 8K TSB Load DMMU tag target register
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ldxa [%g0] ASI_DMMU, %g1 ! Load DMMU tag target register
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casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and write it out
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membar #StoreLoad
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cmp %g4, %g7
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bne,pn %xcc, 1b
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@ -2137,6 +2136,7 @@ dmmu_write_fault:
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mov SFSR, %g7
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stx %g4, [%g2+8] ! Update TSB entry data
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nop
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#ifdef DEBUG
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set DATA_START, %g6 ! debug
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stx %g1, [%g6+0x40] ! debug
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@ -6695,6 +6695,10 @@ ENTRY(blast_dcache)
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/*
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* We turn off interrupts for the duration to prevent RED exceptions.
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*/
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#ifdef PROF
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save %sp, -CC64FSZ, %sp
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#endif
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rdpr %pstate, %o3
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set (2 * NBPG) - 8, %o1
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andn %o3, PSTATE_IE, %o4 ! Turn off PSTATE_IE bit
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@ -6705,8 +6709,14 @@ ENTRY(blast_dcache)
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dec 8, %o1
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sethi %hi(KERNBASE), %o2
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flush %o2
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#ifdef PROF
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wrpr %o3, %pstate
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ret
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restore
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#else
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retl
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wrpr %o3, %pstate
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#endif
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/*
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* blast_icache()
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@ -6733,10 +6743,8 @@ ENTRY(blast_icache)
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retl
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wrpr %o3, %pstate
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/*
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* dcache_flush_page(vaddr_t pa)
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* dcache_flush_page(paddr_t pa)
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*
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* Clear one page from D$.
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*
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@ -6746,30 +6754,27 @@ ENTRY(dcache_flush_page)
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#ifndef _LP64
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COMBINE(%o0, %o1, %o0)
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#endif
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!! Try using cache_flush_phys for a change.
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mov -1, %o1 ! Generate mask for tag: bits [29..2]
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srlx %o0, 13-2, %o2 ! Tag is VA bits <40:13> in bits <29:2>
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srlx %o0, 13-2, %o2 ! Tag is PA bits <40:13> in bits <29:2>
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clr %o4
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srl %o1, 2, %o1 ! Now we have bits <29:0> set
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set (2*NBPG), %o5
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ba,pt %icc, 1f
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andn %o1, 3, %o1 ! Now we have bits <29:2> set
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.align 8
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1:
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ldxa [%o4] ASI_DCACHE_TAG, %o3
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mov %o4, %o0
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deccc 16, %o5
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deccc 32, %o5
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bl,pn %icc, 2f
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inc 16, %o4
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inc 32, %o4
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xor %o3, %o2, %o3
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andcc %o3, %o1, %g0
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bne,pt %xcc, 1b
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membar #LoadStore
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stxa %g0, [%o0] ASI_DCACHE_TAG
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ba,pt %icc, 1b
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membar #StoreLoad
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@ -6782,7 +6787,7 @@ ENTRY(dcache_flush_page)
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membar #Sync
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/*
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* icache_flush_page(vaddr_t pa)
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* icache_flush_page(paddr_t pa)
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*
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* Clear one page from I$.
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*
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@ -6825,59 +6830,6 @@ ENTRY(icache_flush_page)
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retl
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nop
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/*
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* cache_flush_virt(vaddr_t va, vsize_t len)
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*
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* Clear everything in that va range from D$ and I$.
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*
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*/
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.align 8
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ENTRY(cache_flush_virt)
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brz,pn %o1, 2f ! What? nothing to clear?
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add %o0, %o1, %o2
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mov 0x1ff, %o3
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sllx %o3, 5, %o3 ! Generate mask for VA bits
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and %o0, %o3, %o0
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and %o2, %o3, %o2
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sub %o2, %o1, %o4 ! End < start? need to split flushes.
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sethi %hi((1<<13)), %o5
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brlz,pn %o4, 1f
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movrz %o4, %o3, %o4 ! If start == end we need to wrap
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!! Clear from start to end
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1:
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stxa %g0, [%o0] ASI_DCACHE_TAG
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dec 16, %o4
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xor %o5, %o0, %o3 ! Second way
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#ifdef SPITFIRE
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stxa %g0, [%o0] ASI_ICACHE_TAG! Don't do this on cheetah
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stxa %g0, [%o3] ASI_ICACHE_TAG! Don't do this on cheetah
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#endif
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brgz,pt %o4, 1b
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inc 16, %o0
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2:
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sethi %hi(KERNBASE), %o5
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flush %o5
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membar #Sync
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retl
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nop
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!! We got a hole. Clear from start to hole
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clr %o4
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3:
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stxa %g0, [%o4] ASI_DCACHE_TAG
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dec 16, %o1
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xor %o5, %o4, %g1 ! Second way
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stxa %g0, [%o4] ASI_ICACHE_TAG
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stxa %g0, [%g1] ASI_ICACHE_TAG
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brgz,pt %o1, 3b
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inc 16, %o4
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!! Now clear to the end.
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sub %o3, %o2, %o4 ! Size to clear (NBPG - end)
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ba,pt %icc, 1b
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mov %o2, %o0 ! Start of clear
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/*
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* cache_flush_phys __P((paddr_t, psize_t, int));
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*
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@ -8886,15 +8838,9 @@ paginuse:
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.word 0
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.text
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ENTRY(pmap_zero_page)
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!!
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!! If we have 64-bit physical addresses (and we do now)
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!! we need to move the pointer from %o0:%o1 to %o0
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!!
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#ifndef _LP64
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#if PADDRT == 8
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COMBINE(%o0, %o1, %o0)
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#endif
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#endif
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#ifdef DEBUG
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set pmapdebug, %o4
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ld [%o4], %o4
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@ -8949,16 +8895,9 @@ ENTRY(pmap_zero_page)
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*/
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ENTRY(pmap_copy_page)
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#ifndef _LP64
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!!
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!! If we have 64-bit physical addresses (and we do now)
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!! we need to move the pointer from %o0:%o1 to %o0 and
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!! %o2:%o3 to %o1
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!!
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#if PADDRT == 8
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COMBINE(%o0, %o1, %o0)
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COMBINE(%o2, %o3, %o1)
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#endif
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#endif
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#ifdef DEBUG
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set pmapdebug, %o4
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ld [%o4], %o4
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Loading…
Reference in New Issue