Vrc4172 GPIO support. This device is currently configured on PenCentra 130.
This commit is contained in:
takemura
parent
2113399bb4
commit
54d9a46bbc
@ -2,11 +2,11 @@
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# Distribution kernel (NEC VR based model) kernel config file
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#
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# $NetBSD: GENERIC,v 1.90 2001/05/06 01:54:19 hubertf Exp $
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# $NetBSD: GENERIC,v 1.91 2001/05/06 14:25:16 takemura Exp $
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#
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include "arch/hpcmips/conf/std.hpcmips"
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#ident "GENERIC-$Revision: 1.90 $"
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#ident "GENERIC-$Revision: 1.91 $"
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maxusers 10
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@ -325,10 +325,12 @@ isa4 at vrisab4
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wdc0 at isa4 port 0x170 irq 0x02000003 flags 0x0002 # single drive
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#
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# Unknown machines
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# Fujitsu PenCentra 130
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#
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vrisab4 at vrgiu?
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isa4 at vrisab4
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vrc4172gpio0 at vrgiu? platform FUJITSU_PENCENTRA_130 addr 0x15001080 size 0x4a port 10
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vrisab5 at vrc4172gpio0 isaportoffset 0x1000000
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isa5 at vrisab5
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pcic0 at isa5 port 0x3e0 iomem 0x70000 iosiz 0x4000 irq 0x00010003
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# PCMCIA bus support
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pcmcia* at pcic? controller 0 socket ?
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@ -1,4 +1,4 @@
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# $NetBSD: files.hpcmips,v 1.55 2001/04/30 11:42:18 takemura Exp $
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# $NetBSD: files.hpcmips,v 1.56 2001/05/06 14:25:16 takemura Exp $
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# maxpartitions must be first item in files.${ARCH}.
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maxpartitions 8
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@ -154,6 +154,10 @@ device vrc4172pwm
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attach vrc4172pwm at vrip
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file arch/hpcmips/vr/vrc4172pwm.c vrc4172pwm needs-flag
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device vrc4172gpio: hpcioif, vrisabif
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attach vrc4172gpio at hpcioif
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file arch/hpcmips/vr/vrc4172gpio.c vrc4172gpio
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#
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# TOSHIBA TX3912/3922
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#
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@ -1,4 +1,4 @@
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/* $NetBSD: isa_machdep.c,v 1.13 2001/04/30 11:42:18 takemura Exp $ */
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/* $NetBSD: isa_machdep.c,v 1.14 2001/05/06 14:25:16 takemura Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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@ -256,8 +256,8 @@ isa_intr_establish(ic, intr, type, level, ih_fun, ih_arg)
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mode = INTR_MODE(intr);
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port = INTR_PORT(intr);
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VPRINTF(("ISA IRQ %d -> GPIO port %d, %s\n",
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irq, port, intr_mode_names[mode]));
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VPRINTF(("ISA IRQ %d -> %s port %d, %s\n",
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irq, sc->sc_hc->hc_name, port, intr_mode_names[mode]));
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/* Call Vr routine */
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return hpcio_intr_establish(sc->sc_hc, port, intr_modes[mode],
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666
sys/arch/hpcmips/vr/vrc4172gpio.c
Normal file
666
sys/arch/hpcmips/vr/vrc4172gpio.c
Normal file
@ -0,0 +1,666 @@
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/* $NetBSD: vrc4172gpio.c,v 1.1 2001/05/06 14:25:16 takemura Exp $ */
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/*-
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* Copyright (c) 2001 TAKEMRUA Shin. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/reboot.h>
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#include <machine/bus.h>
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#include <machine/platid.h>
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#include <machine/platid_mask.h>
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#include <dev/hpc/hpciovar.h>
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#include <hpcmips/vr/vripvar.h>
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#include <hpcmips/vr/vrc4172gpioreg.h>
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#include "locators.h"
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#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
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#define VRC2GPIODEBUG
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#ifdef VRC2GPIODEBUG
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#define DBG_IO (1<<0)
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#define DBG_INTR (1<<1)
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#define DBG_INFO (1<<2)
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#ifndef VRC2GPIODEBUG_CONF
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#define VRC2GPIODEBUG_CONF 0
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#endif /* VRC2GPIODEBUG_CONF */
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int vrc4172gpio_debug = VRC2GPIODEBUG_CONF;
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#define DBG(flag) (vrc4172gpio_debug & (flag))
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#define DPRINTF(flag, arg...) do { \
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if (DBG(flag)) \
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printf(##arg); \
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} while (0)
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#else
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#define DBG(flag) (0)
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#define DPRINTF(flag, arg...) do {} while(0)
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#endif
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#define VPRINTF(arg...) do { \
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if (bootverbose) \
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printf(##arg); \
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} while (0)
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#define CHECK_PORT(x) (0 <= (x) && (x) < VRC2_EXGP_NPORTS)
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struct vrc4172gpio_intr_entry {
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int ih_port;
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int (*ih_fun)(void*);
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void *ih_arg;
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TAILQ_ENTRY(vrc4172gpio_intr_entry) ih_link;
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};
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struct vrc4172gpio_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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struct hpcio_attach_args sc_args;
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struct hpcio_chip *sc_hc;
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void *sc_intr_handle;
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u_int32_t sc_intr_mask;
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u_int32_t sc_data;
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u_int32_t sc_intr_mode[VRC2_EXGP_NPORTS];
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TAILQ_HEAD(, vrc4172gpio_intr_entry) sc_intr_head[VRC2_EXGP_NPORTS];
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struct hpcio_chip sc_iochip;
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struct hpcio_attach_args sc_haa;
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};
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int vrc4172gpio_match(struct device*, struct cfdata*, void*);
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void vrc4172gpio_attach(struct device*, struct device*, void*);
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void vrc4172gpio_callback(struct device *self);
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int vrc4172gpio_intr(void*);
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int vrc4172gpio_print(void*, const char*);
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int vrc4172gpio_port_read(hpcio_chip_t, int);
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void vrc4172gpio_port_write(hpcio_chip_t, int, int);
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void *vrc4172gpio_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*);
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void vrc4172gpio_intr_disestablish(hpcio_chip_t, void*);
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void vrc4172gpio_intr_clear(hpcio_chip_t, void*);
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void vrc4172gpio_register_iochip(hpcio_chip_t, hpcio_chip_t);
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void vrc4172gpio_update(hpcio_chip_t);
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void vrc4172gpio_dump(hpcio_chip_t);
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void vrc4172gpio_intr_dump(struct vrc4172gpio_softc *, int);
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hpcio_chip_t vrc4172gpio_getchip(void*, int);
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static void vrc4172gpio_diffport(struct vrc4172gpio_softc *sc);
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static u_int16_t read_2(struct vrc4172gpio_softc *, bus_addr_t);
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static void write_2(struct vrc4172gpio_softc *, bus_addr_t, u_int16_t);
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static u_int32_t read_4(struct vrc4172gpio_softc *, bus_addr_t);
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static void write_4(struct vrc4172gpio_softc *, bus_addr_t, u_int32_t);
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static void dumpbits(u_int32_t*, int, int, int, const char[2]);
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static struct hpcio_chip vrc4172gpio_iochip = {
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.hc_portread = vrc4172gpio_port_read,
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.hc_portwrite = vrc4172gpio_port_write,
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.hc_intr_establish = vrc4172gpio_intr_establish,
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.hc_intr_disestablish = vrc4172gpio_intr_disestablish,
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.hc_intr_clear = vrc4172gpio_intr_clear,
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.hc_register_iochip = vrc4172gpio_register_iochip,
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.hc_update = vrc4172gpio_update,
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.hc_dump = vrc4172gpio_dump,
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};
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static int intlv_regs[] = {
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VRC2_EXGPINTLV0L,
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VRC2_EXGPINTLV0H,
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VRC2_EXGPINTLV1L
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};
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struct cfattach vrc4172gpio_ca = {
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sizeof(struct vrc4172gpio_softc), vrc4172gpio_match, vrc4172gpio_attach
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};
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/*
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* regster access method
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*/
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static inline u_int16_t
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read_2(struct vrc4172gpio_softc *sc, bus_addr_t off)
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{
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return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off);
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}
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static inline void
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write_2(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int16_t data)
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{
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data);
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}
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static u_int32_t
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read_4(struct vrc4172gpio_softc *sc, bus_addr_t off)
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{
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u_int16_t reg0, reg1;
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reg0 = read_2(sc, off);
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reg1 = read_2(sc, off + VRC2_EXGP_OFFSET);
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return (reg0|(reg1<<16));
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}
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static void
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write_4(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int32_t data)
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{
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write_2(sc, off, data & 0xffff);
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write_2(sc, off + VRC2_EXGP_OFFSET, (data>>16)&0xffff);
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}
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int
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vrc4172gpio_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct hpcio_attach_args *haa = aux;
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platid_mask_t mask;
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if (strcmp(haa->haa_busname, HPCIO_BUSNAME))
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return (0);
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if (cf->cf_loc[HPCIOIFCF_PLATFORM] == 0)
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return (0);
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mask = PLATID_DEREF(cf->cf_loc[HPCIOIFCF_PLATFORM]);
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return platid_match(&platid, &mask);
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}
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void
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vrc4172gpio_attach(struct device *parent, struct device *self, void *aux)
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{
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struct hpcio_attach_args *args = aux;
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struct vrc4172gpio_softc *sc = (void*)self;
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int i, *loc, port, mode;
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u_int32_t regs[6], t0, t1, t2;
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printf("\n");
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loc = sc->sc_dev.dv_cfdata->cf_loc;
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/*
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* map bus space
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*/
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sc->sc_iot = args->haa_iot;
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sc->sc_hc = (*args->haa_getchip)(args->haa_sc, loc[HPCIOIFCF_IOCHIP]);
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sc->sc_args = *args; /* structure copy */
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bus_space_map(sc->sc_iot, loc[HPCIOIFCF_ADDR], loc[HPCIOIFCF_SIZE],
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0 /* no cache */, &sc->sc_ioh);
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if (sc->sc_ioh == NULL) {
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printf("%s: can't map bus space\n", sc->sc_dev.dv_xname);
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return;
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}
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/*
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* dump Windows CE register setting
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*/
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regs[0] = read_4(sc, VRC2_EXGPDATA);
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regs[1] = read_4(sc, VRC2_EXGPDIR);
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regs[2] = read_4(sc, VRC2_EXGPINTEN);
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regs[3] = read_4(sc, VRC2_EXGPINTTYP);
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t0 = read_2(sc, VRC2_EXGPINTLV0L);
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t1 = read_2(sc, VRC2_EXGPINTLV0H);
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t2 = read_2(sc, VRC2_EXGPINTLV1L);
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regs[4] = ((t2&0xff00)<<8) | (t1&0xff00) | ((t0&0xff00)>>8);
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regs[5] = ((t2&0xff)<<16) | ((t1&0xff)<<8) | (t0&0xff);
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if (bootverbose || DBG(DBG_INFO)) {
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/*
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* o: output
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* i: input (no interrupt)
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* H: level sense interrupt (active high)
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* L: level sense interrupt (active low)
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* B: both edge trigger interrupt
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* P: positive edge trigger interrupt
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* N: negative edge trigger interrupt
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*/
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printf(" port#:321098765432109876543210\n");
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printf(" EXGPDATA :");
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dumpbits(®s[0], 1, 23, 0, "10\n");
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printf("WIN setting:");
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dumpbits(®s[1], 5, 23, 0,
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"oooo" /* dir=1 en=1 typ=1 */
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"oooo" /* dir=1 en=1 typ=0 */
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"oooo" /* dir=1 en=0 typ=1 */
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"oooo" /* dir=1 en=0 typ=0 */
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"BBPN" /* dir=0 en=1 typ=1 */
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"HLHL" /* dir=0 en=1 typ=0 */
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"iiii" /* dir=0 en=0 typ=1 */
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"iiii" /* dir=0 en=0 typ=0 */
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);
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printf("\n");
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}
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#ifdef VRC2GPIODEBUG
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if (DBG(DBG_INFO)) {
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printf(" EXGPDIR :");
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dumpbits(®s[1], 1, 23, 0, "oi\n");
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printf(" EXGPINTEN :");
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dumpbits(®s[2], 1, 23, 0, "I-\n");
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printf(" EXGPINTTYP:");
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dumpbits(®s[3], 1, 23, 0, "EL\n");
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printf(" EXPIB :");
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dumpbits(®s[4], 1, 23, 0, "10\n");
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printf(" EXPIL :");
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dumpbits(®s[5], 1, 23, 0, "10\n");
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printf(" EXGPINTLV :%04x %04x %04x\n", t2, t1, t0);
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}
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#endif /* VRC2GPIODEBUG */
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/*
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* initialize register and internal data
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*/
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sc->sc_intr_mask = 0;
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write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask);
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for (i = 0; i < VRC2_EXGP_NPORTS; i++)
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TAILQ_INIT(&sc->sc_intr_head[i]);
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sc->sc_data = read_4(sc, VRC2_EXGPDATA);
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if (bootverbose || DBG(DBG_INFO)) {
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u_int32_t data;
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sc->sc_intr_mask = (~read_4(sc, VRC2_EXGPDIR) & 0xffffff);
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write_4(sc, VRC2_EXGPINTTYP, 0); /* level sence interrupt */
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data = ~read_4(sc, VRC2_EXGPDATA);
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write_2(sc, VRC2_EXGPINTLV0L, (data >> 0) & 0xff);
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write_2(sc, VRC2_EXGPINTLV0H, (data >> 8) & 0xff);
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write_2(sc, VRC2_EXGPINTLV1L, (data >> 16) & 0xff);
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}
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/*
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* install interrupt handler
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*/
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port = loc[HPCIOIFCF_PORT];
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mode = HPCIO_INTR_LEVEL | HPCIO_INTR_HIGH;
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sc->sc_intr_handle =
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hpcio_intr_establish(sc->sc_hc, port, mode, vrc4172gpio_intr, sc);
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if (sc->sc_intr_handle == NULL) {
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printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname);
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return;
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}
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/*
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* fill hpcio_chip structure
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*/
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sc->sc_iochip = vrc4172gpio_iochip; /* structure copy */
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sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRC4172GPIO;
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sc->sc_iochip.hc_name = sc->sc_dev.dv_xname;
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sc->sc_iochip.hc_sc = sc;
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/* Register functions to upper interface */
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hpcio_register_iochip(sc->sc_hc, &sc->sc_iochip);
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/*
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* hpcio I/F
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*/
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sc->sc_haa.haa_busname = HPCIO_BUSNAME;
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sc->sc_haa.haa_sc = sc;
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sc->sc_haa.haa_getchip = vrc4172gpio_getchip;
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sc->sc_haa.haa_iot = sc->sc_iot;
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while (config_found(self, &sc->sc_haa, vrc4172gpio_print)) ;
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/*
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* GIU-ISA bridge
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*/
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#if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/
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config_defer(self, vrc4172gpio_callback);
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#else
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vrc4172gpio_callback(self);
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#endif
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}
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void
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vrc4172gpio_callback(struct device *self)
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{
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struct vrc4172gpio_softc *sc = (void*)self;
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sc->sc_haa.haa_busname = "vrisab";
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config_found(self, &sc->sc_haa, vrc4172gpio_print);
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}
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||||
|
||||
int
|
||||
vrc4172gpio_print(void *aux, const char *pnp)
|
||||
{
|
||||
if (pnp)
|
||||
return (QUIET);
|
||||
return (UNCONF);
|
||||
}
|
||||
|
||||
/*
|
||||
* PORT
|
||||
*/
|
||||
int
|
||||
vrc4172gpio_port_read(hpcio_chip_t hc, int port)
|
||||
{
|
||||
struct vrc4172gpio_softc *sc = hc->hc_sc;
|
||||
int on;
|
||||
|
||||
if (!CHECK_PORT(port))
|
||||
panic("%s: illegal gpio port", __FUNCTION__);
|
||||
|
||||
on = (read_4(sc, VRC2_EXGPDATA) & (1 << port));
|
||||
|
||||
return (on ? 1 : 0);
|
||||
}
|
||||
|
||||
void
|
||||
vrc4172gpio_port_write(hpcio_chip_t hc, int port, int onoff)
|
||||
{
|
||||
struct vrc4172gpio_softc *sc = hc->hc_sc;
|
||||
u_int32_t data;
|
||||
|
||||
if (!CHECK_PORT(port))
|
||||
panic("%s: illegal gpio port", __FUNCTION__);
|
||||
data = read_4(sc, VRC2_EXGPDATA);
|
||||
if (onoff)
|
||||
data |= (1<<port);
|
||||
else
|
||||
data &= ~(1<<port);
|
||||
write_4(sc, VRC2_EXGPDATA, data);
|
||||
}
|
||||
|
||||
void
|
||||
vrc4172gpio_update(hpcio_chip_t hc)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
vrc4172gpio_intr_dump(struct vrc4172gpio_softc *sc, int port)
|
||||
{
|
||||
u_int32_t mask, mask2;
|
||||
int intlv_reg;
|
||||
|
||||
mask = (1 << port);
|
||||
mask2 = (1 << (port % 8));
|
||||
intlv_reg = intlv_regs[port/8];
|
||||
|
||||
if (read_4(sc, VRC2_EXGPDIR) & mask) {
|
||||
printf(" output");
|
||||
return;
|
||||
}
|
||||
printf(" input");
|
||||
|
||||
if (read_4(sc, VRC2_EXGPINTTYP) & mask) {
|
||||
if (read_4(sc, intlv_reg) & (mask2 << 8)) {
|
||||
printf(", both edge");
|
||||
} else {
|
||||
if (read_4(sc, intlv_reg) & mask2)
|
||||
printf(", positive edge");
|
||||
else
|
||||
printf(", negative edge");
|
||||
}
|
||||
} else {
|
||||
if (read_4(sc, intlv_reg) & mask2)
|
||||
printf(", high level");
|
||||
else
|
||||
printf(", low level");
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
vrc4172gpio_diffport(struct vrc4172gpio_softc *sc)
|
||||
{
|
||||
u_int32_t data;
|
||||
data = read_4(sc, VRC2_EXGPDATA);
|
||||
if (sc->sc_data != data) {
|
||||
printf(" port# 321098765432109876543210\n");
|
||||
printf("vrc4172data:");
|
||||
dumpbits(&data, 1, 23, 0, "10\n");
|
||||
/* bits which changed */
|
||||
data = (data & ~sc->sc_data)|(~data & sc->sc_data);
|
||||
printf(" ");
|
||||
dumpbits(&data, 1, 23, 0, "^ \n");
|
||||
sc->sc_data = data;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
dumpbits(u_int32_t *data, int ndata, int start, int end, const char *sym)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
if (start <= end)
|
||||
panic("%s(%d): %s", __FILE__, __LINE__, __FUNCTION__);
|
||||
|
||||
for (i = start; end <= i; i--) {
|
||||
int d = 0;
|
||||
for (j = 0; j < ndata; j++)
|
||||
d = (d << 1) | ((data[j] & (1 << i)) ? 1 : 0);
|
||||
printf("%c", sym[(1 << ndata) - d - 1]);
|
||||
|
||||
}
|
||||
if (sym[1<<ndata])
|
||||
printf("%c", sym[1<<ndata]);
|
||||
}
|
||||
|
||||
void
|
||||
vrc4172gpio_dump(hpcio_chip_t hc)
|
||||
{
|
||||
}
|
||||
|
||||
hpcio_chip_t
|
||||
vrc4172gpio_getchip(void* scx, int chipid)
|
||||
{
|
||||
struct vrc4172gpio_softc *sc = scx;
|
||||
|
||||
return (&sc->sc_iochip);
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupt staff
|
||||
*/
|
||||
void *
|
||||
vrc4172gpio_intr_establish(
|
||||
hpcio_chip_t hc,
|
||||
int port, /* GPIO pin # */
|
||||
int mode, /* GIU trigger setting */
|
||||
int (*ih_fun)(void*),
|
||||
void *ih_arg)
|
||||
{
|
||||
struct vrc4172gpio_softc *sc = hc->hc_sc;
|
||||
int s;
|
||||
u_int32_t reg, mask, mask2;
|
||||
struct vrc4172gpio_intr_entry *ih;
|
||||
int intlv_reg;
|
||||
|
||||
s = splhigh();
|
||||
|
||||
if (!CHECK_PORT(port))
|
||||
panic (__FUNCTION__": bogus interrupt line");
|
||||
if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port])
|
||||
panic (__FUNCTION__": bogus interrupt type");
|
||||
else
|
||||
sc->sc_intr_mode[port] = mode;
|
||||
|
||||
mask = (1 << port);
|
||||
mask2 = (1 << (port % 8));
|
||||
intlv_reg = intlv_regs[port/8];
|
||||
|
||||
ih = malloc(sizeof(struct vrc4172gpio_intr_entry), M_DEVBUF, M_NOWAIT);
|
||||
if (ih == NULL)
|
||||
panic(__FUNCTION__": no memory");
|
||||
|
||||
ih->ih_port = port;
|
||||
ih->ih_fun = ih_fun;
|
||||
ih->ih_arg = ih_arg;
|
||||
TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link);
|
||||
|
||||
#ifdef VRC2GPIODEBUG
|
||||
if (DBG(DBG_INFO)) {
|
||||
printf("port %2d:", port);
|
||||
vrc4172gpio_intr_dump(sc, port);
|
||||
printf("->");
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Setup registers
|
||||
*/
|
||||
/* I/O direction */
|
||||
reg = read_4(sc, VRC2_EXGPDIR);
|
||||
reg &= ~mask;
|
||||
write_4(sc, VRC2_EXGPDIR, reg);
|
||||
|
||||
/* interrupt triger (level/edge) */
|
||||
reg = read_4(sc, VRC2_EXGPINTTYP);
|
||||
if (mode & HPCIO_INTR_EDGE)
|
||||
reg |= mask; /* edge */
|
||||
else
|
||||
reg &= ~mask; /* level */
|
||||
write_4(sc, VRC2_EXGPINTTYP, reg);
|
||||
|
||||
/* interrupt trigger option */
|
||||
reg = read_4(sc, intlv_reg);
|
||||
if (mode & HPCIO_INTR_EDGE) {
|
||||
switch (mode & (HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE)) {
|
||||
case HPCIO_INTR_POSEDGE:
|
||||
reg &= ~(mask2 << 8);
|
||||
reg |= mask2;
|
||||
break;
|
||||
case HPCIO_INTR_NEGEDGE:
|
||||
reg &= ~(mask2 << 8);
|
||||
reg &= ~mask2;
|
||||
break;
|
||||
case HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE:
|
||||
default:
|
||||
reg |= (mask2 << 8);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
if (mode & HPCIO_INTR_HIGH)
|
||||
reg |= mask2; /* high */
|
||||
else
|
||||
reg &= ~mask2; /* low */
|
||||
}
|
||||
write_4(sc, intlv_reg, reg);
|
||||
|
||||
#ifdef VRC2GPIODEBUG
|
||||
if (DBG(DBG_INFO)) {
|
||||
vrc4172gpio_intr_dump(sc, port);
|
||||
printf("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* XXX, Vrc4172 doesn't have register to set hold or through */
|
||||
|
||||
/*
|
||||
* clear interrupt status and enable interrupt
|
||||
*/
|
||||
vrc4172gpio_intr_clear(&sc->sc_iochip, ih);
|
||||
sc->sc_intr_mask |= mask;
|
||||
write_4(sc, VRC2_EXGPINTEN, sc->sc_intr_mask);
|
||||
|
||||
splx(s);
|
||||
|
||||
DPRINTF(DBG_INFO, "\n");
|
||||
|
||||
return (ih);
|
||||
}
|
||||
|
||||
void
|
||||
vrc4172gpio_intr_disestablish(hpcio_chip_t hc, void *arg)
|
||||
{
|
||||
struct vrc4172gpio_intr_entry *ihe = arg;
|
||||
struct vrc4172gpio_softc *sc = hc->hc_sc;
|
||||
int port = ihe->ih_port;
|
||||
struct vrc4172gpio_intr_entry *ih;
|
||||
int s;
|
||||
|
||||
s = splhigh();
|
||||
TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) {
|
||||
if (ih == ihe) {
|
||||
TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link);
|
||||
free(ih, M_DEVBUF);
|
||||
if (TAILQ_EMPTY(&sc->sc_intr_head[port])) {
|
||||
/* disable interrupt */
|
||||
sc->sc_intr_mask &= ~(1<<port);
|
||||
write_4(sc, VRC2_EXGPINTEN,
|
||||
sc->sc_intr_mask);
|
||||
}
|
||||
splx(s);
|
||||
return;
|
||||
}
|
||||
}
|
||||
panic(__FUNCTION__": no such a handle.");
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
/* Clear interrupt */
|
||||
void
|
||||
vrc4172gpio_intr_clear(hpcio_chip_t hc, void *arg)
|
||||
{
|
||||
struct vrc4172gpio_softc *sc = hc->hc_sc;
|
||||
struct vrc4172gpio_intr_entry *ihe = arg;
|
||||
|
||||
write_4(sc, VRC2_EXGPINTST, 1 << ihe->ih_port);
|
||||
write_4(sc, VRC2_EXGPINTST, 0);
|
||||
}
|
||||
|
||||
void
|
||||
vrc4172gpio_register_iochip(hpcio_chip_t hc, hpcio_chip_t iochip)
|
||||
{
|
||||
struct vrc4172gpio_softc *sc = hc->hc_sc;
|
||||
|
||||
hpcio_register_iochip(sc->sc_hc, iochip);
|
||||
}
|
||||
|
||||
/* interrupt handler */
|
||||
int
|
||||
vrc4172gpio_intr(void *arg)
|
||||
{
|
||||
struct vrc4172gpio_softc *sc = arg;
|
||||
int i;
|
||||
u_int32_t reg;
|
||||
|
||||
/* dispatch handler */
|
||||
reg = read_4(sc, VRC2_EXGPINTST);
|
||||
DPRINTF(DBG_INTR, "%s: EXGPINTST=%06x\n", __FUNCTION__, reg);
|
||||
for (i = 0; i < VRC2_EXGP_NPORTS; i++) {
|
||||
if (reg & (1 << i)) {
|
||||
register struct vrc4172gpio_intr_entry *ih;
|
||||
|
||||
/*
|
||||
* call interrupt handler
|
||||
*/
|
||||
TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) {
|
||||
ih->ih_fun(ih->ih_arg);
|
||||
}
|
||||
|
||||
/*
|
||||
* disable interrupt if no handler is installed
|
||||
*/
|
||||
if (TAILQ_EMPTY(&sc->sc_intr_head[i])) {
|
||||
sc->sc_intr_mask &= ~(1 << i);
|
||||
write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask);
|
||||
|
||||
/* dump EXGPDATA bits which changed */
|
||||
if (bootverbose || DBG(DBG_INFO))
|
||||
vrc4172gpio_diffport(sc);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: vrc4172gpioreg.h,v 1.1 2000/11/11 04:42:08 sato Exp $ */
|
||||
/* $NetBSD: vrc4172gpioreg.h,v 1.2 2001/05/06 14:25:16 takemura Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000 SATO Kazumi. All rights reserved.
|
||||
@ -29,6 +29,14 @@
|
||||
* Vrc4172 GPIO (General Purpose I/O) Unit Registers.
|
||||
*/
|
||||
#define VRC2_EXGPREG_MAX 0x4a
|
||||
#define VRC2_EXGP_NPORTS 24
|
||||
#define VRC2_EXGP_OFFSET 0x40
|
||||
|
||||
#define VRC2_EXGPDATA VRC2_EXGPDATA0
|
||||
#define VRC2_EXGPDIR VRC2_EXGPDIR0
|
||||
#define VRC2_EXGPINTEN VRC2_EXGPINTEN0
|
||||
#define VRC2_EXGPINTST VRC2_EXGPINTST0
|
||||
#define VRC2_EXGPINTTYP VRC2_EXGPINTTYP0
|
||||
|
||||
#define VRC2_EXGPDATA0 0x00 /* I/O data (0..15) */
|
||||
#define VRC2_EXGPDIR0 0x02 /* direction (0..15) */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: vrgiu.c,v 1.21 2001/05/01 00:25:17 takemura Exp $ */
|
||||
/* $NetBSD: vrgiu.c,v 1.22 2001/05/06 14:25:16 takemura Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 1999-2001
|
||||
* Shin Takemura and PocketBSD Project. All rights reserved.
|
||||
@ -115,6 +115,7 @@ static void vrgiu_port_write(hpcio_chip_t, int, int);
|
||||
static void *vrgiu_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*);
|
||||
static void vrgiu_intr_disestablish(hpcio_chip_t, void*);
|
||||
static void vrgiu_intr_clear(hpcio_chip_t, void*);
|
||||
static void vrgiu_register_iochip(hpcio_chip_t, hpcio_chip_t);
|
||||
static void vrgiu_update(hpcio_chip_t);
|
||||
static void vrgiu_dump(hpcio_chip_t);
|
||||
static hpcio_chip_t vrgiu_getchip(void*, int);
|
||||
@ -125,6 +126,7 @@ static struct hpcio_chip vrgiu_iochip = {
|
||||
.hc_intr_establish = vrgiu_intr_establish,
|
||||
.hc_intr_disestablish = vrgiu_intr_disestablish,
|
||||
.hc_intr_clear = vrgiu_intr_clear,
|
||||
.hc_register_iochip = vrgiu_register_iochip,
|
||||
.hc_update = vrgiu_update,
|
||||
.hc_dump = vrgiu_dump,
|
||||
};
|
||||
@ -204,6 +206,7 @@ vrgiu_attach(parent, self, aux)
|
||||
haa.haa_busname = HPCIO_BUSNAME;
|
||||
haa.haa_sc = sc;
|
||||
haa.haa_getchip = vrgiu_getchip;
|
||||
haa.haa_iot = sc->sc_iot;
|
||||
while (config_found(self, &haa, vrgiu_print)) ;
|
||||
/*
|
||||
* GIU-ISA bridge
|
||||
@ -225,6 +228,7 @@ vrgiu_callback(self)
|
||||
haa.haa_busname = "vrisab";
|
||||
haa.haa_sc = sc;
|
||||
haa.haa_getchip = vrgiu_getchip;
|
||||
haa.haa_iot = sc->sc_iot;
|
||||
config_found(self, &haa, vrgiu_print);
|
||||
}
|
||||
|
||||
@ -631,6 +635,16 @@ vrgiu_intr_clear(hc, arg)
|
||||
vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg & ~(1 << ihe->ih_port));
|
||||
}
|
||||
|
||||
static void
|
||||
vrgiu_register_iochip(hc, iochip)
|
||||
hpcio_chip_t hc;
|
||||
hpcio_chip_t iochip;
|
||||
{
|
||||
struct vrgiu_softc *sc = hc->hc_sc;
|
||||
|
||||
vrip_gpio_register(sc->sc_vc, iochip);
|
||||
}
|
||||
|
||||
/* interrupt handler */
|
||||
int
|
||||
vrgiu_intr(arg)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: vripvar.h,v 1.3 2001/04/30 11:42:19 takemura Exp $ */
|
||||
/* $NetBSD: vripvar.h,v 1.4 2001/05/06 14:25:16 takemura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1999
|
||||
@ -50,6 +50,7 @@ struct vripbus_attach_args {
|
||||
/* Vrip GPIO chips */
|
||||
enum vrip_iochip {
|
||||
VRIP_IOCHIP_VRGIU = 0,
|
||||
VRIP_IOCHIP_VRC4172GPIO,
|
||||
VRIP_NIOCHIPS
|
||||
};
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# $NetBSD: files.hpcio,v 1.1 2001/04/30 11:42:17 takemura Exp $
|
||||
# $NetBSD: files.hpcio,v 1.2 2001/05/06 14:25:15 takemura Exp $
|
||||
# H/PC GPIO interface
|
||||
|
||||
# platform:
|
||||
@ -20,7 +20,7 @@
|
||||
# 2: negative edge
|
||||
# other: both
|
||||
|
||||
define hpcioif { [platform = -1], [iochip = -1], [id = -1], [port = -1], [active = 1], [level = -1], [edge = -1], [initvalue = -1] }
|
||||
define hpcioif { [platform = -1], [iochip = -1], [id = -1], [port = -1], [active = 1], [level = -1], [edge = -1], [initvalue = -1], [addr=-1], [size=-1] }
|
||||
|
||||
device hpcioman { [iochip = -1], [evtype = -1], [id = -1], [port = -1], [active = 1], [level = -1], [edge = -1], [initvalue = -1] }
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: hpciovar.h,v 1.2 2001/05/01 00:25:17 takemura Exp $ */
|
||||
/* $NetBSD: hpciovar.h,v 1.3 2001/05/06 14:25:15 takemura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2001 TAKEMURA Shin.
|
||||
@ -45,6 +45,7 @@ struct hpcio_chip {
|
||||
hpcio_intr_handle_t(*hc_intr_establish)(hpcio_chip_t, int, int, int (*)(void *), void*);
|
||||
void (*hc_intr_disestablish)(hpcio_chip_t, hpcio_intr_handle_t);
|
||||
void (*hc_intr_clear)(hpcio_chip_t, hpcio_intr_handle_t);
|
||||
void (*hc_register_iochip)(hpcio_chip_t, hpcio_chip_t);
|
||||
void (*hc_update)(hpcio_chip_t);
|
||||
void (*hc_dump)(hpcio_chip_t);
|
||||
};
|
||||
@ -53,6 +54,7 @@ struct hpcio_attach_args {
|
||||
char *haa_busname;
|
||||
void *haa_sc;
|
||||
hpcio_chip_t (*haa_getchip)(void*, int);
|
||||
bus_space_tag_t haa_iot; /* I/O space tag */
|
||||
};
|
||||
#define HPCIO_BUSNAME "hpcioif"
|
||||
|
||||
@ -66,6 +68,8 @@ struct hpcio_attach_args {
|
||||
((*(hc)->hc_intr_disestablish)((hc), (handle)))
|
||||
#define hpcio_intr_clear(hc, handle) \
|
||||
((*(hc)->hc_intr_clear)((hc), (handle)))
|
||||
#define hpcio_register_iochip(hc, iochip) \
|
||||
((*(hc)->hc_register_iochip)((hc), (iochip)))
|
||||
#define hpcio_update(hc) \
|
||||
((*(hc)->hc_update)(hc))
|
||||
#define hpcio_dump(hc) \
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: pwctl.c,v 1.3 2001/05/01 00:25:17 takemura Exp $ */
|
||||
/* $NetBSD: pwctl.c,v 1.4 2001/05/06 14:25:15 takemura Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1999-2001
|
||||
@ -40,6 +40,7 @@
|
||||
#include <sys/systm.h>
|
||||
#include <sys/device.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/config_hook.h>
|
||||
#include <machine/platid.h>
|
||||
#include <machine/platid_mask.h>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user