now that it's optional, kill schizo_pci_find_ino().
prepare to enable the tomatillo iocache.
This commit is contained in:
mrg
parent
111bde084e
commit
546f8cf55d
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@ -1,9 +1,10 @@
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/* $NetBSD: schizo.c,v 1.16 2010/03/11 03:54:56 mrg Exp $ */
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/* $NetBSD: schizo.c,v 1.17 2011/01/02 10:43:18 mrg Exp $ */
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/* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */
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/*
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* Copyright (c) 2002 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2003 Henric Jungheim
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* Copyright (c) 2008, 2009, 2010 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -102,7 +103,6 @@ static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *),
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static int schizo_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
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static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
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int, int (*)(void *), void *);
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static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *);
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static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
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bus_size_t, int, bus_dmamap_t *);
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@ -141,6 +141,7 @@ schizo_attach(struct device *parent, struct device *self, void *aux)
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uint64_t reg, eccctrl;
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int *busranges = NULL, nranges;
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char *str;
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bool no_sc;
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aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr);
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str = prom_getpropstring(ma->ma_node, "compatible");
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@ -213,7 +214,10 @@ schizo_attach(struct device *parent, struct device *self, void *aux)
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is = &pbm->sp_is;
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pbm->sp_sb.sb_is = is;
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if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) {
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no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0;
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if (no_sc)
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aprint_debug("%s: no streaming buffers\n", sc->sc_dv.dv_xname);
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else {
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vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40];
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/*
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@ -227,8 +231,6 @@ schizo_attach(struct device *parent, struct device *self, void *aux)
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bus_space_subregion(pbm->sp_regt, pbm->sp_regh,
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offsetof(struct schizo_pbm_regs, strbuf),
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sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb);
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} else {
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aprint_debug("%s: no streaming buffers\n", sc->sc_dv.dv_xname);
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}
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aprint_normal("%s: ", sc->sc_dv.dv_xname);
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@ -297,6 +299,22 @@ schizo_attach(struct device *parent, struct device *self, void *aux)
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schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc,
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SCZ_SERR_INO, "safari");
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#if 0
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if (sc->sc_tomatillo) {
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/*
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* We should enable the IOCACHE here.
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*/
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uint64_t iocache_csr;
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char bits[128];
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iocache_csr = schizo_pbm_read(pbm, SCZ_PCI_IOCACHE_CSR);
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snprintb(bits, sizeof(bits), TOM_IOCACHE_CSR_BITS, iocache_csr);
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printf("IOCACHE_CSR=%s\n", bits);
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printf("IOCACHE_CSR=%" PRIx64 "\n", iocache_csr);
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}
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#endif
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config_found(&sc->sc_dv, &pba, schizo_print);
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}
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@ -605,7 +623,7 @@ schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc)
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npc->spc_conf_write = schizo_conf_write;
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npc->spc_intr_map = schizo_pci_intr_map;
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npc->spc_intr_establish = schizo_pci_intr_establish;
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npc->spc_find_ino = schizo_pci_find_ino;
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npc->spc_find_ino = NULL;
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return (npc);
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}
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@ -814,54 +832,3 @@ schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
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DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie));
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return (cookie);
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}
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static int
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schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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#if 0
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struct schizo_pbm *pbm = pa->pa_pc->cookie;
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struct schizo_softc *sc = pbm->sp_sc;
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u_int bus;
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u_int dev;
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u_int pin;
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#endif
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DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n",
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PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag),
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(int)PCITAG_DEV(pa->pa_tag),
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(int)PCITAG_FUN(pa->pa_tag)));
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DPRINTF(SDB_INTMAP,
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("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n",
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pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin));
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DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n",
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PCITAG_NODE(pa->pa_intrtag),
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(int)PCITAG_BUS(pa->pa_intrtag),
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(int)PCITAG_DEV(pa->pa_intrtag),
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(int)PCITAG_FUN(pa->pa_intrtag)));
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#if 0
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bus = (pp->pp_id == PSYCHO_PBM_B);
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/*
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* If we are on a ppb, use the devno on the underlying bus when forming
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* the ivec.
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*/
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if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0)
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dev = PCITAG_DEV(pa->pa_intrtag);
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else
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dev = pa->pa_device;
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dev--;
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if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
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pp->pp_id == PSYCHO_PBM_B)
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dev--;
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pin = pa->pa_intrpin - 1;
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DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n",
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sc->sc_mode, pp->pp_id, dev, pin));
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*ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) |
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((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT);
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#endif
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return (0);
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}
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@ -1,8 +1,9 @@
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/* $NetBSD: schizoreg.h,v 1.6 2010/02/13 11:55:48 nakayama Exp $ */
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/* $NetBSD: schizoreg.h,v 1.7 2011/01/02 10:43:18 mrg Exp $ */
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/* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */
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/*
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* Copyright (c) 2002 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2010 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -129,6 +130,9 @@ struct schizo_regs {
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#define SCZ_PCI_AFAR 0x02018
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#define SCZ_PCI_DIAG 0x02020
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#define SCZ_PCI_ESTAR 0x02028
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#define SCZ_PCI_IOCACHE_CSR 0x02248
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#define SCZ_PCI_IOCACHE_TAG_DIAG_BASE 0x02250
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#define SCZ_PCI_IOCACHE_TAG_DATA_BASE 0x02290
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#define SCZ_PCI_STRBUF_CTRL 0x02800
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#define SCZ_PCI_STRBUF_FLUSH 0x02808
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#define SCZ_PCI_STRBUF_FSYNC 0x02810
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@ -251,6 +255,30 @@ struct schizo_regs {
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#define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */
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#define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */
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/* Enable prefetch bits */
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#define TOM_IOCACHE_CSR_WRT_PEN (1UL << 19UL) /* for partial line writes */
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#define TOM_IOCACHE_CSR_NCP_RDM (1UL << 18UL) /* memory read multiple (NC) */
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#define TOM_IOCACHE_CSR_NCP_ONE (1UL << 17UL) /* memory read (NC) */
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#define TOM_IOCACHE_CSR_NCP_LINE (1UL << 16UL) /* memory read line (NC) */
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#define TOM_IOCACHE_CSR_PEN_RDM (1UL << 2UL) /* memory read multiple */
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#define TOM_IOCACHE_CSR_PEN_ONE (1UL << 1UL) /* memory read */
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#define TOM_IOCACHE_CSR_PEN_LINE (1UL << 0UL) /* memory read line */
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/* Prefetch lines selection 0x0 = 1, 0x3 = 4 */
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#define TOM_IOCACHE_CSR_PLEN_RDM_MASK 0x000000000000c000UL /* read multiple */
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#define TOM_IOCACHE_CSR_PLEN_RDM_SHIFT 14
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#define TOM_IOCACHE_CSR_PLEN_ONE_MASK 0x0000000000003000UL /* read one */
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#define TOM_IOCACHE_CSR_PLEN_ONE_SHIFT 12
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#define TOM_IOCACHE_CSR_PLEN_LINE_MASK 0x0000000000000c00UL /* read line */
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#define TOM_IOCACHE_CSR_PLEN_LINE_SHIFT 10
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/* Prefetch offset selection 0x00 = 1, 0x7e = 127, 0x7f = invalid */
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#define TOM_IOCACHE_CSR_POFFSET_MASK 0x00000000000003f8UL
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#define TOM_IOCACHE_CSR_BITS "\177\020" \
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"b\19WRT_PEN\0b\18NCP_RDM\0b17NCP_ONE\0b\16NCP_LINE\0" \
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"f\14\2PLEN_RDM\0f\12\2PEN_ONE\0f\10\2PEN_LINE\0" \
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"f\3\7POFFSET\0" \
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"b\2PEN_RDM\0b\1PEN_ONE\0b\0PEN_LINE\0\0"
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#define TOM_IOMMU_ERR (1UL << 24)
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#define TOM_IOMMU_ERR_MASK (3UL << 25)
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#define TOM_IOMMU_PROT_ERR (0UL << 25)
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