What ISC wraps under ISC_PLATFORM_HAVEXADD appears to be 32-bit

atomic adds, and I beleive all our platforms can do that.  Therefore,
no need to conditionalize that definition under __HAVE_ATOMIC64_OPS.
This commit is contained in:
he 2015-01-01 15:28:30 +00:00
parent 79c9d5023f
commit 53f679e766
1 changed files with 0 additions and 2 deletions

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@ -270,9 +270,7 @@
* If the "xadd" operation is available on this architecture,
* ISC_PLATFORM_HAVEXADD will be defined.
*/
#ifdef __HAVE_ATOMIC64_OPS
#define ISC_PLATFORM_HAVEXADD 1
#endif
/*
* If the "xaddq" operation (64bit xadd) is available on this architecture,