What ISC wraps under ISC_PLATFORM_HAVEXADD appears to be 32-bit
atomic adds, and I beleive all our platforms can do that. Therefore, no need to conditionalize that definition under __HAVE_ATOMIC64_OPS.
This commit is contained in:
parent
79c9d5023f
commit
53f679e766
|
@ -270,9 +270,7 @@
|
|||
* If the "xadd" operation is available on this architecture,
|
||||
* ISC_PLATFORM_HAVEXADD will be defined.
|
||||
*/
|
||||
#ifdef __HAVE_ATOMIC64_OPS
|
||||
#define ISC_PLATFORM_HAVEXADD 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If the "xaddq" operation (64bit xadd) is available on this architecture,
|
||||
|
|
Loading…
Reference in New Issue