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Both Exynos4 and Exynos5 have a 24 Mhz external crystal that gets pumped up to

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the required frequencies by PLL circuits.

USB freq. seems to be tied directly to this freq.
This commit is contained in:
reinoud 2014-05-09 22:16:56 +00:00
parent bea9e0590d
commit 53eff1d429
1 changed files with 4 additions and 1 deletions
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5
sys/arch/arm/samsung/exynos_reg.h
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@ -107,7 +107,10 @@
/* standard frequency settings */
#define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */
#define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */
#define EXYNOS_USB_FREQ (24*1000*1000) /* 24 Mhz */
#define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */
#define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */
/* Watchdog register definitions */
#define EXYNOS_WDT_WTCON 0x0000