MD parts of uvm_pageidlezero.
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minoura
parent
5169345855
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53e627cd0b
@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.14 1999/05/13 14:24:27 minoura Exp $ */
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/* $NetBSD: pmap.h,v 1.15 2000/05/14 14:10:09 minoura Exp $ */
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/*
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* Copyright (c) 1987 Carnegie-Mellon University
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@ -153,4 +153,10 @@ vaddr_t pmap_map __P((vaddr_t, paddr_t, paddr_t, int));
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void pmap_procwr __P((struct proc *, vaddr_t, size_t));
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#define PMAP_NEED_PROCWR
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/*
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* Do idle page zero'ing uncached to avoid polluting the cache.
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*/
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void pmap_zero_page_uncached __P((paddr_t));
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#define PMAP_PAGEIDLEZERO(pa) pmap_zero_page_uncached((pa))
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#endif /* !_X68K_PMAP_H_ */
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.11 1999/10/26 00:20:40 itohy Exp $
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# $NetBSD: genassym.cf,v 1.12 2000/05/14 14:10:10 minoura Exp $
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#
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# Copyright (c) 1982, 1990, 1993
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@ -48,6 +48,7 @@ include <sys/user.h>
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include <vm/vm.h>
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include <uvm/uvm.h>
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include <uvm/uvm_extern.h>
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ifdef COMPAT_SVR4
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@ -206,6 +207,9 @@ define SYS_compat_13_sigreturn13 SYS_compat_13_sigreturn13
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define EFAULT EFAULT
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define ENAMETOOLONG ENAMETOOLONG
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# UVM
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define UVM_PAGE_IDLE_ZERO offsetof(struct uvm, page_idle_zero)
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# SVR4 binary compatibility
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ifdef COMPAT_SVR4
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define SVR4_SIGF_HANDLER offsetof(struct svr4_sigframe, sf_handler)
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.52 2000/01/14 08:21:22 itohy Exp $ */
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/* $NetBSD: locore.s,v 1.53 2000/05/14 14:10:10 minoura Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -1066,10 +1066,16 @@ ENTRY(switch_exit)
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*/
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ASENTRY_NOPROFILE(Idle)
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stop #PSL_LOWIPL
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movw #PSL_HIGHIPL,sr
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movl _C_LABEL(whichqs),d0
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movw #PSL_HIGHIPL,%sr
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movl _C_LABEL(whichqs),%d0
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jne Lsw1
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movw #PSL_LOWIPL,%sr
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/* Try to zero some pages. */
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movl _C_LABEL(uvm)+UVM_PAGE_IDLE_ZERO,%d0
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jeq _ASM_LABEL(Idle)
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jra Lsw1
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jbsr _C_LABEL(uvm_pageidlezero)
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jra _ASM_LABEL(Idle)
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Lbadsw:
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PANIC("switch")
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@ -1302,241 +1308,6 @@ Lsldone:
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rts
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#endif
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#if 0
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/*
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* Invalidate entire TLB.
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*/
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ENTRY(TBIA)
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_C_LABEL(_TBIA):
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
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jne Lmotommu3 | no, skip
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.word 0xf518 | yes, pflusha
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#ifdef M68060
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cmpl #CPU_68060,_C_LABEL(cputype)
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jne Ltbiano60
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movc cacr,d0
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orl #IC60_CABC,d0 | clear all branch cache entries
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movc d0,cacr
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Ltbiano60:
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#endif
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rts
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Lmotommu3:
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#endif
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pflusha | flush entire TLB
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tstl _C_LABEL(mmutype)
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jpl Lmc68851a | 68851 implies no d-cache
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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Lmc68851a:
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rts
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/*
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* Invalidate any TLB entry for given VA (TB Invalidate Single)
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*/
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ENTRY(TBIS)
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#ifdef DEBUG
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tstl _ASM_LABEL(fulltflush) | being conservative?
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jne _C_LABEL(_TBIA) | yes, flush entire TLB
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#endif
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
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jne Lmotommu4 | no, skip
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movl sp@(4),a0
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movc dfc,d1
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moveq #FC_USERD,d0 | user space
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movc d0,dfc
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.word 0xf508 | pflush a0@
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moveq #FC_SUPERD,d0 | supervisor space
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movc d0,dfc
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.word 0xf508 | pflush a0@
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movc d1,dfc
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#ifdef M68060
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cmpl #CPU_68060,_C_LABEL(cputype)
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jne Ltbisno60
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movc cacr,d0
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orl #IC60_CABC,d0 | clear all branch cache entries
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movc d0,cacr
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Ltbisno60:
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#endif
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rts
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Lmotommu4:
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#endif
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movl sp@(4),a0 | get addr to flush
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tstl _C_LABEL(mmutype)
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jpl Lmc68851b | is 68851?
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pflush #0,#0,a0@ | flush address from both sides
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip data cache
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rts
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Lmc68851b:
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pflushs #0,#0,a0@ | flush address from both sides
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rts
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/*
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* Invalidate supervisor side of TLB
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*/
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ENTRY(TBIAS)
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#ifdef DEBUG
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tstl _ASM_LABEL(fulltflush) | being conservative?
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jne _C_LABEL(_TBIA) | yes, flush everything
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#endif
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
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jne Lmotommu5 | no, skip
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.word 0xf518 | yes, pflusha (for now) XXX
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#ifdef M68060
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cmpl #CPU_68060,_C_LABEL(cputype)
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jne Ltbiasno60
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movc cacr,d0
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orl #IC60_CABC,d0 | clear all branch cache entries
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movc d0,cacr
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Ltbiasno60:
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#endif
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rts
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Lmotommu5:
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#endif
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tstl _C_LABEL(mmutype)
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jpl Lmc68851c | 68851?
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pflush #4,#4 | flush supervisor TLB entries
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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Lmc68851c:
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pflushs #4,#4 | flush supervisor TLB entries
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rts
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/*
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* Invalidate user side of TLB
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*/
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ENTRY(TBIAU)
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#ifdef DEBUG
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tstl _ASM_LABEL(fulltflush) | being conservative?
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jne _C_LABEL(_TBIA) | yes, flush everything
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#endif
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040?
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jne Lmotommu6 | no, skip
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.word 0xf518 | yes, pflusha (for now) XXX
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#ifdef M68060
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cmpl #CPU_68060,_C_LABEL(cputype)
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jne Ltbiauno60
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movc cacr,d0
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orl #IC60_CUBC,d0 | clear user branch cache entries
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movc d0,cacr
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Ltbiauno60:
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#endif
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rts
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Lmotommu6:
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#endif
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tstl _C_LABEL(mmutype)
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jpl Lmc68851d | 68851?
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pflush #0,#4 | flush user TLB entries
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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Lmc68851d:
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pflushs #0,#4 | flush user TLB entries
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rts
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/*
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* Invalidate instruction cache
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*/
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ENTRY(ICIA)
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#if defined(M68040) || defined(M68060)
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ENTRY(ICPA)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
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jne Lmotommu7 | no, skip
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.word 0xf498 | cinva ic
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rts
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Lmotommu7:
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#endif
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movl #IC_CLEAR,d0
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movc d0,cacr | invalidate i-cache
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rts
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/*
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* Invalidate data cache.
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* HP external cache allows for invalidation of user/supervisor portions.
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* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
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* problems with DC_WA. The only cases we have to worry about are context
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* switch and TLB changes, both of which are handled "in-line" in resume
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* and TBI*.
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*/
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ENTRY(DCIA)
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_C_LABEL(_DCIA):
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
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jne Lmotommu8 | no, skip
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/* XXX implement */
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Lmotommu8:
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#endif
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rts
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ENTRY(DCIS)
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_C_LABEL(_DCIS):
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
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jne Lmotommu9 | no, skip
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/* XXX implement */
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Lmotommu9:
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#endif
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rts
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ENTRY(DCIU)
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_C_LABEL(_DCIU):
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
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jne LmotommuA | no, skip
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/* XXX implement */
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LmotommuA:
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#endif
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rts
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#if defined(M68040) || defined(M68060)
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ENTRY(ICPL)
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movl sp@(4),a0 | address
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.word 0xf488 | cinvl ic,a0@
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rts
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ENTRY(ICPP)
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movl sp@(4),a0 | address
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.word 0xf490 | cinvp ic,a0@
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rts
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ENTRY(DCPL)
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movl sp@(4),a0 | address
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.word 0xf448 | cinvl dc,a0@
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rts
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ENTRY(DCPP)
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movl sp@(4),a0 | address
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.word 0xf450 | cinvp dc,a0@
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rts
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ENTRY(DCPA)
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.word 0xf458 | cinva dc
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rts
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ENTRY(DCFL)
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movl sp@(4),a0 | address
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.word 0xf468 | cpushl dc,a0@
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rts
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ENTRY(DCFP)
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movl sp@(4),a0 | address
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.word 0xf470 | cpushp dc,a0@
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rts
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#endif
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ENTRY(PCIA)
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#if defined(M68040) || defined(M68060)
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ENTRY(DCFA)
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cmpl #MMU_68040,_C_LABEL(mmutype) | 68040
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jne LmotommuB | no, skip
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.word 0xf478 | cpusha dc
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rts
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LmotommuB:
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#endif
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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#endif
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ENTRY(ecacheon)
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rts
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.49 2000/04/18 21:06:12 minoura Exp $ */
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/* $NetBSD: pmap.c,v 1.50 2000/05/14 14:10:11 minoura Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -1973,6 +1973,43 @@ pmap_zero_page(phys)
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splx(s);
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}
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/*
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* pmap_zero_page_uncached:
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*
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* Same as above, except uncached. Used in uvm_pageidlezero,
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* through PMAP_PAGEIDLEZERO macro.
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*/
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void
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pmap_zero_page_uncached(phys)
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paddr_t phys;
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{
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int s, npte;
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PMAP_DPRINTF(PDB_FOLLOW, ("pmap_zero_page_uncached(%lx)\n", phys));
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#if defined(M68040) || defined(M68060)
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if (mmutype == MMU_68040) {
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DCPP(phys);
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}
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#endif
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npte = phys | PG_V | PG_CI;
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s = splimp();
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*caddr1_pte = npte;
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TBIS((vaddr_t)CADDR1);
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zeropage(CADDR1);
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#ifdef DEBUG
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*caddr1_pte = PG_NV;
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TBIS((vaddr_t)CADDR1);
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#endif
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splx(s);
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}
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/*
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* pmap_copy_page: [ INTERFACE ]
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*
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