Pull up the following revisions, requested by msaitoh in #1656:

sys/dev/pci/if_wm.c				1.768-1.782 via patch
	sys/dev/pci/if_wmreg.h				1.129-1.130
	sys/dev/pci/if_wmvar.h				1.49

wm(4):
- Rework for event counters:
  - Fix calculation of GORC, GOTC, TOR and TOT counters correctly.
  - Rearrange the order of the registers so that they are roughly
    in ascending order.
  - Reorder evcnt_attach_dynamic(), WM_EVCNT_ADD() and evcnt_detach()
    to match.
  - IC{TX,RX}*C registers are for older than 82575.
  - Fix a bug that the transmit underrun counter is incorrectly
    counted.
  - Don't add "Count" for event counter's description.
  - Some statistics registers were replaced with new counters on newer
    chips. Treat 0x403c(CEXTERR->HTDPMC), 0x40fc(TSCTFC->CBRMPC),
    0x4124(ICRXOC->HTCBDPC) and from 0x4104 to 0x4124.
  - Add some new counters:
    - Circuit Breaker TX Manageability Packet
    - Circuit Breaker RX Dropped Packet
    - Host Good Octets RX
    - Host Good Octets TX
    - Length Errors
    - SerDes/SGMII Code Violation Packet
    - Header Redirection Missed Packet
    - EEE TX LPI
    - EEE RX LPI
  - Fix prc511's comment and description.
- Add SOICZIFDATA (ifconfig -z) support for evcnt(9).
- Use WM_IS_ICHPCH(). No functional change.
- Fix typo. s/ictxact/ictxatc/. No functional change.
- Add comment.

sys/dev/pci/if_wmreg.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: if_wmreg.h,v 1.115.2.7 2023/01/23 13:59:04 martin Exp $	*/
+/*	$NetBSD: if_wmreg.h,v 1.115.2.8 2023/06/27 18:32:46 martin Exp $	*/
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -1152,11 +1152,18 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_MCC	0x401c	/* Multiple Collision Count - R/clr */
 #define	WMREG_LATECOL	0x4020	/* Late Collisions Count - R/clr */
 #define	WMREG_COLC	0x4028	/* Collision Count - R/clr */
+#define	WMREG_CBTMPC	0x402c	/* Circuit Breaker Tx Manageability Packet */
 #define	WMREG_DC	0x4030	/* Defer Count - R/clr */
 #define	WMREG_TNCRS	0x4034	/* Tx with No CRS - R/clr */
 #define	WMREG_SEC	0x4038	/* Sequence Error Count */
+
+/* Old */
 #define	WMREG_CEXTERR	0x403c	/* Carrier Extension Error Count */
+/* New */
+#define	WMREG_HTDPMC	0x403c	/* Host Tx Discarded Packets by MAC Count */
+
 #define	WMREG_RLEC	0x4040	/* Receive Length Error Count */
+#define	WMREG_CBRDPC	0x4044	/* Circuit Breaker Rx Dropped Packet Count */
 #define	WMREG_XONRXC	0x4048	/* XON Rx Count - R/clr */
 #define	WMREG_XONTXC	0x404c	/* XON Tx Count - R/clr */
 #define	WMREG_XOFFRXC	0x4050	/* XOFF Rx Count - R/clr */
@@ -1199,8 +1206,15 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_MPTC	0x40f0	/* Multicast Packets Tx Count - R/clr */
 #define	WMREG_BPTC	0x40f4	/* Broadcast Packets Tx Count */
 #define	WMREG_TSCTC	0x40f8	/* TCP Segmentation Context Tx */
+
+/* Old */
 #define	WMREG_TSCTFC	0x40fc	/* TCP Segmentation Context Tx Fail */
+/* New */
+#define	WMREG_CBRMPC	0x40fc	/* Circuit Breaker Rx Manageability Packet */
+
 #define	WMREG_IAC	0x4100	/* Interrupt Assertion Count */
+
+/* Old */
 #define	WMREG_ICRXPTC	0x4104	/* Interrupt Cause Rx Pkt Timer Expire Count */
 #define	WMREG_ICRXATC	0x4108	/* Interrupt Cause Rx Abs Timer Expire Count */
 #define	WMREG_ICTXPTC	0x410c	/* Interrupt Cause Tx Pkt Timer Expire Count */
@@ -1209,6 +1223,21 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_ICTXQMTC	0x411c	/* Interrupt Cause Tx Queue Min Thresh Count */
 #define	WMREG_ICRXDMTC	0x4120	/* Interrupt Cause Rx Desc Min Thresh Count */
 #define	WMREG_ICRXOC	0x4124	/* Interrupt Cause Receiver Overrun Count */
+/* New */
+#define	WMREG_RPTHC	0x4104	/* Rx Pkt To Host Count */
+#define	WMREG_DEBUG1	0x4108	/* Debug Counter 1 */
+#define	WMREG_DEBUG2	0x410c	/* Debug Counter 2 */
+#define	WMREG_DEBUG3	0x4110	/* Debug Counter 3 */
+#define	WMREG_HGPTC	0x4118	/* Host Good Packets Tx Count (>=82576?) */
+#define	WMREG_DEBUG4	0x411c	/* Debug Counter 4 */
+#define	WMREG_RXDMTC	0x4120	/* Rx Desc Min Thresh Count */
+#define	WMREG_HTCBDPC	0x4124	/* Host Tx Circuit Breaker Dropped Pkt. Cnt. */
+#define	WMREG_HGORCL	0x4128	/* Host Good Octets Rx Count Low (>=82576?) */
+#define	WMREG_HGORCH	0x412c	/* Host Good Octets Rx Count High (>=82576?) */
+#define	WMREG_HGOTCL	0x4130	/* Host Good Octets Tx Count Low (>=82576?) */
+#define	WMREG_HGOTCH	0x4134	/* Host Good Octets Tx Count High (>=82576?) */
+#define	WMREG_LENERRS	0x4138	/* Length Errors Count (>=82576?) */
+
 #define	WMREG_TLPIC	0x4148	/* EEE Tx LPI Count */
 #define	WMREG_RLPIC	0x414c	/* EEE Rx LPI Count */
 #define	WMREG_B2OGPRC	0x4158	/* BMC2OS packets received by host */
@@ -1248,6 +1277,7 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_PCS_ANADV	0x4218	/* AN Advertsement */
 #define	WMREG_PCS_LPAB	0x421c	/* Link Partnet Ability */
 #define	WMREG_PCS_NPTX	0x4220	/* Next Page Transmit */
+#define	WMREG_SCVPC	0x4228	/* SerDes/SGMII Code Violation Packet Count */
 
 #define	WMREG_RXCSUM	0x5000	/* Receive Checksum register */
 #define	RXCSUM_PCSS	0x000000ff	/* Packet Checksum Start */
@@ -1445,6 +1475,8 @@ struct livengood_tcpip_ctxdesc {
 #define	WMREG_B2OSPC	0x8fe0	/* BMC2OS packets sent by BMC */
 #define	WMREG_O2BGPTC	0x8fe4	/* OS2BMC packets received by BMC */
 
+#define	WMREG_HRMPC	0xa018	/* Header Redirection Missed Packet Count */
+
 #define	WMREG_EEC	0x12010
 #define	EEC_FLASH_DETECTED __BIT(19)	/* FLASH */
 #define	EEC_FLUPD	__BIT(23)	/* Update FLASH */

sys/dev/pci/if_wmvar.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: if_wmvar.h,v 1.44.4.4 2022/07/11 14:10:18 martin Exp $	*/
+/*	$NetBSD: if_wmvar.h,v 1.44.4.5 2023/06/27 18:32:46 martin Exp $	*/
 
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -213,4 +213,7 @@ typedef enum {
 #define	WM_MDIO_OWNERSHIP_TIMEOUT 10
 #define	WM_MAX_PLL_TRIES	5
 
+/* For 80003, ICHs and PCHs */
+#define	WM_IS_ICHPCH(x)	((x)->sc_type >= WM_T_80003)
+
 #endif /* _DEV_PCI_IF_WMVAR_H_ */