Support Cache Protocol 'MEI' with MULTIPROCESSOR.
This commit is contained in:
kiyohara
parent
62d7fcf09f
commit
515e584834
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@ -1,9 +1,10 @@
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# $NetBSD: files.powerpc,v 1.84 2012/10/02 23:51:39 christos Exp $
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# $NetBSD: files.powerpc,v 1.85 2012/10/20 14:42:15 kiyohara Exp $
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defflag opt_altivec.h ALTIVEC K_ALTIVEC PPC_HAVE_SPE
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defflag opt_openpic.h OPENPIC OPENPIC_SERIAL_MODE OPENPIC_DISTRIBUTE
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defparam opt_ppcparam.h L2CR_CONFIG L3CR_CONFIG INTSTK CLOCKBASE VERBOSE_INITPPC
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defflag opt_ppcarch.h PPC_OEA PPC_OEA601 PPC_OEA64 PPC_OEA64_BRIDGE PPC_MPC8XX PPC_IBM4XX PPC_IBM403 PPC_BOOKE
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defflag opt_ppccache.h CACHE_PROTO_MEI
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defflag opt_pmap.h PMAPDEBUG PMAPCHECK PMAPCOUNTERS PMAP_MINIMALTLB
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defparam opt_pmap.h PTEGCOUNT PMAP_MEMLIMIT
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.93 2012/07/28 23:11:00 matt Exp $ */
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/* $NetBSD: cpu.h,v 1.94 2012/10/20 14:42:15 kiyohara Exp $ */
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/*
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* Copyright (C) 1999 Wolfgang Solfrank.
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@ -165,7 +165,8 @@ struct cpu_hatch_data {
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uintptr_t hatch_asr;
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uintptr_t hatch_sdr1;
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uint32_t hatch_sr[16];
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uintptr_t hatch_batu[8], hatch_batl[8];
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uintptr_t hatch_ibatu[8], hatch_ibatl[8];
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uintptr_t hatch_dbatu[8], hatch_dbatl[8];
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#endif
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#if defined(PPC_BOOKE)
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vaddr_t hatch_sp;
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu_subr.c,v 1.75 2012/10/20 13:18:45 kiyohara Exp $ */
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/* $NetBSD: cpu_subr.c,v 1.76 2012/10/20 14:42:15 kiyohara Exp $ */
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/*-
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* Copyright (c) 2001 Matt Thomas.
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@ -34,9 +34,10 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.75 2012/10/20 13:18:45 kiyohara Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.76 2012/10/20 14:42:15 kiyohara Exp $");
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#include "opt_ppcparam.h"
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#include "opt_ppccache.h"
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#include "opt_multiprocessor.h"
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#include "opt_altivec.h"
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#include "sysmon_envsys.h"
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@ -581,6 +582,13 @@ cpu_setup(device_t self, struct cpu_info *ci)
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break;
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}
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#ifdef MULTIPROCESSOR
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switch (vers) {
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case MPC603e:
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hid0 |= HID0_ABE;
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}
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#endif
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if (hid0 != hid0_save) {
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mtspr(SPR_HID0, hid0);
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__asm volatile("sync;isync");
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@ -1189,7 +1197,7 @@ cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
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#endif /* NSYSMON_ENVSYS > 0 */
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#ifdef MULTIPROCESSOR
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extern volatile u_int cpu_spinstart_ack;
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volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum;
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int
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cpu_spinup(device_t self, struct cpu_info *ci)
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@ -1243,14 +1251,22 @@ cpu_spinup(device_t self, struct cpu_info *ci)
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h->hatch_asr = 0;
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/* copy the bat regs */
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__asm volatile ("mfibatu %0,0" : "=r"(h->hatch_batu[0]));
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__asm volatile ("mfibatl %0,0" : "=r"(h->hatch_batl[0]));
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__asm volatile ("mfibatu %0,1" : "=r"(h->hatch_batu[1]));
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__asm volatile ("mfibatl %0,1" : "=r"(h->hatch_batl[1]));
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__asm volatile ("mfibatu %0,2" : "=r"(h->hatch_batu[2]));
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__asm volatile ("mfibatl %0,2" : "=r"(h->hatch_batl[2]));
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__asm volatile ("mfibatu %0,3" : "=r"(h->hatch_batu[3]));
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__asm volatile ("mfibatl %0,3" : "=r"(h->hatch_batl[3]));
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__asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0]));
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__asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0]));
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__asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1]));
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__asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1]));
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__asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2]));
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__asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2]));
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__asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3]));
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__asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3]));
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__asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0]));
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__asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0]));
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__asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1]));
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__asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1]));
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__asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2]));
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__asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2]));
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__asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3]));
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__asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3]));
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__asm volatile ("sync; isync");
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if (md_setup_trampoline(h, ci) == -1)
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@ -1262,7 +1278,19 @@ cpu_spinup(device_t self, struct cpu_info *ci)
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delay(200000);
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#ifdef CACHE_PROTO_MEI
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__asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory");
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__asm volatile ("sync; isync");
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__asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory");
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__asm volatile ("sync; isync");
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#endif
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if (h->hatch_running < 1) {
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#ifdef CACHE_PROTO_MEI
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__asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory");
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__asm volatile ("sync; isync");
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__asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory");
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__asm volatile ("sync; isync");
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#endif
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aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack,
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ci->ci_cpuid, cpu_spinstart_ack);
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Debugger();
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@ -1305,14 +1333,22 @@ cpu_hatch(void)
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cpu_spinstart_ack = 0;
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/* Initialize MMU. */
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__asm ("mtibatu 0,%0" :: "r"(h->hatch_batu[0]));
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__asm ("mtibatl 0,%0" :: "r"(h->hatch_batl[0]));
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__asm ("mtibatu 1,%0" :: "r"(h->hatch_batu[1]));
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__asm ("mtibatl 1,%0" :: "r"(h->hatch_batl[1]));
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__asm ("mtibatu 2,%0" :: "r"(h->hatch_batu[2]));
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__asm ("mtibatl 2,%0" :: "r"(h->hatch_batl[2]));
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__asm ("mtibatu 3,%0" :: "r"(h->hatch_batu[3]));
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__asm ("mtibatl 3,%0" :: "r"(h->hatch_batl[3]));
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__asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0]));
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__asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0]));
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__asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1]));
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__asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1]));
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__asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2]));
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__asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2]));
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__asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3]));
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__asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3]));
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__asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0]));
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__asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0]));
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__asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1]));
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__asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1]));
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__asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2]));
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__asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2]));
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__asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3]));
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__asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3]));
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mtspr(SPR_HID0, h->hatch_hid0);
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@ -1,4 +1,4 @@
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/* $NetBSD: ofwoea_machdep.c,v 1.30 2012/07/17 03:13:31 jmmv Exp $ */
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/* $NetBSD: ofwoea_machdep.c,v 1.31 2012/10/20 14:42:15 kiyohara Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ofwoea_machdep.c,v 1.30 2012/07/17 03:13:31 jmmv Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ofwoea_machdep.c,v 1.31 2012/10/20 14:42:15 kiyohara Exp $");
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#include "opt_ppcarch.h"
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#include "opt_compat_netbsd.h"
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static void set_timebase(void);
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extern void cpu_spinstart(u_int);
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volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum;
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extern volatile u_int cpu_spinstart_ack;
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void
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ofwoea_initppc(u_int startkernel, u_int endkernel, char *args)
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/* $NetBSD: pmap.c,v 1.86 2012/07/28 23:11:00 matt Exp $ */
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/* $NetBSD: pmap.c,v 1.87 2012/10/20 14:42:15 kiyohara Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -63,7 +63,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.86 2012/07/28 23:11:00 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.87 2012/10/20 14:42:15 kiyohara Exp $");
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#define PMAP_NOOPNAMES
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@ -490,7 +490,11 @@ extern struct evcnt pmap_evcnt_idlezeroed_pages;
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/* XXXSL: this needs to be moved to assembler */
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#define TLBIEL(va) __asm __volatile("tlbie %0" :: "r"(va))
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#ifdef MD_TLBSYNC
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#define TLBSYNC() MD_TLBSYNC()
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#else
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#define TLBSYNC() __asm volatile("tlbsync")
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#endif
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#define SYNC() __asm volatile("sync")
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#define EIEIO() __asm volatile("eieio")
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#define DCBST(va) __asm __volatile("dcbst 0,%0" :: "r"(va))
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@ -1939,6 +1943,10 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
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break;
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}
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}
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#ifdef MULTIPROCESSOR
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if (((mfpvr() >> 16) & 0xffff) == MPC603e)
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pte_lo = PTE_M;
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#endif
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} else {
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pte_lo |= PTE_I;
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}
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break;
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}
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}
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#ifdef MULTIPROCESSOR
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if (((mfpvr() >> 16) & 0xffff) == MPC603e)
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pte_lo = PTE_M;
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#endif
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}
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if (prot & VM_PROT_WRITE)
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@ -1,4 +1,4 @@
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/* $NetBSD: vm_machdep.c,v 1.97 2012/06/28 15:28:44 matt Exp $ */
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/* $NetBSD: vm_machdep.c,v 1.98 2012/10/20 14:42:15 kiyohara Exp $ */
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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@ -32,11 +32,12 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.97 2012/06/28 15:28:44 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.98 2012/10/20 14:42:15 kiyohara Exp $");
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#include "opt_altivec.h"
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#include "opt_multiprocessor.h"
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#include "opt_ppcarch.h"
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#include "opt_ppccache.h"
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#include <sys/param.h>
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#include <sys/core.h>
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#ifdef PPC_HAVE_FPU
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pcb2->pcb_flags = PSL_FE_DFLT;
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#endif
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#ifdef CACHE_PROTO_MEI
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{
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paddr_t pa;
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int dcache_line_size, i;
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/* Flush on cache values for other cpu. */
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dcache_line_size = curcpu()->ci_ci.dcache_line_size;
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pa = vtophys((vaddr_t)sf);
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for (i = 0; i < SFRAMELEN + CALLFRAMELEN + FRAMELEN;
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i += dcache_line_size) {
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__asm volatile ("dcbf 0,%0"::"r"(pa):"memory");
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pa += dcache_line_size;
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}
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__asm volatile ("dcbf 0,%0"::"r"(pa):"memory");
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pa = vtophys((vaddr_t)pcb2->pcb_pm);
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for (i = 0; i < sizeof(*pcb2->pcb_pm); i += dcache_line_size) {
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__asm volatile ("dcbf 0,%0"::"r"(pa):"memory");
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pa += dcache_line_size;
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}
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__asm volatile ("dcbf 0,%0"::"r"(pa):"memory");
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pa = vtophys((vaddr_t)pcb2);
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for (i = 0; i < sizeof(*pcb2); i += dcache_line_size) {
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__asm volatile ("dcbf 0,%0"::"r"(pa):"memory");
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pa += dcache_line_size;
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}
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__asm volatile ("dcbf 0,%0"::"r"(pa):"memory");
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/* Need more flush? */
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}
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#endif
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}
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void
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