HME ethernet driver.
Note: this is work in progress; needs testing and tweaking. mgr has promised to do that..
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/* $NetBSD: hmereg.h,v 1.1 1999/06/27 12:26:32 pk Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* HME Shared Ethernet Block register offsets
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*/
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#define HME_SEBI_RESET (0*4)
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#define HME_SEBI_CFG (1*4)
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#define HME_SEBI_STAT (64*4)
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#define HME_SEBI_IMASK (65*4)
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/* HME SEB bits. */
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#define HME_SEB_RESET_ETX 0x00000001 /* reset external transmitter */
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#define HME_SEB_RESET_ERX 0x00000002 /* reset external receiver */
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#define HME_SEB_CFG_BURSTMASK 0x00000003 /* covers all burst bits */
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#define HME_SEB_CFG_BURST16 0x00000000 /* 16 byte bursts */
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#define HME_SEB_CFG_BURST32 0x00000001 /* 32 byte bursts */
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#define HME_SEB_CFG_BURST64 0x00000002 /* 64 byte bursts */
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#define HME_SEB_CFG_64BIT 0x00000004 /* ? */
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#define HME_SEB_CFG_PARITY 0x00000008 /* ? */
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#define HME_SEB_STAT_GOTFRAME 0x00000001 /* frame received */
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#define HME_SEB_STAT_RCNTEXP 0x00000002 /* rx frame count expired */
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#define HME_SEB_STAT_ACNTEXP 0x00000004 /* align error count expired */
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#define HME_SEB_STAT_CCNTEXP 0x00000008 /* crc error count expired */
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#define HME_SEB_STAT_LCNTEXP 0x00000010 /* length error count expired */
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#define HME_SEB_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */
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#define HME_SEB_STAT_CVCNTEXP 0x00000040 /* code violation counter exp */
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#define HME_SEB_STAT_STSTERR 0x00000080 /* xif sqe test failed */
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#define HME_SEB_STAT_SENTFRAME 0x00000100 /* frame sent */
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#define HME_SEB_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */
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#define HME_SEB_STAT_MAXPKTERR 0x00000400 /* max-packet size error */
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#define HME_SEB_STAT_NCNTEXP 0x00000800 /* normal collision count exp */
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#define HME_SEB_STAT_ECNTEXP 0x00001000 /* excess collision count exp */
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#define HME_SEB_STAT_LCCNTEXP 0x00002000 /* late collision count exp */
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#define HME_SEB_STAT_FCNTEXP 0x00004000 /* first collision count exp */
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#define HME_SEB_STAT_DTIMEXP 0x00008000 /* defer timer expired */
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#define HME_SEB_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */
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#define HME_SEB_STAT_NORXD 0x00020000 /* out of receive descriptors */
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#define HME_SEB_STAT_RXERR 0x00040000 /* rx dma error */
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#define HME_SEB_STAT_RXLATERR 0x00080000 /* late error during rx dma */
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#define HME_SEB_STAT_RXPERR 0x00100000 /* parity error during rx dma */
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#define HME_SEB_STAT_RXTERR 0x00200000 /* tag error during rx dma */
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#define HME_SEB_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */
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#define HME_SEB_STAT_MIFIRQ 0x00800000 /* mif needs attention */
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#define HME_SEB_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */
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#define HME_SEB_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */
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#define HME_SEB_STAT_TXEACK 0x04000000 /* error during tx dma */
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#define HME_SEB_STAT_TXLERR 0x08000000 /* late error during tx dma */
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#define HME_SEB_STAT_TXPERR 0x10000000 /* parity error during tx dma */
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#define HME_SEB_STAT_TXTERR 0x20000000 /* tag error durig tx dma */
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#define HME_SEB_STAT_SLVERR 0x40000000 /* pio access error */
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#define HME_SEB_STAT_SLVPERR 0x80000000 /* pio access parity error */
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#define HME_SEB_STAT_BITS "\177\020" \
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"b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \
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"b\3CCNTEXP\0b\5LCNTEXP\0b\6RFIFOVF\0" \
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"b\7CVCNTEXP\0b\10SENTFRAME\0b\11TFIFO_UND\0" \
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"b\12MAXPKTERR\0b\13NCNTEXP\0b\14ECNTEXP\0" \
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"b\15LCCNTEXP\0b\16FCNTEXP\0b\17DTIMEXP\0" \
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"b\20RXTOHOST\0b\21NORXD\0b\22RXERR\0" \
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"b\23RXLATERR\0b\24RXPERR\0b\25RXTERR\0" \
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"b\26EOPERR\0b\27MIFIRQ\0b\30HOSTTOTX\0" \
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"b\31TXALL\0b\32XTEACK\0b\33TXLERR\0" \
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"b\34TXPERR\0b\35TXTERR\0b\36SLVERR\0" \
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"b\37SLVPERR\0\0"
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#define HME_SEB_STAT_ALL_ERRORS \
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(HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\
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HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\
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HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\
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HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\
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HME_SEB_STAT_DTIMEXP | HME_SEB_STAT_FCNTEXP | HME_SEB_STAT_LCCNTEXP |\
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HME_SEB_STAT_ECNTEXP | HME_SEB_STAT_NCNTEXP | HME_SEB_STAT_MAXPKTERR|\
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HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_CVCNTEXP |\
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HME_SEB_STAT_RFIFOVF | HME_SEB_STAT_LCNTEXP | HME_SEB_STAT_CCNTEXP |\
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HME_SEB_STAT_ACNTEXP)
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/*
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* HME Transmitter register offsets
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*/
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#define HME_ETXI_PENDING (0*4) /* Pending/wakeup */
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#define HME_ETXI_CFG (1*4)
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#define HME_ETXI_RING (2*4) /* Descriptor Ring pointer */
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#define HME_ETXI_BBASE (3*4) /* Buffer base address (ro) */
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#define HME_ETXI_BDISP (4*4) /* Buffer displacement (ro) */
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#define HME_ETXI_FIFO_WPTR (5*4) /* FIFO write pointer */
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#define HME_ETXI_FIFO_SWPTR (6*4) /* FIFO shadow write pointer */
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#define HME_ETXI_FIFO_RPTR (7*4) /* FIFO read pointer */
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#define HME_ETXI_FIFO_SRPTR (8*4) /* FIFO shadow read pointer */
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#define HME_ETXI_FIFO_SMACH (9*4) /* State machine */
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#define HME_ETXI_RSIZE (10*4) /* Ring size */
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#define HME_ETXI_BPTR (11*4) /* Buffer pointer */
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/* TXI_PENDING bits */
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#define HME_ETX_TP_DMAWAKEUP 0x00000001 /* Start tx (rw, auto-clear) */
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/* TXI_CFG bits */
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#define HME_ETX_CFG_DMAENABLE 0x00000001 /* Enable TX dma */
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#define HME_ETX_CFG_FIFOTHRESH 0x000003fe /* TX fifo threshold */
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#define HME_ETX_CFG_IRQDAFTER 0x00000400 /* Intr after tx-fifo empty */
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#define HME_ETX_CFG_IRQDBEFORE 0x00000000 /* Intr before tx-fifo empty */
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/*
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* HME Receiver register offsets
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*/
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#define HME_ERXI_CFG (0*4)
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#define HME_ERXI_RING (1*4) /* Descriptor Ring pointer */
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#define HME_ERXI_BPTR (2*4) /* Data Buffer pointer (ro) */
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#define HME_ERXI_FIFO_WPTR (3*4) /* FIFO write pointer */
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#define HME_ERXI_FIFO_SWPTR (4*4) /* FIFO shadow write pointer */
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#define HME_ERXI_FIFO_RPTR (5*4) /* FIFO read pointer */
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#define HME_ERXI_FIFO_SRPTR (6*4) /* FIFO shadow read pointer */
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#define HME_ERXI_FIFO_SMACH (7*4) /* State machine */
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/* RXI_CFG bits */
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#define HME_ERX_CFG_DMAENABLE 0x00000001 /* Enable RX dma */
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#define HME_ERX_CFG_BYTEOFFSET 0x00000038 /* RX first byte offset */
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#define HME_ERX_CFG_RINGSIZE32 0x00000000 /* Descriptor ring size: 32 */
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#define HME_ERX_CFG_RINGSIZE64 0x00000200 /* Descriptor ring size: 64 */
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#define HME_ERX_CFG_RINGSIZE128 0x00000400 /* Descriptor ring size: 128 */
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#define HME_ERX_CFG_RINGSIZE256 0x00000600 /* Descriptor ring size: 256 */
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#define HME_ERX_CFG_CSUMSTART 0x007f0000 /* cksum offset */
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/*
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* HME MAC-core register offsets
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*/
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#define HME_MACI_XIF (0*4)
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#define HME_MACI_TXSWRST (130*4) /* TX reset */
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#define HME_MACI_TXCFG (131*4) /* TX config */
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#define HME_MACI_JSIZE (139*4) /* TX jam size */
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#define HME_MACI_NCCNT (144*4) /* TX normal collision cnt */
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#define HME_MACI_FCCNT (145*4) /* TX first collision cnt */
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#define HME_MACI_EXCNT (146*4) /* TX excess collision cnt */
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#define HME_MACI_LTCNT (147*4) /* TX late collision cnt */
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#define HME_MACI_RANDSEED (148*4) /* */
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#define HME_MACI_RXSWRST (194*4) /* RX reset */
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#define HME_MACI_RXCFG (195*4) /* RX config */
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#define HME_MACI_MACADDR2 (198*4) /* MAC address */
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#define HME_MACI_MACADDR1 (199*4)
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#define HME_MACI_MACADDR0 (200*4)
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#define HME_MACI_HASHTAB3 (208*4) /* Address hash table */
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#define HME_MACI_HASHTAB2 (209*4)
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#define HME_MACI_HASHTAB1 (210*4)
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#define HME_MACI_HASHTAB0 (211*4)
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#define HME_MACI_AFILTER2 (212*4) /* Address filter */
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#define HME_MACI_AFILTER1 (213*4)
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#define HME_MACI_AFILTER0 (214*4)
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#define HME_MACI_AFILTER_MASK (215*4)
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/* XIF config register. */
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#define HME_MAC_XIF_OE 0x00000001 /* Output driver enable */
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#define HME_MAC_XIF_XLBACK 0x00000002 /* Loopback-mode XIF enable */
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#define HME_MAC_XIF_MLBACK 0x00000004 /* Loopback-mode MII enable */
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#define HME_MAC_XIF_MIIDISAB 0x00000008 /* MII receive buffer disable */
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#define HME_MAC_XIF_SQENABLE 0x00000010 /* SQE test enable */
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#define HME_MAC_XIF_SQETWIN 0x000003e0 /* SQE time window */
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#define HME_MAC_XIF_LANCE 0x00000010 /* Lance mode enable */
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#define HME_MAC_XIF_LIPG0 0x000003e0 /* Lance mode IPG0 */
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/* Transmit config register. */
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#define HME_MAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
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#define HME_MAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
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#define HME_MAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
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#define HME_MAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
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#define HME_MAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
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#define HME_MAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
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#define HME_MAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
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/* Receive config register. */
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#define HME_MAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
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#define HME_MAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
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#define HME_MAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
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#define HME_MAC_RXCFG_DERR 0x00000080 /* Disable error checking */
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#define HME_MAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
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#define HME_MAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
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#define HME_MAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
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#define HME_MAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
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#define HME_MAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
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/*
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* HME MIF register offsets
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*/
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#define HME_MIFI_BB_CLK (0*4) /* bit-bang clock */
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#define HME_MIFI_BB_DATA (1*4) /* bit-bang data */
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#define HME_MIFI_BB_OE (2*4) /* bit-bang output enable */
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#define HME_MIFI_FO (3*4) /* frame output */
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#define HME_MIFI_CFG (4*4) /* */
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#define HME_MIFI_IMASK (5*4) /* Interrupt mask for status change */
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#define HME_MIFI_STAT (6*4) /* Status (ro, auto-clear) */
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#define HME_MIFI_SM (7*4) /* State machine (ro) */
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/* MIF Configuration register */
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#define HME_MIF_CFG_PHY 0x00000001 /* PHY select */
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#define HME_MIF_CFG_PE 0x00000002 /* Poll enable */
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#define HME_MIF_CFG_BBMODE 0x00000004 /* Bit-bang mode */
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#define HME_MIF_CFG_PRADDR 0x000000f8 /* Poll register adddress */
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#define HME_MIF_CFG_MDI0 0x00000100 /* MDI_0 (ro) */
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#define HME_MIF_CFG_MDI1 0x00000200 /* MDI_1 (ro) */
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#define HME_MIF_CFG_PPADDR 0x00007c00 /* Poll phy adddress */
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/* MIF Frame/Output register */
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#define HME_MIF_FO_ST 0xc0000000 /* Start of frame */
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#define HME_MIF_FO_ST_SHIFT 30 /* */
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#define HME_MIF_FO_OPC 0x30000000 /* Opcode */
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#define HME_MIF_FO_OPC_SHIFT 28 /* */
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#define HME_MIF_FO_PHYAD 0x0f800000 /* PHY Address */
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#define HME_MIF_FO_PHYAD_SHIFT 23 /* */
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#define HME_MIF_FO_REGAD 0x007c0000 /* Register Address */
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#define HME_MIF_FO_REGAD_SHIFT 18 /* */
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#define HME_MIF_FO_TAMSB 0x00020000 /* Turn-around MSB */
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#define HME_MIF_FO_TALSB 0x00010000 /* Turn-around LSB */
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#define HME_MIF_FO_DATA 0x0000ffff /* data to read or write */
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/*
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* Buffer Descriptors.
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*
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struct hme_xd {
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volatile u_int32_t xd_flags;
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volatile u_int32_t xd_addr; // Buffer address (DMA)
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}; */
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#define HME_XD_SIZE 8
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#define HME_XD_FLAGS(base, index) ((base) + ((index) * HME_XD_SIZE) + 0)
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#define HME_XD_ADDR(base, index) ((base) + ((index) * HME_XD_SIZE) + 4)
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#define HME_XD_GETFLAGS(b, i) \
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(*((u_int32_t *)HME_XD_FLAGS(b,i)))
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#define HME_XD_SETFLAGS(b, i, f) do { \
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*((u_int32_t *)HME_XD_FLAGS(b,i)) = (f); \
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} while(0)
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#define HME_XD_SETADDR(b, i, a) do { \
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*((u_int32_t *)HME_XD_ADDR(b,i)) = (a); \
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} while(0)
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/* Descriptor flag values */
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#define HME_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */
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#define HME_XD_SOP 0x40000000 /* start of packet marker (tx) */
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#define HME_XD_OFL 0x40000000 /* buffer overflow (rx) */
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#define HME_XD_EOP 0x20000000 /* end of packet marker (tx) */
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#define HME_XD_TXCKSUM 0x10000000 /* checksum enable (tx) */
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#define HME_XD_RXLENMSK 0x3fff0000 /* packet length mask (rx) */
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#define HME_XD_RXLENSHIFT 16
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#define HME_XD_TXLENMSK 0x00003fff /* packet length mask (tx) */
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#define HME_XD_RXCKSUM 0x0000ffff /* packet checksum (rx) */
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/* Macros to encode/decode the receive buffer size from the flags field */
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#define HME_XD_ENCODE_RSIZE(sz) \
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(((sz) << HME_XD_RXLENSHIFT) & HME_XD_RXLENMSK)
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#define HME_XD_DECODE_RSIZE(flags) \
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(((flags) & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT)
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/* Provide encode/decode macros for the transmit buffers for symmetry */
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#define HME_XD_ENCODE_TSIZE(sz) \
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(((sz) << 0) & HME_XD_TXLENMSK)
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#define HME_XD_DECODE_TSIZE(flags) \
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(((flags) & HME_XD_TXLENMSK) >> 0)
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@ -0,0 +1,106 @@
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/* $NetBSD: hmevar.h,v 1.1 1999/06/27 12:26:33 pk Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "rnd.h"
|
||||
|
||||
#if NRND > 0
|
||||
#include <sys/rnd.h>
|
||||
#endif
|
||||
|
||||
|
||||
struct hme_ring {
|
||||
/* Ring Descriptors */
|
||||
caddr_t rb_membase; /* Packet buffer: CPU address */
|
||||
bus_addr_t rb_dmabase; /* Packet buffer: DMA address */
|
||||
caddr_t rb_txd; /* Transmit descriptors */
|
||||
bus_addr_t rb_txddma; /* DMA address of same */
|
||||
caddr_t rb_rxd; /* Receive descriptors */
|
||||
bus_addr_t rb_rxddma; /* DMA address of same */
|
||||
caddr_t rb_txbuf; /* Transmit buffers */
|
||||
caddr_t rb_rxbuf; /* Receive buffers */
|
||||
int rb_ntbuf; /* # of transmit buffers */
|
||||
int rb_nrbuf; /* # of receive buffers */
|
||||
|
||||
/* Ring Descriptor state */
|
||||
int rb_tdhead, rb_tdtail;
|
||||
int rb_rdtail;
|
||||
int rb_td_nbusy;
|
||||
};
|
||||
|
||||
struct hme_softc {
|
||||
struct device sc_dev; /* boilerplate device view */
|
||||
struct ethercom sc_ethercom; /* Ethernet common part */
|
||||
struct mii_data sc_mii; /* MII media control */
|
||||
#define sc_media sc_mii.mii_media/* shorthand */
|
||||
|
||||
/* The following bus handles are to be provided by the bus front-end */
|
||||
bus_space_tag_t sc_bustag; /* bus tag */
|
||||
bus_dma_tag_t sc_dmatag; /* bus dma tag */
|
||||
bus_space_handle_t sc_seb; /* HME Global registers */
|
||||
bus_space_handle_t sc_erx; /* HME ERX registers */
|
||||
bus_space_handle_t sc_etx; /* HME ETX registers */
|
||||
bus_space_handle_t sc_mac; /* HME MAC registers */
|
||||
bus_space_handle_t sc_mif; /* HME MIF registers */
|
||||
int sc_burst; /* DVMA burst size in effect */
|
||||
|
||||
/* Ring descriptor */
|
||||
struct hme_ring sc_rb;
|
||||
#if notused
|
||||
void (*sc_copytobuf) __P((struct hme_softc *,
|
||||
void *, void *, size_t));
|
||||
void (*sc_copyfrombuf) __P((struct hme_softc *,
|
||||
void *, void *, size_t));
|
||||
#endif
|
||||
|
||||
int sc_debug;
|
||||
void *sc_sh; /* shutdownhook cookie */
|
||||
u_int8_t sc_enaddr[6]; /* MAC address */
|
||||
|
||||
/* Special hardware hooks */
|
||||
void (*sc_hwreset) __P((struct hme_softc *));
|
||||
void (*sc_hwinit) __P((struct hme_softc *));
|
||||
|
||||
#if NRND > 0
|
||||
rndsource_element_t rnd_source;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
void hme_config __P((struct hme_softc *));
|
||||
void hme_reset __P((struct hme_softc *));
|
||||
int hme_intr __P((void *));
|
||||
Loading…
Reference in New Issue