diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h index 074b7d1e1cd1..28e0b82116f8 100644 --- a/sys/dev/pci/pcireg.h +++ b/sys/dev/pci/pcireg.h @@ -1,6 +1,7 @@ -/* $NetBSD: pcireg.h,v 1.2 1994/10/27 04:21:41 cgd Exp $ */ +/* $NetBSD: pcireg.h,v 1.3 1995/06/18 01:34:01 cgd Exp $ */ /* + * Copyright (c) 1995 Christopher G. Demetriou. All rights reserved. * Copyright (c) 1994 Charles Hannum. All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,132 +33,173 @@ /* * Standardized PCI configuration information * - * XXX - * This is not complete. + * XXX This is not complete. */ /* * Device identification register; contains a vendor ID and a device ID. - * We have little need to distinguish the two parts. */ #define PCI_ID_REG 0x00 +typedef u_int16_t pci_vendor_id_t; +typedef u_int16_t pci_product_id_t; + +#define PCI_VENDOR_SHIFT 0 +#define PCI_VENDOR_MASK 0xffff +#define PCI_VENDOR(id) \ + (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) + +#define PCI_PRODUCT_SHIFT 16 +#define PCI_PRODUCT_MASK 0xffff +#define PCI_PRODUCT(id) \ + (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) + /* * Command and status register. */ -#define PCI_COMMAND_STATUS_REG 0x04 +#define PCI_COMMAND_STATUS_REG 0x04 -#define PCI_COMMAND_IO_ENABLE 0x00000001 -#define PCI_COMMAND_MEM_ENABLE 0x00000002 -#define PCI_COMMAND_MASTER_ENABLE 0x00000004 -#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 -#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 -#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 -#define PCI_COMMAND_PARITY_ENABLE 0x00000040 -#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 -#define PCI_COMMAND_SERR_ENABLE 0x00000100 -#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 +#define PCI_COMMAND_IO_ENABLE 0x00000001 +#define PCI_COMMAND_MEM_ENABLE 0x00000002 +#define PCI_COMMAND_MASTER_ENABLE 0x00000004 +#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 +#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 +#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 +#define PCI_COMMAND_PARITY_ENABLE 0x00000040 +#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 +#define PCI_COMMAND_SERR_ENABLE 0x00000100 +#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 -#define PCI_STATUS_BACKTOBACK_OKAY 0x00800000 -#define PCI_STATUS_PARITY_ERROR 0x01000000 -#define PCI_STATUS_DEVSEL_FAST 0x00000000 -#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 -#define PCI_STATUS_DEVSEL_SLOW 0x04000000 -#define PCI_STATUS_DEVSEL_MASK 0x06000000 -#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 -#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 -#define PCI_STATUS_MASTER_ABORT 0x20000000 -#define PCI_STATUS_SPECIAL_ERROR 0x40000000 -#define PCI_STATUS_PARITY_DETECT 0x80000000 +#define PCI_STATUS_BACKTOBACK_OKAY 0x00800000 +#define PCI_STATUS_PARITY_ERROR 0x01000000 +#define PCI_STATUS_DEVSEL_FAST 0x00000000 +#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 +#define PCI_STATUS_DEVSEL_SLOW 0x04000000 +#define PCI_STATUS_DEVSEL_MASK 0x06000000 +#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 +#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 +#define PCI_STATUS_MASTER_ABORT 0x20000000 +#define PCI_STATUS_SPECIAL_ERROR 0x40000000 +#define PCI_STATUS_PARITY_DETECT 0x80000000 /* - * Class register; defines basic type of device. + * PCI Class and Revision Register; defines type and revision of device. */ #define PCI_CLASS_REG 0x08 -#define PCI_CLASS_MASK 0xff000000 -#define PCI_SUBCLASS_MASK 0x00ff0000 +typedef u_int8_t pci_class_t; +typedef u_int8_t pci_subclass_t; +typedef u_int8_t pci_interface_t; +typedef u_int8_t pci_revision_t; + +#define PCI_CLASS_SHIFT 24 +#define PCI_CLASS_MASK 0xff +#define PCI_CLASS(cr) \ + (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) + +#define PCI_SUBCLASS_SHIFT 16 +#define PCI_SUBCLASS_MASK 0xff +#define PCI_SUBCLASS(cr) \ + (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) + +#define PCI_INTERFACE_SHIFT 8 +#define PCI_INTERFACE_MASK 0xff +#define PCI_INTERFACE(cr) \ + (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) + +#define PCI_REVISION_SHIFT 0 +#define PCI_REVISION_MASK 0xff +#define PCI_REVISION(cr) \ + (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) /* base classes */ -#define PCI_CLASS_PREHISTORIC 0x00000000 -#define PCI_CLASS_MASS_STORAGE 0x01000000 -#define PCI_CLASS_NETWORK 0x02000000 -#define PCI_CLASS_DISPLAY 0x03000000 -#define PCI_CLASS_MULTIMEDIA 0x04000000 -#define PCI_CLASS_MEMORY 0x05000000 -#define PCI_CLASS_BRIDGE 0x06000000 -#define PCI_CLASS_UNDEFINED 0xff000000 +#define PCI_CLASS_PREHISTORIC 0x00 +#define PCI_CLASS_MASS_STORAGE 0x01 +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MEMORY 0x05 +#define PCI_CLASS_BRIDGE 0x06 +#define PCI_CLASS_UNDEFINED 0xff /* 0x00 prehistoric subclasses */ -#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00000000 -#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 +#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 +#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 /* 0x01 mass storage subclasses */ -#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000 -#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x00010000 -#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x00020000 -#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x00030000 -#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x00800000 +#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 +#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 +#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 +#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 +#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 /* 0x02 network subclasses */ -#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00000000 -#define PCI_SUBCLASS_NETWORK_TOKENRING 0x00010000 -#define PCI_SUBCLASS_NETWORK_FDDI 0x00020000 -#define PCI_SUBCLASS_NETWORK_MISC 0x00800000 +#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 +#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 +#define PCI_SUBCLASS_NETWORK_FDDI 0x02 +#define PCI_SUBCLASS_NETWORK_MISC 0x80 /* 0x03 display subclasses */ -#define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 -#define PCI_SUBCLASS_DISPLAY_XGA 0x00010000 -#define PCI_SUBCLASS_DISPLAY_MISC 0x00800000 +#define PCI_SUBCLASS_DISPLAY_VGA 0x00 +#define PCI_SUBCLASS_DISPLAY_XGA 0x01 +#define PCI_SUBCLASS_DISPLAY_MISC 0x80 /* 0x04 multimedia subclasses */ -#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00000000 -#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x00010000 -#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x00800000 +#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 +#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 +#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 /* 0x05 memory subclasses */ -#define PCI_SUBCLASS_MEMORY_RAM 0x00000000 -#define PCI_SUBCLASS_MEMORY_FLASH 0x00010000 -#define PCI_SUBCLASS_MEMORY_MISC 0x00800000 +#define PCI_SUBCLASS_MEMORY_RAM 0x00 +#define PCI_SUBCLASS_MEMORY_FLASH 0x01 +#define PCI_SUBCLASS_MEMORY_MISC 0x80 /* 0x06 bridge subclasses */ -#define PCI_SUBCLASS_BRIDGE_HOST 0x00000000 -#define PCI_SUBCLASS_BRIDGE_ISA 0x00010000 -#define PCI_SUBCLASS_BRIDGE_EISA 0x00020000 -#define PCI_SUBCLASS_BRIDGE_MC 0x00030000 -#define PCI_SUBCLASS_BRIDGE_PCI 0x00040000 -#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x00050000 -#define PCI_SUBCLASS_BRIDGE_MISC 0x00800000 +#define PCI_SUBCLASS_BRIDGE_HOST 0x00 +#define PCI_SUBCLASS_BRIDGE_ISA 0x01 +#define PCI_SUBCLASS_BRIDGE_EISA 0x02 +#define PCI_SUBCLASS_BRIDGE_MC 0x03 +#define PCI_SUBCLASS_BRIDGE_PCI 0x04 +#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 +#define PCI_SUBCLASS_BRIDGE_MISC 0x80 /* * Mapping registers + * XXX ADJUST */ #define PCI_MAP_REG_START 0x10 #define PCI_MAP_REG_END 0x28 -#define PCI_MAP_MEMORY 0x00000000 -#define PCI_MAP_IO 0x00000001 +#define PCI_MAP_MEMORY 0x00000000 +#define PCI_MAP_IO 0x00000001 -#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 -#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 -#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 -#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 -#define PCI_MAP_MEMORY_CACHABLE 0x00000008 -#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 +#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 +#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 +#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 +#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 +#define PCI_MAP_MEMORY_CACHABLE 0x00000008 +#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 /* - * Interrupt configuration register + * Interrupt Configuration Register; contains interrupt pin and line. */ #define PCI_INTERRUPT_REG 0x3c -#define PCI_INTERRUPT_PIN_MASK 0x0000ff00 -#define PCI_INTERRUPT_PIN_EXTRACT(x) ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff) -#define PCI_INTERRUPT_PIN_NONE 0x00 -#define PCI_INTERRUPT_PIN_A 0x01 -#define PCI_INTERRUPT_PIN_B 0x02 -#define PCI_INTERRUPT_PIN_C 0x03 -#define PCI_INTERRUPT_PIN_D 0x04 +typedef u_int8_t pci_intr_pin_t; +typedef u_int8_t pci_intr_line_t; -#define PCI_INTERRUPT_LINE_MASK 0x000000ff -#define PCI_INTERRUPT_LINE_EXTRACT(x) ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff) -#define PCI_INTERRUPT_LINE_INSERT(x,v) (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0)) +#define PCI_INTERRUPT_PIN_SHIFT 8 +#define PCI_INTERRUPT_PIN_MASK 0xff +#define PCI_INTERRUPT_PIN(icr) \ + (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) + +#define PCI_INTERRUPT_LINE_SHIFT 0 +#define PCI_INTERRUPT_LINE_MASK 0xff +#define PCI_INTERRUPT_LINE(icr) \ + (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) + +#define PCI_INTERRUPT_PIN_NONE 0x00 +#define PCI_INTERRUPT_PIN_A 0x01 +#define PCI_INTERRUPT_PIN_B 0x02 +#define PCI_INTERRUPT_PIN_C 0x03 +#define PCI_INTERRUPT_PIN_D 0x04