Replace 1000 with PAGE_SIZE
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matt
parent
8165c44e7b
commit
4f5250b410
@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.123 2014/02/26 01:03:03 matt Exp $ */
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/* $NetBSD: pmap.h,v 1.124 2014/02/26 01:45:33 matt Exp $ */
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/*
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* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
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@ -80,6 +80,30 @@
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#include <uvm/uvm_object.h>
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#endif
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#ifdef ARM_MMU_EXTENDED
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#define PMAP_TLB_MAX 1
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#define PMAP_TLB_HWPAGEWALKER 1
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#define PMAP_TLB_NUM_PIDS 256
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#define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti)))
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#if PMAP_TLB_MAX > 1
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#define cpu_tlb_info(ci) ((ci)->ci_tlb_info)
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#else
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#define cpu_tlb_info(ci) (&pmap_tlb0_info)
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#endif
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#define pmap_md_tlb_asid_max() (PMAP_TLB_NUM_PIDS - 1)
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#include <uvm/pmap/tlb.h>
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#include <uvm/pmap/pmap_tlb.h>
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/*
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* If we have an EXTENDED MMU and the address space is split evenly between
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* user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for
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* user and kernel address spaces.
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*/
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#if KERNEL_BASE != 0x80000000
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#error ARMv6 or later systems must have a KERNEL_BASE of 0x8000000
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#endif
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#endif /* ARM_MMU_EXTENDED */
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/*
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* a pmap describes a processes' 4GB virtual address space. this
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* virtual address space can be broken up into 4096 1MB regions which
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@ -111,6 +135,8 @@
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* space per l2_dtable. Most processes will, therefore, require only two or
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* three of these to map their whole working set.
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*/
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#define L2_BUCKET_XLOG2 (L1_S_SHIFT)
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#define L2_BUCKET_XSIZE (1 << L2_BUCKET_XLOG2)
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#define L2_BUCKET_LOG2 4
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#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2)
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@ -119,7 +145,7 @@
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* of l2_dtable structures required to track all possible page descriptors
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* mappable by an L1 translation table is given by the following constants:
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*/
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#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
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#define L2_LOG2 (32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2))
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#define L2_SIZE (1 << L2_LOG2)
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/*
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@ -134,6 +160,7 @@
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#ifndef _LOCORE
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#ifndef PMAP_MMU_EXTENDED
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struct l1_ttable;
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struct l2_dtable;
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@ -165,6 +192,7 @@ union pmap_cache_state {
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* Assigned to cs_all to force cacheops to work for a particular pmap
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*/
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#define PMAP_CACHE_STATE_ALL 0xffffffffu
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#endif /* !ARM_MMU_EXTENDED */
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/*
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* This structure is used by machine-dependent code to describe
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@ -182,21 +210,38 @@ struct pmap_devmap {
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* The pmap structure itself
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*/
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struct pmap {
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uint8_t pm_domain;
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bool pm_remove_all;
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bool pm_activated;
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struct l1_ttable *pm_l1;
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#ifndef ARM_HAS_VBAR
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pd_entry_t *pm_pl1vec;
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#endif
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pd_entry_t pm_l1vec;
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union pmap_cache_state pm_cstate;
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struct uvm_object pm_obj;
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kmutex_t pm_obj_lock;
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#define pm_lock pm_obj.vmobjlock
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#ifndef ARM_HAS_VBAR
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pd_entry_t *pm_pl1vec;
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pd_entry_t pm_l1vec;
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#endif
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struct l2_dtable *pm_l2[L2_SIZE];
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struct pmap_statistics pm_stats;
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LIST_ENTRY(pmap) pm_list;
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#ifdef ARM_MMU_EXTENDED
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pd_entry_t *pm_l1;
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paddr_t pm_l1_pa;
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bool pm_remove_all;
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#ifdef MULTIPROCESSOR
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kcpuset_t *pm_onproc;
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kcpuset_t *pm_active;
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struct pmap_asid_info pm_pai[2];
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#else
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struct pmap_asid_info pm_pai[1];
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#endif
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#else
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struct l1_ttable *pm_l1;
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union pmap_cache_state pm_cstate;
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uint8_t pm_domain;
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bool pm_activated;
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bool pm_remove_all;
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#endif
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};
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struct pmap_kernel {
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struct pmap kernel_pmap;
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};
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/*
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@ -306,6 +351,7 @@ bool pmap_extract(pmap_t, vaddr_t, paddr_t *);
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#define PMAP_NEED_PROCWR
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#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */
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#define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */
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#define PMAP_PTE 0x01000000 /* Use PTE cache settings */
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#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
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#define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td))
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@ -324,6 +370,7 @@ void pmap_bootstrap(vaddr_t, vaddr_t);
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void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int);
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int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
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int pmap_prefetchabt_fixup(void *);
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bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
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bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
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struct pcb;
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@ -371,6 +418,8 @@ vtopte(vaddr_t va)
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pd_entry_t *pdep;
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pt_entry_t *ptep;
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KASSERT(trunc_page(va) == va);
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if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false)
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return (NULL);
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return (ptep);
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@ -437,32 +486,63 @@ pmap_ptesync(pt_entry_t *ptep, size_t cnt)
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#endif
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}
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#define PTE_SYNC(ptep) pmap_ptesync((ptep), 1)
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#define PDE_SYNC(pdep) pmap_ptesync((pdep), 1)
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#define PDE_SYNC_RANGE(pdep, cnt) pmap_ptesync((pdep), (cnt))
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#define PTE_SYNC(ptep) pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE)
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#define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt))
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#define l1pte_valid(pde) ((pde) != 0)
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#define l1pte_valid_p(pde) ((pde) != 0)
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#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
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#define l1pte_supersection_p(pde) (l1pte_section_p(pde) \
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&& ((pde) & L1_S_V6_SUPER) != 0)
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#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
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#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
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#define l1pte_pa(pde) ((pde) & L1_C_ADDR_MASK)
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#define l1pte_index(v) ((vaddr_t)(v) >> L1_S_SHIFT)
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#define l1pte_pgindex(v) l1pte_index((v) & L1_ADDR_BITS \
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& ~(PAGE_SIZE * PAGE_SIZE / sizeof(pt_entry_t) - 1))
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#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
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#define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
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static inline void
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l1pte_setone(pt_entry_t *pdep, pt_entry_t pde)
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{
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*pdep = pde;
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}
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static inline void
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l1pte_set(pt_entry_t *pdep, pt_entry_t pde)
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{
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*pdep = pde;
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if (l1pte_page_p(pde)) {
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KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep);
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for (size_t k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) {
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pde += L2_T_SIZE;
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pdep[k] = pde;
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}
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} else if (l1pte_supersection_p(pde)) {
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KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep);
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for (size_t k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) {
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pdep[k] = pde;
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}
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}
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}
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#define l2pte_index(v) ((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT))
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#define l2pte_valid_p(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
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#define l2pte_pa(pte) ((pte) & L2_S_FRAME)
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#define l2pte_minidata(pte) (((pte) & \
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#define l1pte_lpage_p(pte) (((pte) & L2_TYPE_MASK) == L2_TYPE_L)
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#define l2pte_minidata_p(pte) (((pte) & \
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(L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\
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== (L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))
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static inline void
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l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte)
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{
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KASSERT(*ptep == opte);
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*ptep = pte;
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for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
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KASSERT(ptep[k] == opte ? opte + k * L2_S_SIZE : 0);
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for (size_t k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) {
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KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte);
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*ptep++ = pte;
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pte += L2_S_SIZE;
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ptep[k] = pte;
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if (opte)
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opte += L2_S_SIZE;
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}
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}
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@ -482,7 +562,7 @@ l2pte_reset(pt_entry_t *ptep)
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#define pmap_pde_page(pde) l1pte_page_p(*(pde))
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#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
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#define pmap_pte_v(pte) l2pte_valid(*(pte))
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#define pmap_pte_v(pte) l2pte_valid_p(*(pte))
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#define pmap_pte_pa(pte) l2pte_pa(*(pte))
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/* Size of the kernel part of the L1 page table */
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@ -584,11 +664,16 @@ extern void (*pmap_zero_page_func)(paddr_t);
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/*****************************************************************************/
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#define KERNEL_PID 0 /* The kernel uses ASID 0 */
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/*
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* Definitions for MMU domains
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*/
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#define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */
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#define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */
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#define PMAP_DOMAIN_KERNEL 0 /* The kernel pmap uses domain #0 */
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#ifdef ARM_MMU_EXTENDED
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#define PMAP_DOMAIN_USER 1 /* User pmaps use domain #1 */
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#endif
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/*
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* These macros define the various bit masks in the PTE.
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@ -703,7 +788,11 @@ extern void (*pmap_zero_page_func)(paddr_t);
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#define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */
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#endif
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#define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */
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#ifdef ARM_MMU_EXTENDED
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#define L2_S_PROTO_armv7 (L2_TYPE_S|L2_XS_XN)
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#else
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#define L2_S_PROTO_armv7 (L2_TYPE_S)
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#endif
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/*
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* User-visible names for the ones that vary with MMU class.
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