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ep93xx processor on-chip 1/10/100 ethernet MAC driver

This commit is contained in:
joff 2004-12-22 19:11:10 +00:00
parent 4e771f5ddb
commit 4eeab77519
3 changed files with 1021 additions and 0 deletions
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797
sys/arch/arm/ep93xx/epe.c Normal file
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/* $NetBSD: epe.c,v 1.1 2004/12/22 19:11:10 joff Exp $ */
/*
* Copyright (c) 2004 Jesse Off
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.1 2004/12/22 19:11:10 joff Exp $");
#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/malloc.h>
#include <sys/time.h>
#include <sys/device.h>
#include <uvm/uvm_extern.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <arm/cpufunc.h>
#include <arm/ep93xx/epsocvar.h>
#include <arm/ep93xx/ep93xxvar.h>
#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_types.h>
#include <net/if_media.h>
#include <net/if_ether.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#ifdef INET
#include <netinet/in.h>
#include <netinet/in_systm.h>
#include <netinet/in_var.h>
#include <netinet/ip.h>
#include <netinet/if_inarp.h>
#endif
#ifdef NS
#include <netns/ns.h>
#include <netns/ns_if.h>
#endif
#include "bpfilter.h"
#if NBPFILTER > 0
#include <net/bpf.h>
#include <net/bpfdesc.h>
#endif
#include <machine/bus.h>
#ifdef IPKDB_EP93XX
#include <ipkdb/ipkdb.h>
#endif
#include <arm/ep93xx/epereg.h>
#include <arm/ep93xx/epevar.h>
#define EPE_READ(x) \
bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x))
#define EPE_WRITE(x, y) \
bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y))
static int epe_match(struct device *, struct cfdata *, void *);
static void epe_attach(struct device *, struct device *, void *);
static void epe_init(struct epe_softc *);
static int epe_intr(void* arg);
static int epe_mediachange(struct ifnet *);
static void epe_mediastatus(struct ifnet *, struct ifmediareq *);
int epe_mii_readreg (struct device *, int, int);
void epe_mii_writereg (struct device *, int, int, int);
void epe_statchg (struct device *);
void epe_tick (void *);
static int epe_ifioctl (struct ifnet *, u_long, caddr_t);
static void epe_ifstart (struct ifnet *);
static void epe_ifwatchdog (struct ifnet *);
static int epe_ifinit (struct ifnet *);
static void epe_ifstop (struct ifnet *, int);
static void epe_setaddr (struct ifnet *);
CFATTACH_DECL(epe, sizeof(struct epe_softc),
epe_match, epe_attach, NULL, NULL);
static int
epe_match(struct device *parent, struct cfdata *match, void *aux)
{
return 2;
}
static void
epe_attach(struct device *parent, struct device *self, void *aux)
{
struct epe_softc *sc;
struct epsoc_attach_args *sa;
printf("\n");
sc = (struct epe_softc*) self;
sa = aux;
sc->sc_iot = sa->sa_iot;
sc->sc_intr = sa->sa_intr;
sc->sc_dmat = sa->sa_dmat;
if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size,
0, &sc->sc_ioh))
panic("%s: Cannot map registers", self->dv_xname);
ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc);
epe_init(sc);
}
static int
epe_intr(void *arg)
{
struct epe_softc *sc = (struct epe_softc *)arg;
struct ifnet * ifp = &sc->sc_ec.ec_if;
u_int32_t ndq = 0, irq, *cur;
irq = EPE_READ(IntStsC);
begin:
if ((irq & IntSts_RxSQ) == 0) goto txq;
cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) -
sc->ctrlpage_dmamap->dm_segs[0].ds_addr +
sc->ctrlpage);
bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap,
TX_QLEN * 3 * sizeof(u_int32_t),
RX_QLEN * 4 * sizeof(u_int32_t),
BUS_DMASYNC_PREREAD);
while (sc->RXStsQ_cur != cur) {
if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) ==
(RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) {
u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff;
u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff;
struct mbuf *m;
bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap,
0, fl, BUS_DMASYNC_PREREAD);
MGETHDR(m, M_DONTWAIT, MT_DATA);
if (m != NULL) MCLGET(m, M_DONTWAIT);
if (m != NULL && (m->m_flags & M_EXT)) {
bus_dmamap_unload(sc->sc_dmat,
sc->rxq[bi].m_dmamap);
sc->rxq[bi].m->m_pkthdr.rcvif = ifp;
sc->rxq[bi].m->m_pkthdr.len =
sc->rxq[bi].m->m_len = fl;
#if NBPFILTER > 0
if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, sc->rxq[bi].m);
#endif /* NBPFILTER > 0 */
(*ifp->if_input)(ifp, sc->rxq[bi].m);
sc->rxq[bi].m = m;
bus_dmamap_load(sc->sc_dmat,
sc->rxq[bi].m_dmamap,
m->m_ext.ext_buf, MCLBYTES,
NULL, BUS_DMA_NOWAIT);
sc->RXDQ[bi * 2] =
sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr;
bus_dmamap_sync(sc->sc_dmat,
sc->rxq[bi].m_dmamap, 0, MCLBYTES,
BUS_DMASYNC_PREREAD);
} else {
/* Drop packets until we can get replacement
* empty mbufs for the RXDQ.
*/
if (m != NULL) {
m_freem(m);
}
ifp->if_ierrors++;
}
} else {
ifp->if_ierrors++;
}
ndq++;
sc->RXStsQ_cur += 2;
if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) {
sc->RXStsQ_cur = sc->RXStsQ;
}
}
if (ndq > 0) {
ifp->if_ipackets += ndq;
bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap,
TX_QLEN * 3 * sizeof(u_int32_t),
RX_QLEN * 4 * sizeof(u_int32_t),
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
EPE_WRITE(RXStsEnq, ndq);
EPE_WRITE(RXDEnq, ndq);
ndq = 0;
}
txq:
if ((irq & IntSts_TxSQ) == 0)
goto end;
/* Handle transmit completions */
cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) -
sc->ctrlpage_dmamap->dm_segs[0].ds_addr +
sc->ctrlpage);
bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap,
TX_QLEN * 2 * sizeof(u_int32_t),
TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD);
while (sc->TXStsQ_cur != cur) {
u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff;
struct mbuf *m = sc->txq[tbi].m;
if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) {
ifp->if_oerrors++;
}
bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap);
m_freem(m);
do {
sc->txq[tbi].m = NULL;
ndq++;
tbi = (tbi + 1) % TX_QLEN;
} while (sc->txq[tbi].m == m);
ifp->if_opackets++;
sc->TXStsQ_cur++;
if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) {
sc->TXStsQ_cur = sc->TXStsQ;
}
}
if (ndq > 0) {
sc->TXDQ_avail += ndq;
if (sc->TXDQ_avail == TX_QLEN - 1) {
ifp->if_flags &= ~IFF_OACTIVE;
ifp->if_timer = 0;
} else {
ifp->if_timer = 10;
}
if (IFQ_IS_EMPTY(&ifp->if_snd) == 0 &&
sc->TXDQ_avail > TX_QLEN / 2) epe_ifstart(ifp);
ndq = 0;
}
end:
irq = EPE_READ(IntStsC);
if ((irq & (IntSts_TxSQ|IntSts_RxSQ)) != 0)
goto begin;
return (1);
}
static void
epe_init(struct epe_softc *sc)
{
bus_dma_segment_t segs;
caddr_t addr;
int rsegs, err, i;
struct ifnet * ifp = &sc->sc_ec.ec_if;
callout_init(&sc->epe_tick_ch);
/* Select primary Individual Address in Address Filter Pointer */
EPE_WRITE(AFP, 0);
/* Read ethernet MAC, should already be set by bootrom */
bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
sc->sc_enaddr, ETHER_ADDR_LEN);
printf("%s: MAC address %s\n", sc->sc_dev.dv_xname,
ether_sprintf(sc->sc_enaddr));
/* Soft Reset the MAC */
EPE_WRITE(SelfCtl, SelfCtl_RESET);
while(EPE_READ(SelfCtl) & SelfCtl_RESET);
/* suggested magic initialization values from datasheet */
EPE_WRITE(RXBufThrshld, 0x800040);
EPE_WRITE(TXBufThrshld, 0x200010);
EPE_WRITE(RXStsThrshld, 0x40002);
EPE_WRITE(TXStsThrshld, 0x40002);
EPE_WRITE(RXDThrshld, 0x40002);
EPE_WRITE(TXDThrshld, 0x40002);
/* Allocate a page of memory for descriptor and status queues */
err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE,
&segs, 1, &rsegs, BUS_DMA_WAITOK);
if (err == 0) {
err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE,
&sc->ctrlpage, (BUS_DMA_WAITOK));
}
if (err == 0) {
err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE,
0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap);
}
if (err == 0) {
err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap,
sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK);
}
if (err != 0) {
panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname);
}
bzero(sc->ctrlpage, PAGE_SIZE);
/* Set up pointers to start of each queue in kernel addr space.
* Each descriptor queue or status queue entry uses 2 words
*/
sc->TXDQ = (u_int32_t *)sc->ctrlpage;
sc->TXDQ_cur = sc->TXDQ;
sc->TXDQ_avail = TX_QLEN - 1;
sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2];
sc->TXStsQ_cur = sc->TXStsQ;
sc->RXDQ = &sc->TXStsQ[TX_QLEN];
sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2];
sc->RXStsQ_cur = sc->RXStsQ;
/* Program each queue's start addr, cur addr, and len registers
* with the physical addresses.
*/
addr = (caddr_t)sc->ctrlpage_dmamap->dm_segs[0].ds_addr;
EPE_WRITE(TXDQBAdd, (u_int32_t)addr);
EPE_WRITE(TXDQCurAdd, (u_int32_t)addr);
EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t));
addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t);
EPE_WRITE(TXStsQBAdd, (u_int32_t)addr);
EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr);
EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t));
addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t);
EPE_WRITE(RXDQBAdd, (u_int32_t)addr);
EPE_WRITE(RXDCurAdd, (u_int32_t)addr);
EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t));
addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t);
EPE_WRITE(RXStsQBAdd, (u_int32_t)addr);
EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr);
EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t));
/* Populate the RXDQ with mbufs */
for(i = 0; i < RX_QLEN; i++) {
struct mbuf *m;
bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0,
BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap);
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
sc->rxq[i].m = m;
bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap,
m->m_ext.ext_buf, MCLBYTES, NULL,
BUS_DMA_WAITOK);
sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr;
sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES;
bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0,
MCLBYTES, BUS_DMASYNC_PREREAD);
}
for(i = 0; i < TX_QLEN; i++) {
bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
(BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW),
&sc->txq[i].m_dmamap);
sc->txq[i].m = NULL;
sc->TXDQ[i * 2 + 1] = (i << 16);
}
/* Divide HCLK by 32 for MDC clock */
EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(32)|SelfCtl_PSPRS));
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = epe_mii_readreg;
sc->sc_mii.mii_writereg = epe_mii_writereg;
sc->sc_mii.mii_statchg = epe_statchg;
ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange,
epe_mediastatus);
mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn);
EPE_WRITE(IntEn, IntEn_TSQIE|IntEn_REOFIE);
/* maximum valid max frame length */
EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN);
/* wait for receiver ready */
while((EPE_READ(BMSts) & BMSts_RxAct) == 0);
/* enqueue the entries in RXStsQ and RXDQ */
bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, 0,
sc->ctrlpage_dmamap->dm_mapsize,
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
EPE_WRITE(RXDEnq, RX_QLEN - 1);
EPE_WRITE(RXStsEnq, RX_QLEN - 1);
/*
* We can support 802.1Q VLAN-sized frames.
*/
sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST;
ifp->if_ioctl = epe_ifioctl;
ifp->if_start = epe_ifstart;
ifp->if_watchdog = epe_ifwatchdog;
ifp->if_init = epe_ifinit;
ifp->if_stop = epe_ifstop;
ifp->if_timer = 0;
ifp->if_softc = sc;
IFQ_SET_READY(&ifp->if_snd);
if_attach(ifp);
ether_ifattach(ifp, (sc)->sc_enaddr);
}
static int
epe_mediachange(ifp)
struct ifnet *ifp;
{
if (ifp->if_flags & IFF_UP)
epe_ifinit(ifp);
return (0);
}
static void
epe_mediastatus(ifp, ifmr)
struct ifnet *ifp;
struct ifmediareq *ifmr;
{
struct epe_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_active = sc->sc_mii.mii_media_active;
ifmr->ifm_status = sc->sc_mii.mii_media_status;
}
int
epe_mii_readreg(self, phy, reg)
struct device *self;
int phy, reg;
{
struct epe_softc *sc = (struct epe_softc *)self;
u_int32_t d, v;
d = EPE_READ(SelfCtl);
EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */
EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg));
while(EPE_READ(MIISts) & MIISts_BUSY);
v = EPE_READ(MIIData);
EPE_WRITE(SelfCtl, d); /* restore old value */
return v;
}
void
epe_mii_writereg(self, phy, reg, val)
struct device *self;
int phy, reg, val;
{
struct epe_softc *sc = (struct epe_softc *)self;
u_int32_t d;
d = EPE_READ(SelfCtl);
EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */
EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg));
EPE_WRITE(MIIData, val);
while(EPE_READ(MIISts) & MIISts_BUSY);
EPE_WRITE(SelfCtl, d); /* restore old value */
}
void
epe_statchg(self)
struct device *self;
{
struct epe_softc *sc = (struct epe_softc *)self;
u_int32_t reg;
/*
* We must keep the MAC and the PHY in sync as
* to the status of full-duplex!
*/
reg = EPE_READ(TestCtl);
if (sc->sc_mii.mii_media_active & IFM_FDX)
reg |= TestCtl_MFDX;
else
reg &= ~TestCtl_MFDX;
EPE_WRITE(TestCtl, reg);
}
void
epe_tick(arg)
void *arg;
{
struct epe_softc* sc = (struct epe_softc *)arg;
struct ifnet * ifp = &sc->sc_ec.ec_if;
u_int32_t misses;
ifp->if_collisions += EPE_READ(TXCollCnt);
/* These misses are ok, they will happen if the RAM/CPU can't keep up */
misses = EPE_READ(RXMissCnt);
if (misses > 0)
printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses);
mii_tick(&sc->sc_mii);
callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc);
}
static int
epe_ifioctl(ifp, cmd, data)
struct ifnet *ifp;
u_long cmd;
caddr_t data;
{
struct epe_softc *sc = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *)data;
int s, error;
s = splnet();
switch(cmd) {
case SIOCSIFMEDIA:
case SIOCGIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
break;
default:
error = ether_ioctl(ifp, cmd, data);
if (error == ENETRESET) {
if (ifp->if_flags & IFF_RUNNING)
epe_setaddr(ifp);
error = 0;
}
}
splx(s);
return error;
}
static void
epe_ifstart(ifp)
struct ifnet *ifp;
{
struct epe_softc *sc = (struct epe_softc *)ifp->if_softc;
struct mbuf *m;
bus_dma_segment_t *segs;
int s, bi, err, nsegs, ndq = 0;
s = splnet();
if (sc->TXDQ_avail == 0) {
splx(s);
return;
}
bi = sc->TXDQ_cur - sc->TXDQ;
IFQ_POLL(&ifp->if_snd, m);
if (m == NULL) {
splx(s);
return;
}
again:
if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
BUS_DMA_NOWAIT)) ||
sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 ||
sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) {
/* Copy entire mbuf chain to new and 32-bit aligned storage */
struct mbuf *mn;
if (err == 0)
bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap);
MGETHDR(mn, M_DONTWAIT, MT_DATA);
if (mn == NULL) goto stop;
if (m->m_pkthdr.len > (MHLEN & (~0x3))) {
MCLGET(mn, M_DONTWAIT);
if ((mn->m_flags & M_EXT) == 0) {
m_freem(mn);
goto stop;
}
}
mn->m_data = (caddr_t)(((u_int32_t)mn->m_data + 0x3) & (~0x3));
m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, caddr_t));
mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len;
IFQ_DEQUEUE(&ifp->if_snd, m);
m_freem(m);
m = mn;
bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
BUS_DMA_NOWAIT);
} else {
IFQ_DEQUEUE(&ifp->if_snd, m);
}
#if NBPFILTER > 0
if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m);
#endif /* NBPFILTER > 0 */
nsegs = sc->txq[bi].m_dmamap->dm_nsegs;
segs = sc->txq[bi].m_dmamap->dm_segs;
bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0,
sc->txq[bi].m_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
/* XXX: This driver hasn't been tested w/nsegs > 1 */
while (nsegs > 0) {
nsegs--;
sc->txq[bi].m = m;
sc->TXDQ[bi * 2] = segs->ds_addr;
if (nsegs == 0)
sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) |
(1 << 31);
else
sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16);
segs++;
bi = (bi + 1) % TX_QLEN;
ndq++;
}
if ((sc->TXDQ_avail - ndq) > 0) {
IFQ_POLL(&ifp->if_snd, m);
if (m != NULL) {
goto again;
}
}
stop:
if (ndq > 0) {
sc->TXDQ_avail -= ndq;
ifp->if_flags |= IFF_OACTIVE;
ifp->if_timer = 10;
sc->TXDQ_cur = &sc->TXDQ[bi];
bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, 0,
TX_QLEN * 2 * sizeof(u_int32_t),
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
EPE_WRITE(TXDEnq, ndq);
}
splx(s);
return;
}
static void
epe_ifwatchdog(ifp)
struct ifnet *ifp;
{
struct epe_softc *sc = (struct epe_softc *)ifp->if_softc;
if ((ifp->if_flags & IFF_RUNNING) == 0)
return;
printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n",
sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts));
}
static int
epe_ifinit(ifp)
struct ifnet *ifp;
{
struct epe_softc *sc = ifp->if_softc;
int s = splnet();
callout_stop(&sc->epe_tick_ch);
EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON);
EPE_WRITE(TXCtl, TXCtl_STxON);
EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */
mii_mediachg(&sc->sc_mii);
callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc);
ifp->if_flags |= IFF_RUNNING;
splx(s);
return 0;
}
static void
epe_ifstop(ifp, disable)
struct ifnet *ifp;
int disable;
{
struct epe_softc *sc = ifp->if_softc;
EPE_WRITE(RXCtl, 0);
EPE_WRITE(TXCtl, 0);
EPE_WRITE(GIIntMsk, 0);
callout_stop(&sc->epe_tick_ch);
/* Down the MII. */
mii_down(&sc->sc_mii);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ifp->if_timer = 0;
sc->sc_mii.mii_media_status &= ~IFM_ACTIVE;
}
static void
epe_setaddr(ifp)
struct ifnet *ifp;
{
struct epe_softc *sc = ifp->if_softc;
struct ethercom *ac = &sc->sc_ec;
struct ether_multi *enm;
struct ether_multistep step;
u_int8_t ias[2][ETHER_ADDR_LEN];
u_int32_t h, nma = 0, hashes[2] = { 0, 0 };
u_int32_t rxctl = EPE_READ(RXCtl);
/* disable receiver temporarily */
EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON);
rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3);
if (ifp->if_flags & IFF_PROMISC) {
rxctl |= RXCtl_PA;
}
ifp->if_flags &= ~IFF_ALLMULTI;
ETHER_FIRST_MULTI(step, ac, enm);
while (enm != NULL) {
if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
/*
* We must listen to a range of multicast addresses.
* For now, just accept all multicasts, rather than
* trying to set only those filter bits needed to match
* the range. (At this time, the only use of address
* ranges is for IP multicast routing, for which the
* range is big enough to require all bits set.)
*/
rxctl &= ~(RXCtl_IA2|RXCtl_IA3);
rxctl |= RXCtl_MA;
hashes[0] = 0xffffffffUL;
hashes[1] = 0xffffffffUL;
ifp->if_flags |= IFF_ALLMULTI;
break;
}
if (nma < 2) {
/* We can program 2 perfect address filters for mcast */
memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN);
rxctl |= (1 << (nma + 2));
} else {
/*
* XXX: Datasheet is not very clear here, I'm not sure
* if I'm doing this right. --joff
*/
h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
/* Just want the 6 most-significant bits. */
h = h >> 26;
hashes[ h / 32 ] |= (1 << (h % 32));
rxctl |= RXCtl_MA;
}
ETHER_NEXT_MULTI(step, enm);
nma++;
}
EPE_WRITE(AFP, 0);
bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
sc->sc_enaddr, ETHER_ADDR_LEN);
if (rxctl & RXCtl_IA2) {
EPE_WRITE(AFP, 2);
bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
ias[0], ETHER_ADDR_LEN);
}
if (rxctl & RXCtl_IA3) {
EPE_WRITE(AFP, 3);
bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
ias[1], ETHER_ADDR_LEN);
}
if (hashes[0] != 0 && hashes[1] != 0) {
EPE_WRITE(AFP, 7);
EPE_WRITE(HashTbl, hashes[0]);
EPE_WRITE(HashTbl + 4, hashes[1]);
}
EPE_WRITE(RXCtl, rxctl);
}

154
sys/arch/arm/ep93xx/epereg.h Normal file
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/* $NetBSD: epereg.h,v 1.1 2004/12/22 19:11:10 joff Exp $ */
/*
* Copyright (c) 2004 Jesse Off
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
* HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _EPEREG_H_
#define _EPEREG_H_
#define EPE_SIZE 0x000000f0UL
#define EPE_RXCtl 0x00000000UL /* Receiver Control */
#define RXCtl_IA0 0x00000001UL
#define RXCtl_IA1 0x00000002UL
#define RXCtl_IA2 0x00000004UL
#define RXCtl_IA3 0x00000008UL
#define RXCtl_IAHA 0x00000100UL
#define RXCtl_MA 0x00000200UL
#define RXCtl_BA 0x00000400UL
#define RXCtl_PA 0x00000800UL
#define RXCtl_RA 0x00001000UL
#define RXCtl_RCRCA 0x00002000UL
#define RXCtl_SRxON 0x00010000UL
#define RXCtl_BCRC 0x00020000UL
#define RXCtl_RxFCE0 0x00040000UL
#define RXCtl_RxFCE1 0x00080000UL
#define RXCtl_PauseA 0x00100000UL
#define EPE_TXCtl 0x00000004UL /* Transmitter Control */
#define TXCtl_STxON 0x00000001UL
#define EPE_TestCtl 0x00000008UL /* Test Control */
#define TestCtl_MFDX 0x00000040UL
#define EPE_MIICmd 0x00000010UL /* MII Command */
#define MIICmd_READ 0x00008000UL
#define MIICmd_WRITE 0x00004000UL
#define EPE_MIIData 0x00000014UL /* MII Data */
#define EPE_MIISts 0x00000018UL /* MII Status */
#define MIISts_BUSY 0x00000001UL
#define EPE_SelfCtl 0x00000020UL /* Self Control */
#define SelfCtl_RESET 0x00000001UL
#define SelfCtl_PSPRS 0x00000100UL
#define SelfCtl_MDCDIV(x) (((x) - 1) << 9)
#define EPE_IntEn 0x00000024UL /* Interrupt Enable */
#define IntEn_TSQIE 0x00000008UL
#define IntEn_REOFIE 0x00000004UL
#define EPE_IntStsP 0x00000028UL /* Interrupt Status Preserve */
#define EPE_IntStsC 0x0000002cUL /* Interrupt Status Clear */
#define IntSts_RxSQ 0x00000004UL
#define IntSts_TxSQ 0x00000008UL
#define IntSts_ECI 0x02000000UL
#define IntSts_MIII 0x00001000UL
#define EPE_DiagAd 0x00000038UL /* Diagnostic Address */
#define EPE_DiagDa 0x0000003cUL /* Diagnostic Data */
#define EPE_GT 0x00000040UL /* General Timer */
#define EPE_FCT 0x00000044UL /* Flow Control Timer */
#define EPE_FCF 0x00000048UL /* Flow Control Format */
#define EPE_AFP 0x0000004cUL /* Address Filter Pointer */
#define EPE_IndAd 0x00000050UL /* Individual Address */
#define EPE_IndAd_SIZE 0x6
#define EPE_HashTbl 0x00000050UL /* Hash Table */
#define EPE_HashTbl_SIZE 0x8
#define EPE_GIIntSts 0x00000060UL /* Global Interrupt Status */
#define EPE_GIIntMsk 0x00000064UL /* Global Interrupt Mask */
#define GIIntMsk_INT 0x00008000UL
#define EPE_GIIntROSts 0x00000068UL /* Global Interrupt Read-Only Status */
#define EPE_GIIntFrc 0x0000006cUL /* Global Interrupt Force */
#define EPE_TXCollCnt 0x00000070UL /* Transmit Collision Count */
#define EPE_RXMissCnt 0x00000074UL /* Receive Miss Count */
#define EPE_RXRuntCnt 0x00000078UL /* Receive Runt Count */
#define EPE_BMCtl 0x00000080UL /* Bus Master Control */
#define BMCtl_RxEn 0x00000001UL
#define BMCtl_TxEn 0x00000100UL
#define EPE_BMSts 0x00000084UL /* Bus Master Status */
#define BMSts_RxAct 0x00000080UL
#define EPE_RXBCA 0x00000088UL /* Receive Buffer Current Address */
#define EPE_RXDQBAdd 0x00000090UL /* Receive Descriptor Queue Base Addr */
#define EPE_RXDQBLen 0x00000094UL /* Receive Descriptor Queue Base Len */
#define EPE_RXDQCurLen 0x00000096UL /* Recv Descriptor Queue Current Len */
#define EPE_RXDCurAdd 0x00000098UL /* Recv Descriptor Current Address */
#define EPE_RXDEnq 0x0000009cUL /* Receive Descriptor Enqueue */
#define EPE_RXStsQBAdd 0x000000a0UL /* Receive Status Queue Base Address */
#define EPE_RXStsQBLen 0x000000a4UL /* Receive Status Queue Base Length */
#define EPE_RXStsQCurLen 0x000000a6UL /* Recv Sts Q Current Length */
#define EPE_RXStsQCurAdd 0x000000a8UL /* Recv Sts Q Current Address */
#define EPE_RXStsEnq 0x000000acUL /* Receive Status Enqueue */
#define EPE_TXDQBAdd 0x000000b0UL /* Transmit Descriptor Q Base Addr */
#define EPE_TXDQBLen 0x000000b4UL /* Transmit Descriptor Q Base Length */
#define EPE_TXDQCurLen 0x000000b6UL /* Transmit Descriptor Q Current Len */
#define EPE_TXDQCurAdd 0x000000b8UL /* Transmit Descriptor Q Current Addr */
#define EPE_TXDEnq 0x000000bcUL /* Transmit Descriptor Enqueue */
#define EPE_TXStsQBAdd 0x000000c0UL /* Transmit Status Queue Base Address */
#define EPE_TXStsQBLen 0x000000c4UL /* Transmit Status Queue Base Length */
#define EPE_TXStsQCurLen 0x000000c6UL /* Transmit Sts Q Current Len */
#define EPE_TXStsQCurAdd 0x000000c8UL /* Transmit Sts Q Current Adr */
#define EPE_RXBufThrshld 0x000000d0UL /* Receive Buffer Threshold */
#define EPE_TXBufThrshld 0x000000d4UL /* Transmit Buffer Threshold */
#define EPE_RXStsThrshld 0x000000d8UL /* Receive Status Threshold */
#define EPE_TXStsThrshld 0x000000dcUL /* Transmit Status Threshold */
#define EPE_RXDThrshld 0x000000e0UL /* Receive Descriptor Threshold */
#define EPE_TXDThrshld 0x000000e4UL /* Transmit Descriptor Threshold */
#define EPE_MaxFrmLen 0x000000e8UL /* Maximum Frame Length */
#define EPE_RXHdrLen 0x000000ecUL /* Receive Header Length */
#define EPE_MACFIFO 0x00004000UL /* FIFO RAM */
#define EPE_MACFIFO_SIZE 0xc000UL
/* Receive Status Queue, First Word */
#define RXStsQ_RFP 0x80000000UL
#define RXStsQ_RWE 0x40000000UL
#define RXStsQ_EOF 0x20000000UL
#define RXStsQ_EOB 0x10000000UL
#define RXStsQ_RX_Err 0x00200000UL
#define RXStsQ_OE 0x00100000UL
#define RXStsQ_FE 0x00080000UL
#define RXStsQ_Runt 0x00040000UL
#define RXStsQ_EData 0x00020000UL
#define RXStsQ_CRCE 0x00010000UL
#define RXStsQ_CRCI 0x00008000UL
/* Transmit Status Queue */
#define TXStsQ_TxFP 0x80000000UL
#define TXStsQ_TxWE 0x40000000UL
#define TXStsQ_FA 0x20000000UL
#define TXStsQ_LCRS 0x10000000UL
#define TXStsQ_OW 0x04000000UL
#define TXStsQ_TxU 0x02000000UL
#define TXStsQ_EColl 0x01000000UL
#endif /* _EPEREG_H_ */

70
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/* $NetBSD: epevar.h,v 1.1 2004/12/22 19:11:10 joff Exp $ */
/*-
* Copyright (c) 2004 Jesse Off
* All rights reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ifndef _EPEVAR_H_
#define _EPEVAR_H_
#define TX_QLEN 16
#define RX_QLEN 64
struct epe_qmeta {
struct mbuf *m;
bus_dmamap_t m_dmamap;
};
struct epe_softc {
struct device sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
bus_dma_tag_t sc_dmat;
int sc_intr;
u_int8_t sc_enaddr[ETHER_ADDR_LEN];
struct ethercom sc_ec;
mii_data_t sc_mii;
caddr_t ctrlpage;
bus_dmamap_t ctrlpage_dmamap;
u_int32_t *TXDQ;
u_int32_t TXDQ_avail;
u_int32_t *TXDQ_cur;
u_int32_t *TXStsQ;
u_int32_t *TXStsQ_cur;
u_int32_t *RXDQ;
u_int32_t *RXStsQ;
u_int32_t *RXStsQ_cur;
struct epe_qmeta rxq[RX_QLEN];
struct epe_qmeta txq[TX_QLEN];
struct callout epe_tick_ch;
};
#endif /* _EPEVAR_H_ */