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Align descriptors to 64 bytes instead of CACHE_LINE_SIZE (128) as all known 

Allwinner SoCs with this part use 64-byte cache lines.
This commit is contained in:
jmcneill 2021-02-21 16:07:43 +00:00
parent 905a01e770
commit 4d6fdc916e
1 changed files with 2 additions and 2 deletions
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4
sys/arch/arm/sunxi/sunxi_emac.h
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@ -203,8 +203,8 @@ struct sunxi_emac_desc {
uint32_t addr;
uint32_t next;
} __packed __aligned(CACHE_LINE_SIZE);
} __packed __aligned(64);
__CTASSERT(sizeof(struct sunxi_emac_desc) == CACHE_LINE_SIZE);
__CTASSERT(sizeof(struct sunxi_emac_desc) == 64);
#endif /* !__SUNXI_EMAC_H__ */