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@ -340,7 +340,7 @@ ENTRY_NP(armv7_icache_inv_all)
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END(armv7_icache_inv_all)
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END(armv7_icache_inv_all)
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/* * LINTSTUB: void armv7_dcache_l1inv_all(void); */
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/* * LINTSTUB: void armv7_dcache_l1inv_all(void); */
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ENTRY_NP(armv7_cache_l1inv_all)
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ENTRY_NP(armv7_dcache_l1inv_all)
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mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
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mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
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and r0, r0, #0x7 @ check L1
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and r0, r0, #0x7 @ check L1
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bxeq lr @ return if no L1 cache
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bxeq lr @ return if no L1 cache
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