From 4c72b7951882028c2cbdbb3dab06add491fdbfd0 Mon Sep 17 00:00:00 2001 From: jkunz Date: Thu, 29 Jul 2004 19:10:23 +0000 Subject: [PATCH] Import PCI support from OpenBSD and update GENERIC config for PCI devices. --- sys/arch/hp700/conf/GENERIC | 348 +++--- sys/arch/hp700/conf/files.hp700 | 45 +- sys/arch/hp700/dev/com_dino.c | 126 ++ sys/arch/hp700/dev/dino.c | 1697 ++++++++++++++++++++++++++ sys/arch/hp700/hp700/autoconf.c | 104 +- sys/arch/hp700/include/pci_machdep.h | 93 ++ 6 files changed, 2180 insertions(+), 233 deletions(-) create mode 100644 sys/arch/hp700/dev/com_dino.c create mode 100644 sys/arch/hp700/dev/dino.c create mode 100644 sys/arch/hp700/include/pci_machdep.h diff --git a/sys/arch/hp700/conf/GENERIC b/sys/arch/hp700/conf/GENERIC index 24d84fb2d973..5d2ce6553c01 100644 --- a/sys/arch/hp700/conf/GENERIC +++ b/sys/arch/hp700/conf/GENERIC @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC,v 1.28 2004/07/25 21:52:56 jkunz Exp $ +# $NetBSD: GENERIC,v 1.29 2004/07/29 19:10:23 jkunz Exp $ # # GENERIC machine description file # @@ -23,7 +23,7 @@ include "arch/hp700/conf/std.hp700" options INCLUDE_CONFIG_FILE # embed config file in kernel binary options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel -#ident "GENERIC-$Revision: 1.28 $" +#ident "GENERIC-$Revision: 1.29 $" maxusers 32 # estimated number of users @@ -81,7 +81,6 @@ options DDB_HISTORY_SIZE=512 # enable history editing in DDB #makeoptions DEBUG="-g" # compile full symbol table # Compatibility options -options COMPAT_15 # compatability with NetBSD 1.5, options COMPAT_43 # and 4.3BSD #options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended. @@ -124,12 +123,12 @@ options INET6 # IPV6 #options IPSEC_ESP # IP security (encryption part; define w/IPSEC) #options IPSEC_DEBUG # debug for IP security #options MROUTING # IP multicast routing -options NS # XNS +#options NS # XNS #options NSIP # XNS tunneling over IP -options ISO,TPIP # OSI +#options ISO,TPIP # OSI #options EON # OSI tunneling over IP -options CCITT,LLC,HDLC # X.25 -options NETATALK # AppleTalk networking protocols +#options CCITT,LLC,HDLC # X.25 +#options NETATALK # AppleTalk networking protocols options PPP_BSDCOMP # BSD-Compress compression support for PPP options PPP_DEFLATE # Deflate compression support for PPP options PPP_FILTER # Active filter support for PPP (requires bpf) @@ -209,34 +208,39 @@ mem* at mainbus0 # /dev/*mem and memory controller # Basic Bus Support lasi* at mainbus0 # LASI host adapter (LSI PN??? ) -asp0 at mainbus0 # this one comes w/ Viper and leds -wax* at mainbus0 # Wax may host EISA as well +asp* at mainbus0 # this one comes w/ Viper and leds +wax* at mainbus0 # Wax GSC to GSC Bus Adapter mongoose* at mainbus0 irq 17 # EISA Bus Adapter (i82350 or TI??? ) #vmeb* at mainbus0 irq ? # VME bus adapter -#dino* at mainbus0 irq ? # PCI bus bridge pdc0 at mainbus0 # PDC/IODC wrapper for boot console -phantomas0 at mainbus0 # Phantom PseudoBC GSC+ Port -lasi* at phantomas0 # LASI on [ABCJ?]* -wax* at phantomas? # Wax may host EISA as well +phantomas* at mainbus0 # Phantom PseudoBC GSC+ Port +lasi* at phantomas? # LASI on [ABCJ?]* +dino* at phantomas? # PCI bus bridge +wax* at phantomas? # Wax GSC to GSC Bus Adapter # GSC bus support gsc* at lasi? # 712 gsc* at asp? # 7xx (old) gsc* at wax? # {725,715}/{64,80,100}, C*, B*, J* +# Wax GSC to EISA Bus Adapter +#weisa* at mainbus0 # 7xx +#weisa* at gsc? # C*, B* + # PCI bus support -#pci* at dino? +pci* at dino? +com* at dino? +ppb* at pci? dev ? function ? +pci* at ppb? # EISA bus support eisa* at mongoose? -#eisa* at wax? -#eisa0 at pceb? +#eisa* at weisa? # ISA bus support +# Beware: Most ISA MI drivers are not endianes clean! #isa* at mongoose? -#isa* at wax? -#isa0 at pceb? -#isa0 at pcib? +#isa* at weisa? # VME bus support #vme* at vmeb? @@ -252,9 +256,7 @@ eisa* at mongoose? #pckbc* at gsc? # pc keyboard controller #pckbd* at pckbc? # PC keyboard #pms* at pckbc? # PS/2 mouse for wsmouse -#vga0 at isa? #vga* at pci? dev ? function ? -#pcdisplay0 at isa? # CGA, MDA, EGA, HGA #wsdisplay* at sti? #wsdisplay* at vga? console ? #wsdisplay* at pcdisplay? console ? @@ -268,37 +270,19 @@ eisa* at mongoose? # GSC serial interfaces com* at gsc? # RS/232 serial port -# ISA serial interfaces -#options COM_HAYESP # adds Hayes ESP serial board support -#com0 at isa? port 0x3f8 irq 4 # Standard PC serial ports -#com1 at isa? port 0x2f8 irq 3 -#com2 at isa? port 0x3e8 irq 5 -#com3 at isa? port 0x2e8 irq 9 -#ast0 at isa? port 0x1a0 irq 5 # AST 4-port serial cards -#com* at ast? slave ? -#boca0 at isa? port 0x100 irq 5 # BOCA 8-port serial cards -#boca0 at isa? port 0x100 irq 5 # BOCA 16-port serial cards (BB2016) -#boca1 at isa? port 0x140 irq 5 # this line is also needed for BB2016 -#com* at boca? slave ? -#tcom0 at isa? port 0x100 irq 7 # TC-800 8-port serial cards -#com* at tcom? slave ? -#rtfps0 at isa? port 0x1230 irq 10 # RT 4-port serial cards -#com* at rtfps? slave ? -#cy0 at isa? iomem 0xd4000 irq 12 # Cyclades serial cards -#addcom0 at isa? port 0x108 irq 5 # Addonics FlexPort 8S -#com* at addcom? slave ? -#moxa0 at isa? port 0x100 irq 5 # MOXA C168H serial card (experimental) -#com* at moxa? slave ? +# PCI serial interfaces +puc* at pci? dev ? function ? # PCI "universal" comm. cards +com* at puc? port ? # 16x50s on "universal" comm boards +cy* at pci? dev ? function ? # Cyclades Cyclom-Y serial boards +cz* at pci? dev ? function ? # Cyclades-Z multi-port serial boards # Parallel Printer Interfaces # GSC parallel printer interface lpt* at gsc? -# ISA parallel printer interfaces -#lpt0 at isa? port 0x378 irq 7 # standard PC parallel ports -#lpt1 at isa? port 0x278 -#lpt2 at isa? port 0x3bc +# PCI parallel printer interfaces +lpt* at puc? port ? # || ports on "universal" comm boards # SCSI Controllers and Devices @@ -306,31 +290,32 @@ lpt* at gsc? oosiop* at gsc? # NCR 53c700 osiop* at gsc? flags 0x00000 # NCR 53c710 #siop* at gsc? # NCR 53c720 (Fast/Wide) +#siop* at mainbus0 # NCR 53c720 (Fast/Wide) + +# PCI SCSI controllers +adv* at pci? dev ? function ? # AdvanSys 1200[A,B], 9xx[U,UA] SCSI +adw* at pci? dev ? function ? # AdvanSys 9x0UW[D], 3940U[2,3]W SCSI +ahc* at pci? dev ? function ? # Adaptec [23]94x, aic78x0 SCSI +ahd* at pci? dev ? function ? # Adaptec 29320, 39320 (aic790x) SCSI +bha* at pci? dev ? function ? # BusLogic 9xx SCSI +dpt* at pci? dev ? function ? # DPT SmartCache/SmartRAID +iha* at pci? dev ? function ? # Initio INIC-940/950 SCSI +isp* at pci? dev ? function ? # Qlogic ISP [12]0x0 SCSI/FibreChannel +mly* at pci? dev ? function ? # Mylex AcceleRAID and eXtremeRAID +mpt* at pci? dev ? function ? # LSI Fusion SCSI/FC +pcscp* at pci? dev ? function ? # AMD 53c974 PCscsi-PCI SCSI +siop* at pci? dev ? function ? # Symbios 53c8xx SCSI +esiop* at pci? dev ? function ? # Symbios 53c875 SCSI and newer +#options SIOP_SYMLED # drive the act. LED in software +trm* at pci? dev ? function ? # Tekram DC-395U/UW/F, DC-315/U SCSI # EISA SCSI controllers ahb* at eisa? slot ? # Adaptec 174[02] SCSI -#ahc* at eisa? slot ? # Adaptec 274x, aic7770 SCSI +ahc* at eisa? slot ? # Adaptec 274x, aic7770 SCSI bha* at eisa? slot ? # BusLogic 7xx SCSI dpt* at eisa? slot ? # DPT EATA SCSI uha* at eisa? slot ? # UltraStor 24f SCSI -# ISA SCSI controllers -#adv0 at isa? port ? irq ? drq ? # AdvanSys APB-514[02] SCSI -#aha0 at isa? port 0x330 irq ? drq ? # Adaptec 154[02] SCSI -#aha1 at isa? port 0x334 irq ? drq ? -#aic0 at isa? port 0x340 irq 11 # Adaptec 152[02] SCSI -#bha0 at isa? port 0x330 irq ? drq ? # BusLogic [457]4X SCSI -#bha1 at isa? port 0x334 irq ? drq ? -# The "nca" and "dpt" probes might give false hits or hang your machine. -#dpt0 at isa? port 0x170 irq ? drq ? # DPT SmartCache/SmartRAID -#nca0 at isa? port 0x360 irq 15 # Port-mapped NCR 53C80 controller -#nca1 at isa? iomem 0xd8000 irq 5 # Memory-mapped controller (T128, etc.) -#sea0 at isa? iomem 0xc8000 irq 5 # Seagate/Future Domain SCSI -#uha0 at isa? port 0x330 irq ? drq ? # UltraStor [13]4f SCSI -#uha1 at isa? port 0x340 irq ? drq ? -#wds0 at isa? port 0x350 irq 15 drq 6 # WD7000 and TMC-7000 controllers -#wds1 at isa? port 0x358 irq 11 drq 5 - # SCSI bus support scsibus* at scsi? @@ -345,20 +330,50 @@ uk* at scsibus? target ? lun ? # SCSI unknown # RAID controllers and devices +# aac is broken +#aac* at pci? dev ? function ? # Adaptec AAC family +amr* at pci? dev ? function ? # AMI/LSI Logic MegaRAID cac* at eisa? slot ? # Compaq EISA array controllers +cac* at pci? dev ? function ? # Compaq PCI array controllers +icp* at pci? dev ? function ? # ICP-Vortex GDT & Intel RAID +mlx* at pci? dev ? function ? # Mylex DAC960 & DEC SWXCR family mlx* at eisa? slot ? # Mylex DAC960 & DEC SWXCR family +twe* at pci? dev ? function ? # 3ware Escalade RAID controllers +#ld* at aac? unit ? # logical disk devices +ld* at amr? unit ? ld* at cac? unit ? +ld* at icp? unit ? ld* at mlx? unit ? +ld* at twe? unit ? + +icpsp* at icp? unit ? # SCSI pass-through # IDE and related devices +# PCI IDE controllers - see pciide(4) for supported hardware. +# The 0x0001 flag force the driver to use DMA, even if the driver doesn't know +# how to set up DMA modes for this chip. This may work, or may cause +# a machine hang with some controllers. +pciide* at pci? dev ? function ? flags 0x0000 # GENERIC pciide driver +acardide* at pci? dev ? function ? # Acard IDE controllers +aceride* at pci? dev ? function ? # Acer Lab IDE controllers +artsata* at pci? dev ? function ? # Intel i31244 SATA controller +cmdide* at pci? dev ? function ? # CMD tech IDE controllers +cypide* at pci? dev ? function ? # Cypress IDE controllers +geodeide* at pci? dev ? function ? # AMD Geode IDE controllers +hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers +optiide* at pci? dev ? function ? # Opti IDE controllers +piixide* at pci? dev ? function ? # Intel IDE controllers +pdcide* at pci? dev ? function ? # Promise IDE controllers +rccide* at pci? dev ? function ? # ServerWorks IDE controllers +satalink* at pci? dev ? function ? # SiI SATALink controllers +siside* at pci? dev ? function ? # SiS IDE controllers +slide* at pci? dev ? function ? # Symphony Labs IDE controllers +stpcide* at pci? dev ? function ? # STMicro STPC IDE controllers +viaide* at pci? dev ? function ? # VIA/AMD/Nvidia IDE controllers -# ISA ST506, ESDI, and IDE controllers -# Use flags 0x01 if you want to try to use 32bits data I/O (the driver will -# fall back to 16bits I/O if 32bits I/O are not functional). -# Some controllers pass the initial 32bit test, but will fail later. -#wdc0 at isa? port 0x1f0 irq 14 flags 0x00 -#wdc1 at isa? port 0x170 irq 15 flags 0x00 +# ATA (IDE) bus support +atabus* at ata? # IDE drives # Flags are used only with controllers that support DMA operations @@ -371,41 +386,27 @@ ld* at mlx? unit ? # 0x0fac means 'use PIO mode 4, DMA mode 2, disable UltraDMA'. # (0xc=1100, 0xa=1010, 0xf=1111) # 0x0000 means "use whatever the drive claims to support". -#wd* at wdc? channel ? drive ? flags 0x0000 +wd* at atabus? drive ? flags 0x0000 + +# ATA RAID configuration support, as found on some Promise controllers. +pseudo-device ataraid +ld* at ataraid? vendtype ? unit ? # ATAPI bus support -#atapibus* at wdc? channel ? +atapibus* at atapi? # ATAPI devices # flags have the same meaning as for IDE drives. -#cd* at atapibus? drive ? flags 0x0000 # ATAPI CD-ROM drives -#sd* at atapibus? drive ? flags 0x0000 # ATAPI disk drives -#st* at atapibus? drive ? flags 0x0000 # ATAPI tape drives -#uk* at atapibus? drive ? flags 0x0000 # ATAPI unknown - +cd* at atapibus? drive ? flags 0x0000 # ATAPI CD-ROM drives +sd* at atapibus? drive ? flags 0x0000 # ATAPI disk drives +st* at atapibus? drive ? flags 0x0000 # ATAPI tape drives +uk* at atapibus? drive ? flags 0x0000 # ATAPI unknown # Miscellaneous mass storage devices # GSC floppy #fdc* at gsc? # PC floppy controller (WD37C65C) -#options FD_DEBUG - -# ISA floppy -#fdc0 at isa? port 0x3f0 irq 6 drq 2 # standard PC floppy controllers -#fdc1 at isa? port 0x370 irq ? drq ? #fd* at fdc? drive ? # the drives themselves -# some machines need you to do this instead of fd* -#fd0 at fdc0 drive 0 - -# ISA CD-ROM devices -#mcd0 at isa? port 0x300 irq 10 # Mitsumi CD-ROM drives - -# ISA tape devices -# note: the wt driver conflicts unpleasantly with SMC boards at the -# same I/O address. The probe reprograms their EEPROMs. Don't -# uncomment it unless you are actually using it. -#wt0 at isa? port 0x308 irq 5 drq 1 # Archive and Wangtek QIC tape drives - # Network Interfaces @@ -414,6 +415,42 @@ ld* at mlx? unit ? #ie* at gsc? # old 82C5[89]6 Ethernet, use iee(4) iee* at gsc? # 82C596 Ethernet +# PCI network interfaces +an* at pci? dev ? function ? # Aironet PC4500/PC4800 (802.11) +atw* at pci? dev ? function ? # ADMtek ADM8211 (802.11) +bce* at pci? dev ? function ? # Broadcom 4401 10/100 Ethernet +bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet +# en is broken, uses vtophys +#en* at pci? dev ? function ? # ENI/Adaptec ATM +ep* at pci? dev ? function ? # 3Com 3c59x +epic* at pci? dev ? function ? # SMC EPIC/100 Ethernet +esh* at pci? dev ? function ? # Essential HIPPI card +ex* at pci? dev ? function ? # 3Com 90x[BC] +# fpa is broken, does funky things with bus_dma +#fpa* at pci? dev ? function ? # DEC DEFPA FDDI +fxp* at pci? dev ? function ? # Intel EtherExpress PRO 10+/100B +gsip* at pci? dev ? function ? # NS83820 Gigabit Ethernet +le* at pci? dev ? function ? # PCnet-PCI Ethernet +lmc* at pci? dev ? function ? # Lan Media Corp SSI/HSSI/DS3 +mtd* at pci? dev ? function ? # Myson MTD803 3-in-1 Ethernet +ne* at pci? dev ? function ? # NE2000-compatible Ethernet +ntwoc* at pci? dev ? function ? # Riscom/N2 PCI Sync Serial +pcn* at pci? dev ? function ? # AMD PCnet-PCI Ethernet +re* at pci? dev ? function ? # Realtek 8139C+/8169/8169S/8110S +rtk* at pci? dev ? function ? # Realtek 8129/8139 +sf* at pci? dev ? function ? # Adaptec AIC-6915 Ethernet +sip* at pci? dev ? function ? # SiS 900/DP83815 Ethernet +skc* at pci? dev ? function ? # SysKonnect SK9821 Gigabit Ethernet +sk* at skc? # SysKonnect SK9821 Gigabit Ethernet +ste* at pci? dev ? function ? # Sundance ST-201 Ethernet +stge* at pci? dev ? function ? # Sundance/Tamarack TC9021 Gigabit +ti* at pci? dev ? function ? # Alteon ACEnic gigabit Ethernet +tl* at pci? dev ? function ? # ThunderLAN-based Ethernet +tlp* at pci? dev ? function ? # DECchip 21x4x and clones +vr* at pci? dev ? function ? # VIA Rhine Fast Ethernet +wi* at pci? dev ? function ? # Intersil Prism Mini-PCI (802.11b) +wm* at pci? dev ? function ? # Intel 8254x gigabit + # EISA network interfaces ep* at eisa? slot ? # 3Com 3c579 Ethernet #fea* at eisa? slot ? # DEC DEFEA FDDI @@ -421,41 +458,31 @@ tlp* at eisa? slot ? # DEC DE-425 Ethernet #sh* at eisa? slot ? # Interphase Seahawk 4811 FDDI #ie* at eisa? slot ? # Intel Ethernet -# ISA network interfaces -#ate0 at isa? port 0x2a0 irq ? # AT1700 -#cs0 at isa? port 0x300 iomem ? irq ? drq ? # CS8900 Ethernet -#ec0 at isa? port 0x250 iomem 0xd8000 irq 9 # 3Com 3c503 Ethernet -#eg0 at isa? port 0x280 irq 9 # 3C505 ethernet cards -#el0 at isa? port 0x300 irq 9 # 3C501 ethernet cards -#ep* at isa? port ? irq ? # 3C509 ethernet cards -#ef0 at isa? port 0x360 iomem 0xd0000 irq 7 # 3C507 -#ai0 at isa? port 0x360 iomem 0xd0000 irq 7 # StarLAN -#fmv0 at isa? port 0x2a0 irq ? # FMV-180 series -#ie* at isa? port 0x360 iomem 0xd0000 irq 7 # Intel Ethernet -#ie* at isa? port 0x300 irq 10 # Intel Ethernet -#ix0 at isa? port 0x300 irq 10 # EtherExpress/16 -#iy0 at isa? port 0x360 irq ? # EtherExpress PRO 10 ISA -#lc0 at isa? port 0x320 iomem ? irq ? # DEC EtherWORKS III (LEMAC) -#depca0 at isa? port 0x300 iomem 0xc8000 iosiz 0x8000 irq 5 # DEPCA -#le* at depca? -#nele0 at isa? port 0x320 irq 9 drq 7 # NE2100 -#le* at nele? -#ntwoc0 at isa? port 0x300 irq 5 iomem 0xc8000 flags 1 # Riscom/N2 sync serial -#bicc0 at isa? port 0x320 irq 10 drq 7 # BICC IsoLan -#le* at bicc? -#ne0 at isa? port 0x280 irq 9 # NE[12]000 ethernet cards -#ne1 at isa? port 0x300 irq 10 -#sm0 at isa? port 0x300 irq 10 # SMC91C9x Ethernet -#tr0 at isa? port 0xa20 iomem 0xd8000 irq ? # IBM TROPIC based Token-Ring -#tr1 at isa? port 0xa24 iomem 0xd0000 irq ? # IBM TROPIC based Token-Ring -#tr* at isa? port ? irq ? # 3COM TROPIC based Token-Ring -#we0 at isa? port 0x280 iomem 0xd0000 irq 9 # WD/SMC Ethernet -#we1 at isa? port 0x300 iomem 0xcc000 irq 10 - # MII/PHY support +acphy* at mii? phy ? # Altima AC101 and AMD Am79c874 PHYs +amhphy* at mii? phy ? # AMD 79c901 Ethernet PHYs +bmtphy* at mii? phy ? # Broadcom BCM5201 and BCM5202 PHYs +brgphy* at mii? phy ? # Broadcom BCM5400-family PHYs +dmphy* at mii? phy ? # Davicom DM9101 PHYs exphy* at mii? phy ? # 3Com internal PHYs +gentbi* at mii? phy ? # Generic Ten-Bit 1000BASE-[CLS]X PHYs +glxtphy* at mii? phy ? # Level One LXT-1000 PHYs +gphyter* at mii? phy ? # NS83861 Gig-E PHY +icsphy* at mii? phy ? # Integrated Circuit Systems ICS189x +igphy* at mii? phy ? # Intel IGP01E1000 +inphy* at mii? phy ? # Intel 82555 PHYs +iophy* at mii? phy ? # Intel 82553 PHYs +lxtphy* at mii? phy ? # Level One LXT-970 PHYs +makphy* at mii? phy ? # Marvell Semiconductor 88E1000 PHYs +nsphy* at mii? phy ? # NS83840 PHYs +nsphyter* at mii? phy ? # NS83843 PHYs +pnaphy* at mii? phy ? # generic HomePNA PHYs +qsphy* at mii? phy ? # Quality Semiconductor QS6612 PHYs +sqphy* at mii? phy ? # Seeq 80220/80221/80223 PHYs +tlphy* at mii? phy ? # ThunderLAN PHYs +tqphy* at mii? phy ? # TDK Semiconductor PHYs ukphy* at mii? phy ? # generic unknown PHYs - +urlphy* at mii? phy ? # Realtek RTL8150L internal PHYs # Audio Devices @@ -463,74 +490,7 @@ ukphy* at mii? phy ? # generic unknown PHYs #aone* at gsc? # Audio Type 1 (PSB 2160-N) #harmony* at gsc? # Audio Type 2 (CS4215) #com* at harmony? # Telephone add-in card - -# ISA audio devices -# the "aria" probe might give false hits -#aria0 at isa? port 0x290 irq 10 # Aria -#ess0 at isa? port 0x220 irq 5 drq 1 drq2 5 # ESS 18XX -#gus0 at isa? port 0x220 irq 7 drq 1 drq2 6 # Gravis Ultra Sound -#pas0 at isa? port 0x220 irq 7 drq 1 # ProAudio Spectrum -#pss0 at isa? port 0x220 irq 7 drq 6 # Personal Sound System -#sp0 at pss0 port 0x530 irq 10 drq 0 # sound port driver -#sb0 at isa? port 0x220 irq 5 drq 1 drq2 5 # SoundBlaster -#wss0 at isa? port 0x530 irq 10 drq 0 drq2 1 # Windows Sound System - -#cms0 at isa? port 0x220 # Creative Music System - -# OPL[23] FM synthesizers -#opl0 at isa? port 0x388 # use only if not attached to sound card -#opl* at ess? -#opl* at sb? -#opl* at wss? - -# Audio support -#audio* at aone? -#audio* at aria? -#audio* at ess? -#audio* at gus? -#audio* at harmony? -#audio* at pas? -#audio* at sb? -#audio* at sp? -#audio* at wss? - -# MPU 401 UARTs -#mpu* at isa? port 0x330 irq 9 # MPU401 or compatible card -#mpu* at sb? - -# MIDI support -#midi* at opl? # OPL FM synth -#midi* at pcppi? # MIDI interface to the PC speaker -#midi* at sb? # SB1 MIDI port - -# FM-Radio devices -# ISA radio devices -#az0 at isa? port 0x350 # Aztech/PackardBell FM Radio Card -#az1 at isa? port 0x358 -#rt0 at isa? port 0x20c # AIMS Lab Radiotrack & compatible -#rt1 at isa? port 0x284 -#rt2 at isa? port 0x30c -#rt3 at isa? port 0x384 -#rtii0 at isa? port 0x20c # AIMS Lab Radiotrack II FM Radio Card -#rtii1 at isa? port 0x30c -#sf2r0 at isa? port 0x384 # SoundForte RadioLink SF16-FMR2 FM Radio Card - -# Radio support -#radio* at az? -#radio* at rt? -#radio* at rtii? -#radio* at sf2r? - -# Joysticks - -# ISA joysticks. Probe is a little strange; add only if you have one. -#joy0 at isa? port 0x201 - - -# Miscellaneous Devices - -# Planetconnect Satellite receiver driver. -#satlink0 at isa? port 0x300 drq 1 +#audio* at audiobus? # Pseudo-Devices diff --git a/sys/arch/hp700/conf/files.hp700 b/sys/arch/hp700/conf/files.hp700 index 6c9ae51bfbac..ff3b58692e9d 100644 --- a/sys/arch/hp700/conf/files.hp700 +++ b/sys/arch/hp700/conf/files.hp700 @@ -1,4 +1,4 @@ -# $NetBSD: files.hp700,v 1.10 2004/07/25 21:52:56 jkunz Exp $ +# $NetBSD: files.hp700,v 1.11 2004/07/29 19:10:23 jkunz Exp $ # # $OpenBSD: files.hp700,v 1.31 2001/06/26 02:41:25 mickey Exp $ # @@ -18,21 +18,35 @@ defflag USELEDS include "dev/wscons/files.wscons" include "dev/wsfont/files.wsfont" +include "dev/pckbport/files.pckbport" # # Machine-independent SCSI drivers # include "dev/scsipi/files.scsipi" -# I2O +# +# Machine-independent ATA drivers +# +include "dev/ata/files.ata" + +# +# Machine-independent I2O drivers +# include "dev/i2o/files.i2o" # -# MI ATAPI drivers +# Machine-independent USB drivers # -#include "dev/atapiscsi/files.atapiscsi" -#include "dev/ata/files.ata" +include "dev/usb/files.usb" -include "dev/pckbport/files.pckbport" +# +# Machine-independent IEEE1394 drivers +# +include "dev/ieee1394/files.ieee1394" +# +# PCI Bus support +# +include "dev/pci/files.pci" # # ISA Bus support @@ -44,10 +58,6 @@ include "dev/isa/files.isa" # include "dev/eisa/files.eisa" -# -# PCI Bus support -# -include "dev/pci/files.pci" # # Gonzo System Connect Bus @@ -106,10 +116,15 @@ device mongoose: isabus, eisabus attach mongoose at mainbus file arch/hp700/dev/mongoose.c mongoose -device dino: pcibus -attach dino at mainbus +# Dino, GSC to PCI bridge. Includes ps/2, serial, and flying toaster interfaces +# Cujo is a 64-bit data path Dino +device dino { }: pcibus +attach dino at phantomas file arch/hp700/dev/dino.c dino +attach com at dino with com_dino +file arch/hp700/dev/com_dino.c com_dino + device sti: wsemuldisplaydev attach sti at mainbus with sti_sgc file arch/hp700/dev/sti_sgc.c sti_sgc @@ -200,12 +215,6 @@ file arch/hp700/gsc/com_harmony.c com_harmony #attach myri at pci #file dev/pci/myri.c myri -# -# PC Keyboard controller (ps2) -# - -#include "dev/pckbc/files.pckbc" - # # Non-device files # diff --git a/sys/arch/hp700/dev/com_dino.c b/sys/arch/hp700/dev/com_dino.c new file mode 100644 index 000000000000..355384de5ca2 --- /dev/null +++ b/sys/arch/hp700/dev/com_dino.c @@ -0,0 +1,126 @@ +/* $OpenBSD: com_dino.c,v 1.1 2004/02/13 20:39:31 mickey Exp $ */ + +/* + * Copyright (c) 2004 Michael Shalayeff + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF MIND, + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +void *dino_intr_establish(void *sc, int irq, int pri, + int (*handler)(void *v), void *arg); + +#define COM_DINO_FREQ 7272700 + +struct com_dino_softc { + struct com_softc sc_com; /* real "com" softc */ + void *sc_ih; /* interrupt handler */ +}; + +struct com_dino_regs { + u_int8_t reset; + u_int8_t pad0[3]; + u_int8_t test; +#define COM_DINO_PAR_LOOP 0x01 +#define COM_DINO_CLK_SEL 0x02 + u_int8_t pad1[3]; + u_int32_t iodc; + u_int8_t pad2[0x54]; + u_int8_t dither; +}; + +int com_dino_match(struct device *, struct cfdata *, void *); +void com_dino_attach(struct device *, struct device *, void *); + +CFATTACH_DECL(com_dino, sizeof(struct com_dino_softc), com_dino_match, + com_dino_attach, NULL, NULL); + +int +com_dino_match(parent, match, aux) + struct device *parent; + struct cfdata *match; + void *aux; +{ + struct confargs *ca = aux; + + if (ca->ca_type.iodc_type != HPPA_TYPE_FIO || + ca->ca_type.iodc_sv_model != HPPA_FIO_GRS232) + return (0); + + return (1); + /* HOZER comprobe1(ca->ca_iot, ca->ca_hpa + IOMOD_DEVOFFSET); */ +} + +void +com_dino_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct com_softc *sc = (void *)self; + struct com_dino_softc *sc_dino = (void *)self; + struct confargs *ca = aux; + struct com_dino_regs *regs = (struct com_dino_regs *)ca->ca_hpa; + + sc->sc_iot = ca->ca_iot; + sc->sc_iobase = (bus_addr_t)ca->ca_hpa + IOMOD_DEVOFFSET; + +#ifdef work_in_progress + if (sc->sc_iobase == CONADDR) + sc->sc_ioh = comconsioh; + else +#endif + if (bus_space_map(sc->sc_iot, sc->sc_iobase, COM_NPORTS, + 0, &sc->sc_ioh)) { + printf(": cannot map io space\n"); + return; + } + +#ifdef work_in_progress + if (sc->sc_iobase != CONADDR) { + /* regs->reset = 0xd0; + DELAY(1000); */ + } +#endif + + /* select clock freq */ + regs->test = COM_DINO_CLK_SEL; + sc->sc_frequency = COM_DINO_FREQ; + + com_attach_subr(sc); + + sc_dino->sc_ih = dino_intr_establish(parent, ca->ca_irq, IPL_TTY, + comintr, sc); +} diff --git a/sys/arch/hp700/dev/dino.c b/sys/arch/hp700/dev/dino.c new file mode 100644 index 000000000000..74770505c294 --- /dev/null +++ b/sys/arch/hp700/dev/dino.c @@ -0,0 +1,1697 @@ +/* $OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $ */ + +/* + * Copyright (c) 2003 Michael Shalayeff + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* #include "cardbus.h" */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#if NCARDBUS > 0 +#include +#endif + +#include +#include +#include + +#define DINO_MEM_CHUNK 0x800000 + +/* from machdep.c */ +extern struct extent *hp700_io_extent; + +struct dino_regs { + u_int32_t pad0; /* 0x000 */ + u_int32_t iar0; /* 0x004 rw intr addr reg 0 */ + u_int32_t iodc; /* 0x008 rw iodc data/addr */ + u_int32_t irr0; /* 0x00c r intr req reg 0 */ + u_int32_t iar1; /* 0x010 rw intr addr reg 1 */ + u_int32_t irr1; /* 0x014 r intr req reg 1 */ + u_int32_t imr; /* 0x018 rw intr mask reg */ + u_int32_t ipr; /* 0x01c rw intr pending reg */ + u_int32_t toc_addr; /* 0x020 rw TOC addr reg */ + u_int32_t icr; /* 0x024 rw intr control reg */ + u_int32_t ilr; /* 0x028 r intr level reg */ + u_int32_t pad1; /* 0x02c */ + u_int32_t io_command; /* 0x030 w command register */ + u_int32_t io_status; /* 0x034 r status register */ + u_int32_t io_control; /* 0x038 rw control register */ + u_int32_t pad2; /* 0x03c AUX registers follow */ + u_int32_t io_gsc_err_addr;/* 0x040 GSC error address */ + u_int32_t io_err_info; /* 0x044 error info register */ + u_int32_t io_pci_err_addr;/* 0x048 PCI error address */ + u_int32_t pad3[4]; /* 0x04c */ + u_int32_t io_fbb_en; /* 0x05c fast back2back enable reg */ + u_int32_t io_addr_en; /* 0x060 address enable reg */ + u_int32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */ + u_int32_t pci_conf_data; /* 0x068 PCI conf data reg */ + u_int32_t pci_io_data; /* 0x06c PCI io data reg */ + u_int32_t pci_mem_data; /* 0x070 PCI memory data reg */ + u_int32_t pad4[0x740/4]; /* 0x074 */ + u_int32_t gsc2x_config; /* 0x7b4 GSC2X config reg */ + u_int32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */ + u_int32_t gmask; /* 0x800 GSC arbitration mask */ + u_int32_t pamr; /* 0x804 PCI arbitration mask */ + u_int32_t papr; /* 0x808 PCI arbitration priority */ + u_int32_t damode; /* 0x80c PCI arbitration mode */ + u_int32_t pcicmd; /* 0x810 PCI command register */ + u_int32_t pcists; /* 0x814 PCI status register */ + u_int32_t pad6; /* 0x818 */ + u_int32_t mltim; /* 0x81c PCI master latency timer */ + u_int32_t brdg_feat; /* 0x820 PCI bridge feature enable */ + u_int32_t pciror; /* 0x824 PCI read optimization reg */ + u_int32_t pciwor; /* 0x828 PCI write optimization reg */ + u_int32_t pad7; /* 0x82c */ + u_int32_t tltim; /* 0x830 PCI target latency reg */ +}; + +struct dino_softc { + struct device sc_dv; + + int sc_ver; + void *sc_ih; + struct hp700_int_reg sc_int_reg; + bus_space_tag_t sc_bt; + bus_space_handle_t sc_bh; + bus_space_handle_t sc_memh; + bus_dma_tag_t sc_dmat; + volatile struct dino_regs *sc_regs; + + struct hppa_pci_chipset_tag sc_pc; + struct hppa_bus_space_tag sc_iot; + char sc_ioexname[20]; + struct extent *sc_ioex; + struct hppa_bus_space_tag sc_memt; + int sc_memrefcount[30]; + struct hppa_bus_dma_tag sc_dmatag; +}; + +int dinomatch(struct device *, struct cfdata *, void *); +void dinoattach(struct device *, struct device *, void *); + +CFATTACH_DECL(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL, + NULL); + + +void dino_attach_hook(struct device *, struct device *, + struct pcibus_attach_args *); +int dino_maxdevs(void *, int); +pcitag_t dino_make_tag(void *, int, int, int); +void dino_decompose_tag(void *, pcitag_t, int *, int *, int *); +pcireg_t dino_conf_read(void *, pcitag_t, int); +void dino_conf_write(void *, pcitag_t, int, pcireg_t); +int dino_intr_map(struct pci_attach_args *, pci_intr_handle_t *); +const char *dino_intr_string(void *, pci_intr_handle_t); +void *dino_intr_establish(void *, pci_intr_handle_t, int, + int (*handler)(void *), void *); +void dino_intr_disestablish(void *, void *); +void *dino_alloc_parent(struct device *, struct pci_attach_args *, int); +int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); +int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); +int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t, + bus_space_handle_t *); +int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, + bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); +int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, + bus_size_t, int, bus_addr_t *, bus_space_handle_t *); +void dino_unmap(void *, bus_space_handle_t, bus_size_t); +void dino_free(void *, bus_space_handle_t, bus_size_t); +void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); +void *dino_vaddr(void *, bus_space_handle_t); +u_int8_t dino_r1(void *, bus_space_handle_t, bus_size_t); +u_int16_t dino_r2(void *, bus_space_handle_t, bus_size_t); +u_int32_t dino_r4(void *, bus_space_handle_t, bus_size_t); +u_int64_t dino_r8(void *, bus_space_handle_t, bus_size_t); +void dino_w1(void *, bus_space_handle_t, bus_size_t, u_int8_t); +void dino_w2(void *, bus_space_handle_t, bus_size_t, u_int16_t); +void dino_w4(void *, bus_space_handle_t, bus_size_t, u_int32_t); +void dino_w8(void *, bus_space_handle_t, bus_size_t, u_int64_t); +void dino_rm_1(void *, bus_space_handle_t, bus_size_t, u_int8_t *, bus_size_t); +void dino_rm_2(void *, bus_space_handle_t, bus_size_t, u_int16_t *, bus_size_t); +void dino_rm_4(void *, bus_space_handle_t, bus_size_t, u_int32_t *, bus_size_t); +void dino_rm_8(void *, bus_space_handle_t, bus_size_t, u_int64_t *, bus_size_t); +void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, + bus_size_t); +void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const u_int16_t *, + bus_size_t); +void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const u_int32_t *, + bus_size_t); +void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const u_int64_t *, + bus_size_t); +void dino_sm_1(void *, bus_space_handle_t, bus_size_t, u_int8_t, bus_size_t); +void dino_sm_2(void *, bus_space_handle_t, bus_size_t, u_int16_t, bus_size_t); +void dino_sm_4(void *, bus_space_handle_t, bus_size_t, u_int32_t, bus_size_t); +void dino_sm_8(void *, bus_space_handle_t, bus_size_t, u_int64_t, bus_size_t); +void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, u_int16_t *, + bus_size_t); +void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, u_int32_t *, + bus_size_t); +void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, u_int64_t *, + bus_size_t); +void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const u_int16_t *, + bus_size_t); +void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const u_int32_t *, + bus_size_t); +void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const u_int64_t *, + bus_size_t); +void dino_rr_1(void *, bus_space_handle_t, bus_size_t, u_int8_t *, bus_size_t); +void dino_rr_2(void *, bus_space_handle_t, bus_size_t, u_int16_t *, bus_size_t); +void dino_rr_4(void *, bus_space_handle_t, bus_size_t, u_int32_t *, bus_size_t); +void dino_rr_8(void *, bus_space_handle_t, bus_size_t, u_int64_t *, bus_size_t); +void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, + bus_size_t); +void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const u_int16_t *, + bus_size_t); +void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const u_int32_t *, + bus_size_t); +void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const u_int64_t *, + bus_size_t); +void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, u_int16_t *, + bus_size_t); +void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, u_int32_t *, + bus_size_t); +void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, u_int64_t *, + bus_size_t); +void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const u_int16_t *, + bus_size_t); +void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const u_int32_t *, + bus_size_t); +void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const u_int64_t *, + bus_size_t); +void dino_sr_1(void *, bus_space_handle_t, bus_size_t, u_int8_t, bus_size_t); +void dino_sr_2(void *, bus_space_handle_t, bus_size_t, u_int16_t, bus_size_t); +void dino_sr_4(void *, bus_space_handle_t, bus_size_t, u_int32_t, bus_size_t); +void dino_sr_8(void *, bus_space_handle_t, bus_size_t, u_int64_t, bus_size_t); +void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, + bus_size_t, bus_size_t); +void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, + bus_size_t, bus_size_t); +void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, + bus_size_t, bus_size_t); +void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, + bus_size_t, bus_size_t); +int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int, + bus_dmamap_t *); +void dino_dmamap_destroy(void *, bus_dmamap_t); +int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *, + int); +int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int); +int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int); +int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int, + bus_size_t, int); +void dino_dmamap_unload(void *, bus_dmamap_t); +void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int); +int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t, + bus_dma_segment_t *, int, int *, int); +void dino_dmamem_free(void *, bus_dma_segment_t *, int); +int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, caddr_t *, int); +void dino_dmamem_unmap(void *, caddr_t, size_t); +paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int); +int dinoprint(void *, const char *); + + +void +dino_attach_hook(struct device *parent, struct device *self, + struct pcibus_attach_args *pba) +{ + struct dino_softc *sc = pba->pba_pc->_cookie; + int f, d; + pcitag_t t; + pcireg_t data; + + /* + * The firmware enables only devices that are needed for booting. + * So other devices will fail to map PCI MEM / IO when they attach. + * Therefore we walk the bus to simply enable everything. + */ + for (d = 0; d < 32; d++) { + t = dino_make_tag( sc, 0, d, 0); + if (t != -1 && dino_conf_read(sc, t, 0) != 0xffffffff) { + for (f = 0; f < 8; f++) { + t = dino_make_tag(sc, 0, d, f); + if (dino_conf_read(sc, t, 0) != 0xffffffff) { + data = dino_conf_read(sc, t, + PCI_COMMAND_STATUS_REG); + dino_conf_write(sc, t, + PCI_COMMAND_STATUS_REG, + PCI_COMMAND_IO_ENABLE | + PCI_COMMAND_MEM_ENABLE | + PCI_COMMAND_MASTER_ENABLE | data); + } + } + } + } +} + +int +dino_maxdevs(void *v, int bus) +{ + return 32; +} + +pcitag_t +dino_make_tag(void *v, int bus, int dev, int func) +{ + if (bus > 255 || dev > 31 || func > 7) + panic("dino_make_tag: bad request"); + + return (bus << 16) | (dev << 11) | (func << 8); +} + +void +dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func) +{ + *bus = (tag >> 16) & 0xff; + *dev = (tag >> 11) & 0x1f; + *func= (tag >> 8) & 0x07; +} + +pcireg_t +dino_conf_read(void *v, pcitag_t tag, int reg) +{ + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + pcireg_t data; + + r->pci_addr = tag | reg; + data = r->pci_conf_data; + return le32toh(data); +} + +void +dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) +{ + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + pcireg_t data1; + + /* fix coalescing config writes errata by interleaving w/ a read */ + r->pci_addr = tag | PCI_ID_REG; + data1 = r->pci_conf_data; + + r->pci_addr = tag | reg; + r->pci_conf_data = htole32(data); + + r->pci_addr = tag | PCI_ID_REG; + data1 = r->pci_conf_data; +} + +int +dino_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) +{ + pci_chipset_tag_t pc = pa->pa_pc; + pcitag_t tag = pa->pa_tag; + pcireg_t reg; + + reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); + *ihp = PCI_INTERRUPT_LINE(reg); + return *ihp < 0; +} + +const char * +dino_intr_string(void *v, pci_intr_handle_t ih) +{ + static char buf[32]; + + snprintf(buf, 32, "irq %ld", ih); + return buf; +} + +extern int cold; + + +void * +dino_intr_establish(void *v, pci_intr_handle_t ih, + int pri, int (*handler)(void *), void *arg) +{ + struct dino_softc *sc = v; + + return hp700_intr_establish(&sc->sc_dv, pri, handler, arg, + &sc->sc_int_reg, ih); +} + +void +dino_intr_disestablish(void *v, void *cookie) +{ + panic("There is no hp700_intr_disestablish()!"); +} + + +#if NCARDBUS > 0 +void * +dino_alloc_parent(struct device *self, struct pci_attach_args *pa, int io) +{ + struct dino_softc *sc = pa->pa_pc->_cookie; + struct extent *ex; + bus_space_tag_t tag; + bus_addr_t start; + bus_size_t size; + + if (io) { + ex = sc->sc_ioex; + tag = pa->pa_iot; + start = 0xa000; + size = 0x1000; + } else { + ex = hp700_io_extent; + tag = pa->pa_memt; + start = ex->ex_start; /* XXX or 0xf0800000? */ + size = DINO_MEM_CHUNK; + } + + if (extent_alloc_subregion(ex, start, ex->ex_end, size, size, + EX_NOBOUNDARY, EX_NOWAIT, &start)) + return NULL; + extent_free(ex, start, size, EX_NOWAIT); + return rbus_new_root_share(tag, ex, start, size, start); +} +#endif + +int +dino_iomap(void *v, bus_addr_t bpa, bus_size_t size, + int flags, bus_space_handle_t *bshp) +{ + struct dino_softc *sc = v; + int error; + + if (!(flags & BUS_SPACE_MAP_NOEXTENT) && + (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT))) + return error; + + if (bshp) + *bshp = bpa; + + return 0; +} + +int +dino_memmap(void *v, bus_addr_t bpa, bus_size_t size, + int flags, bus_space_handle_t *bshp) +{ + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + u_int32_t reg; + int error; + + reg = r->io_addr_en; + reg |= 1 << ((bpa >> 23) & 0x1f); +#ifdef DEBUG + if (reg & 0x80000001) + panic("mapping outside the mem extent range"); +#endif + if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp))) + return error; + ++sc->sc_memrefcount[((bpa >> 23) & 0x1f)]; + /* map into the upper bus space, if not yet mapped this 8M */ + if (reg != r->io_addr_en) + r->io_addr_en = reg; + return 0; +} + +int +dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, + bus_size_t size, bus_space_handle_t *nbshp) +{ + *nbshp = bsh + offset; + return 0; +} + +int +dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, + bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, + bus_space_handle_t *bshp) +{ + struct dino_softc *sc = v; + struct extent *ex = sc->sc_ioex; + bus_addr_t bpa; + int error; + + if (rstart < ex->ex_start || rend > ex->ex_end) + panic("dino_ioalloc: bad region start/end"); + + if ((error = extent_alloc_subregion(ex, rstart, rend, size, + align, boundary, EX_NOWAIT, &bpa))) + return error; + + if (addrp) + *addrp = bpa; + if (bshp) + *bshp = bpa; + + return 0; +} + +int +dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, + bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, + bus_space_handle_t *bshp) +{ + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + u_int32_t reg; + int i, error; + + /* + * Allow allocation only when PCI MEM is already maped. + * Needed to avoid allocation of I/O space used by devices that + * have no driver in the current kernel. + * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only. + */ + reg = r->io_addr_en; + if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0) + return -1; + /* Find used PCI MEM and narrow allocateble region down to it. */ + for (i = 1; i < 31; i++) + if ((reg & 1 << i) != 0) { + rstart = 0xf0000000 | i << 23; + rend = (0xf0000000 | (i + 1) << 23) - 1; + break; + } + if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align, + boundary, flags, addrp, bshp))) + return error; + ++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)]; + return 0; +} + +void +dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size) +{ + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + if (bsh & 0xf0000000) { + bus_space_unmap(sc->sc_bt, bsh, size); + if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0) + /* Unmap the upper PCI MEM space. */ + r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f)); + } else { + /* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */ + if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT)) + printf("dino_unmap: ps 0x%lx, size 0x%lx\n" + "dino_unmap: can't free region\n", bsh, size); + } +} + +void +dino_free(void *v, bus_space_handle_t bh, bus_size_t size) +{ + /* should be enough */ + dino_unmap(v, bh, size); +} + +void +dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op) +{ + sync_caches(); +} + +void* +dino_vaddr(void *v, bus_space_handle_t h) +{ + struct dino_softc *sc = v; + + return bus_space_vaddr(sc->sc_bt, h); +} + +u_int8_t +dino_r1(void *v, bus_space_handle_t h, bus_size_t o) +{ + h += o; + if (h & 0xf0000000) + return *(volatile u_int8_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + return *((volatile u_int8_t *)&r->pci_io_data + (h & 3)); + } +} + +u_int16_t +dino_r2(void *v, bus_space_handle_t h, bus_size_t o) +{ + volatile u_int16_t *p; + volatile u_int16_t d; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int16_t *)h; + d = le16toh(*p); + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + d = le16toh(*p); + } + + return d; +} + +u_int32_t +dino_r4(void *v, bus_space_handle_t h, bus_size_t o) +{ + u_int32_t data; + + h += o; + if (h & 0xf0000000) + data = *(volatile u_int32_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h; + data = r->pci_io_data; + } + + return le32toh(data); +} + +u_int64_t +dino_r8(void *v, bus_space_handle_t h, bus_size_t o) +{ + h += o; + if (h & 0xf0000000) + return *(volatile u_int64_t *)h; + else + panic("dino_r8: not implemented"); +} + +void +dino_w1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t vv) +{ + h += o; + if (h & 0xf0000000) + *(volatile u_int8_t *)h = vv; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + *((volatile u_int8_t *)&r->pci_io_data + (h & 3)) = vv; + } +} + +void +dino_w2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t vv) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int16_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + } + + *p = htole16(vv); +} + +void +dino_w4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t vv) +{ + h += o; + vv = htole32(vv); + if (h & 0xf0000000) + *(volatile u_int32_t *)h = vv; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h; + r->pci_io_data = vv; + } +} + +void +dino_w8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t vv) +{ + h += o; + if (h & 0xf0000000) + *(volatile u_int64_t *)h = vv; + else + panic("dino_w8: not implemented"); +} + + +void +dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t *a, bus_size_t c) +{ + volatile u_int8_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int8_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); + } + + while (c--) + *a++ = *p; +} + +void +dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t *a, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int16_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + } + + while (c--) + *a++ = le16toh(*p); +} + +void +dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t *a, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int32_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h; + p = (volatile u_int32_t *)&r->pci_io_data; + } + + while (c--) + *a++ = le32toh(*p); +} + +void +dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t *a, bus_size_t c) +{ + panic("dino_rm_8: not implemented"); +} + +void +dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const u_int8_t *a, bus_size_t c) +{ + volatile u_int8_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int8_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); + } + + while (c--) + *p = *a++; +} + +void +dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const u_int16_t *a, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int16_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + } + + while (c--) + *p = htole16(*a++); +} + +void +dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const u_int32_t *a, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int32_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h; + p = (volatile u_int32_t *)&r->pci_io_data; + } + + while (c--) + *p = htole32(*a++); +} + +void +dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const u_int64_t *a, bus_size_t c) +{ + panic("dino_wm_8: not implemented"); +} + +void +dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t vv, bus_size_t c) +{ + volatile u_int8_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int8_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); + } + + while (c--) + *p = vv; +} + +void +dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t vv, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int16_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + } + + while (c--) + *p = htole16(vv); +} + +void +dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t vv, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int32_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h; + p = (volatile u_int32_t *)&r->pci_io_data; + } + + while (c--) + *p = htole32(vv); +} + +void +dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t vv, bus_size_t c) +{ + panic("dino_sm_8: not implemented"); +} + +void +dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o, + u_int16_t *a, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int16_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + } + + while (c--) + *a++ = *p; +} + +void +dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o, + u_int32_t *a, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int32_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h; + p = (volatile u_int32_t *)&r->pci_io_data; + } + + while (c--) + *a++ = *p; +} + +void +dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o, + u_int64_t *a, bus_size_t c) +{ + panic("dino_rrm_8: not implemented"); +} + +void +dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o, + const u_int16_t *a, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int16_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + } + + while (c--) + *p = *a++; +} + +void +dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o, + const u_int32_t *a, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) + p = (volatile u_int32_t *)h; + else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h; + p = (volatile u_int32_t *)&r->pci_io_data; + } + + while (c--) + *p = *a++; +} + +void +dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o, + const u_int64_t *a, bus_size_t c) +{ + panic("dino_wrm_8: not implemented"); +} + +void +dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t *a, bus_size_t c) +{ + volatile u_int8_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int8_t *)h; + while (c--) + *a++ = *p++; + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + while (c--) { + p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); + *a++ = *p; + if (!(++h & 3)) + r->pci_addr = h; + } + } +} + +void +dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t *a, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int16_t *)h; + while (c--) + *a++ = le16toh(*p++); + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + while (c--) { + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + *a++ = le16toh(*p); + h += 2; + if (!(h & 2)) + r->pci_addr = h; + } + } +} + +void +dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t *a, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int32_t *)h; + while (c--) + *a++ = le32toh(*p++); + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + for (; c--; h += 4) { + r->pci_addr = h; + *a++ = le32toh(r->pci_io_data); + } + } +} + +void +dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t *a, bus_size_t c) +{ + panic("dino_rr_8: not implemented"); +} + +void +dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const u_int8_t *a, bus_size_t c) +{ + volatile u_int8_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int8_t *)h; + while (c--) + *p++ = *a++; + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + while (c--) { + p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); + *p = *a++; + if (!(++h & 3)) + r->pci_addr = h; + } + } +} + +void +dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const u_int16_t *a, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int16_t *)h; + while (c--) + *p++ = htole16(*a++); + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + while (c--) { + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + *p = htole16(*a++); + h += 2; + if (!(h & 2)) + r->pci_addr = h; + } + } +} + +void +dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const u_int32_t *a, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int32_t *)h; + while (c--) + *p++ = htole32(*a++); + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + for (; c--; h += 4) { + r->pci_addr = h; + r->pci_io_data = htole32(*a++); + } + } +} + +void +dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const u_int64_t *a, bus_size_t c) +{ + panic("dino_wr_8: not implemented"); +} + +void +dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o, + u_int16_t *a, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int16_t *)h; + while (c--) + *a++ = *p++; + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + while (c--) { + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + *a++ = *p; + h += 2; + if (!(h & 2)) + r->pci_addr = h; + } + } +} + +void +dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o, + u_int32_t *a, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int32_t *)h; + while (c--) + *a++ = *p++; + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + for (; c--; h += 4) { + r->pci_addr = h; + *a++ = r->pci_io_data; + } + } +} + +void +dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o, + u_int64_t *a, bus_size_t c) +{ + panic("dino_rrr_8: not implemented"); +} + +void +dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o, + const u_int16_t *a, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int16_t *)h; + while (c--) + *p++ = *a++; + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + while (c--) { + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + *p = *a++; + h += 2; + if (!(h & 2)) + r->pci_addr = h; + } + } +} + +void +dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o, + const u_int32_t *a, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int32_t *)h; + while (c--) + *p++ = *a++; + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + for (; c--; h += 4) { + r->pci_addr = h; + r->pci_io_data = *a++; + } + } +} + +void +dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o, + const u_int64_t *a, bus_size_t c) +{ + panic("dino_wrr_8: not implemented"); +} + +void +dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t vv, bus_size_t c) +{ + volatile u_int8_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int8_t *)h; + while (c--) + *p++ = vv; + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + while (c--) { + p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); + *p = vv; + if (!(++h & 3)) + r->pci_addr = h; + } + } +} + +void +dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t vv, bus_size_t c) +{ + volatile u_int16_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int16_t *)h; + while (c--) + *p++ = htole16(vv); + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + r->pci_addr = h & ~3; + while (c--) { + p = (volatile u_int16_t *)&r->pci_io_data; + if (h & 2) + p++; + *p = htole16(vv); + h += 2; + if (!(h & 2)) + r->pci_addr = h; + } + } +} + +void +dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t vv, bus_size_t c) +{ + volatile u_int32_t *p; + + h += o; + if (h & 0xf0000000) { + p = (volatile u_int32_t *)h; + while (c--) + *p++ = htole32(vv); + } else { + struct dino_softc *sc = v; + volatile struct dino_regs *r = sc->sc_regs; + + for (; c--; h += 4) { + r->pci_addr = h; + r->pci_io_data = htole32(vv); + } + } +} + +void +dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t vv, bus_size_t c) +{ + panic("dino_sr_8: not implemented"); +} + +void +dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1, + bus_space_handle_t h2, bus_size_t o2, bus_size_t c) +{ + while (c--) + dino_w1(v, h1, o1++, dino_r1(v, h2, o2++)); +} + +void +dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1, + bus_space_handle_t h2, bus_size_t o2, bus_size_t c) +{ + while (c--) { + dino_w2(v, h1, o1, dino_r2(v, h2, o2)); + o1 += 2; + o2 += 2; + } +} + +void +dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1, + bus_space_handle_t h2, bus_size_t o2, bus_size_t c) +{ + while (c--) { + dino_w4(v, h1, o1, dino_r4(v, h2, o2)); + o1 += 4; + o2 += 4; + } +} + +void +dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1, + bus_space_handle_t h2, bus_size_t o2, bus_size_t c) +{ + while (c--) { + dino_w8(v, h1, o1, dino_r8(v, h2, o2)); + o1 += 8; + o2 += 8; + } +} + + +const struct hppa_bus_space_tag dino_iomemt = { + NULL, + + NULL, dino_unmap, dino_subregion, NULL, dino_free, + dino_barrier, dino_vaddr, + dino_r1, dino_r2, dino_r4, dino_r8, + dino_w1, dino_w2, dino_w4, dino_w8, + dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8, + dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8, + dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8, + dino_rrm_2, dino_rrm_4, dino_rrm_8, + dino_wrm_2, dino_wrm_4, dino_wrm_8, + dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8, + dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8, + dino_rrr_2, dino_rrr_4, dino_rrr_8, + dino_wrr_2, dino_wrr_4, dino_wrr_8, + dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8, + dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8 +}; + +int +dino_dmamap_create(void *v, bus_size_t size, int nsegments, + bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) +{ + struct dino_softc *sc = v; + + /* TODO check the addresses, boundary, enable dma */ + + return bus_dmamap_create(sc->sc_dmat, size, nsegments, + maxsegsz, boundary, flags, dmamp); +} + +void +dino_dmamap_destroy(void *v, bus_dmamap_t map) +{ + struct dino_softc *sc = v; + + bus_dmamap_destroy(sc->sc_dmat, map); +} + +int +dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size, + struct proc *p, int flags) +{ + struct dino_softc *sc = v; + + return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags); +} + +int +dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags) +{ + struct dino_softc *sc = v; + + return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags); +} + +int +dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags) +{ + struct dino_softc *sc = v; + + return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags); +} + +int +dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs, + int nsegs, bus_size_t size, int flags) +{ + struct dino_softc *sc = v; + + return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags); +} + +void +dino_dmamap_unload(void *v, bus_dmamap_t map) +{ + struct dino_softc *sc = v; + + bus_dmamap_unload(sc->sc_dmat, map); +} + +void +dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off, + bus_size_t len, int ops) +{ + struct dino_softc *sc = v; + + return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops); +} + +int +dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment, + bus_size_t boundary, bus_dma_segment_t *segs, + int nsegs, int *rsegs, int flags) +{ + struct dino_softc *sc = v; + + return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary, + segs, nsegs, rsegs, flags); +} + +void +dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs) +{ + struct dino_softc *sc = v; + + bus_dmamem_free(sc->sc_dmat, segs, nsegs); +} + +int +dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size, + caddr_t *kvap, int flags) +{ + struct dino_softc *sc = v; + + return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags); +} + +void +dino_dmamem_unmap(void *v, caddr_t kva, size_t size) +{ + struct dino_softc *sc = v; + + bus_dmamem_unmap(sc->sc_dmat, kva, size); +} + +paddr_t +dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off, + int prot, int flags) +{ + struct dino_softc *sc = v; + + return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags); +} + +const struct hppa_bus_dma_tag dino_dmat = { + NULL, + dino_dmamap_create, dino_dmamap_destroy, + dino_dmamap_load, dino_dmamap_load_mbuf, + dino_dmamap_load_uio, dino_dmamap_load_raw, + dino_dmamap_unload, dino_dmamap_sync, + + dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map, + dino_dmamem_unmap, dino_dmamem_mmap +}; + +const struct hppa_pci_chipset_tag dino_pc = { + NULL, + dino_attach_hook, dino_maxdevs, dino_make_tag, dino_decompose_tag, + dino_conf_read, dino_conf_write, + dino_intr_map, dino_intr_string, + dino_intr_establish, dino_intr_disestablish, +#if NCARDBUS > 0 + dino_alloc_parent +#else + NULL +#endif +}; + +int +dinoprint(void *aux, const char *pnp) +{ + struct pcibus_attach_args *pba = aux; + + if (pnp) + printf("%s at %s\n", pba->pba_busname, pnp); + return UNCONF; +} + +int +dinomatch(parent, cfdata, aux) + struct device *parent; + struct cfdata *cfdata; + void *aux; +{ + struct confargs *ca = aux; + + /* there will be only one */ + if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE || + ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO) + return 0; + + /* Make sure we have an IRQ. */ + if (ca->ca_irq == HP700CF_IRQ_UNDEF) { + ca->ca_irq = hp700_intr_allocate_bit(&int_reg_cpu); + if (ca->ca_irq == HP700CF_IRQ_UNDEF) { + aprint_normal("dinomatch: Can't allocate IRQ\n"); + return 0; + } + } + + return 1; +} + +void +dinoattach(parent, self, aux) + struct device *parent; + struct device *self; + void *aux; +{ + struct dino_softc *sc = (struct dino_softc *)self; + struct confargs *ca = (struct confargs *)aux; + struct pcibus_attach_args pba; + volatile struct dino_regs *r; + const char *p; + u_int data; + int s, ver; + + sc->sc_bt = ca->ca_iot; + sc->sc_dmat = ca->ca_dmatag; + if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) { + printf(": can't map space\n"); + return; + } + + sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh; +#ifdef trust_the_firmware_to_proper_initialize_everything + r->io_addr_en = 0; + r->io_control = 0x80; + r->pamr = 0; + r->papr = 0; + r->io_fbb_en |= 1; + r->damode = 0; + r->gmask &= ~1; /* allow GSC bus req */ + r->pciror = 0; + r->pciwor = 0; + r->brdg_feat = 0xc0000000; +#endif + + snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname), + "%s_io", sc->sc_dv.dv_xname); + if ((sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff, + M_DEVBUF, NULL, 0, EX_NOWAIT | EX_MALLOCOK)) == NULL) { + printf(": cannot allocate I/O extent map\n"); + bus_space_unmap(sc->sc_bt, sc->sc_bh, PAGE_SIZE); + return; + } + + /* interrupts guts */ + s = splhigh(); + r->icr = 0; + r->imr = ~0; + data = r->irr0; + r->imr = 0; + r->iar0 = cpu_gethpa(0) | (31 - ca->ca_irq); + splx(s); + /* Establish the interrupt register. */ + hp700_intr_reg_establish(&sc->sc_int_reg); + sc->sc_int_reg.int_reg_mask = &r->imr; + sc->sc_int_reg.int_reg_req = &r->irr0; + /* Add the I/O interrupt register. */ + sc->sc_int_reg.int_reg_dev = sc->sc_dv.dv_xname; + sc->sc_ih = hp700_intr_establish(&sc->sc_dv, IPL_NONE, + NULL, &sc->sc_int_reg, &int_reg_cpu, ca->ca_irq); + + /* TODO establish the bus error interrupt */ + + r->iodc = 0; + data = r->iodc; + ver = (ca->ca_type.iodc_model << 4) | + (ca->ca_type.iodc_revision >> 4); + switch (ver) { + case 0x05d: p = "Dino"; /* j2240 */ + case 0x680: p = "Dino"; + switch (data >> 16) { + case 0x6800: ver = 0x20; break; + case 0x6801: ver = 0x21; break; + case 0x6802: ver = 0x30; break; + case 0x6803: ver = 0x31; break; + default: ver = 0x40; break; + } + break; + + case 0x682: p = "Cujo"; + switch (data >> 16) { + case 0x6820: ver = 0x10; break; + case 0x6821: ver = 0x20; break; + default: ver = 0x30; break; + } + break; + + default: p = "Mojo"; + ver = (data >> 16) & 0xff; + break; + } + sc->sc_ver = ver; + printf(": %s V%d.%d\n", p, ver >> 4, ver & 0xf); + + sc->sc_iot = dino_iomemt; + sc->sc_iot.hbt_cookie = sc; + sc->sc_iot.hbt_map = dino_iomap; + sc->sc_iot.hbt_alloc = dino_ioalloc; + sc->sc_memt = dino_iomemt; + sc->sc_memt.hbt_cookie = sc; + sc->sc_memt.hbt_map = dino_memmap; + sc->sc_memt.hbt_alloc = dino_memalloc; + sc->sc_pc = dino_pc; + sc->sc_pc._cookie = sc; + sc->sc_dmatag = dino_dmat; + sc->sc_dmatag._cookie = sc; + +#ifdef no_hardware_to_test_so_leave_it_for_now + /* scan for ps2 kbd/ms, serial, and flying toasters */ + ca->ca_hpamask = -1; + pdc_scanbus(self, ca, MAXMODBUS); +#endif + + pba.pba_busname = "pci"; + pba.pba_iot = &sc->sc_iot; + pba.pba_memt = &sc->sc_memt; + pba.pba_dmat = &sc->sc_dmatag; + pba.pba_pc = &sc->sc_pc; + pba.pba_bus = 0; + pba.pba_bridgetag = NULL; + pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; + config_found(self, &pba, dinoprint); +} diff --git a/sys/arch/hp700/hp700/autoconf.c b/sys/arch/hp700/hp700/autoconf.c index edf722295b9b..5d3f2cbfcf55 100644 --- a/sys/arch/hp700/hp700/autoconf.c +++ b/sys/arch/hp700/hp700/autoconf.c @@ -1,4 +1,4 @@ -/* $NetBSD: autoconf.c,v 1.14 2004/06/15 20:43:41 jkunz Exp $ */ +/* $NetBSD: autoconf.c,v 1.15 2004/07/29 19:10:23 jkunz Exp $ */ /* $OpenBSD: autoconf.c,v 1.15 2001/06/25 00:43:10 mickey Exp $ */ @@ -86,7 +86,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.14 2004/06/15 20:43:41 jkunz Exp $"); +__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.15 2004/07/29 19:10:23 jkunz Exp $"); #include "opt_kgdb.h" #include "opt_useleds.h" @@ -108,6 +108,8 @@ __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.14 2004/06/15 20:43:41 jkunz Exp $"); #include #include +#include + #include #include #include @@ -319,30 +321,90 @@ device_register(struct device *dev, void *aux) if (dev->dv_parent == NULL || dev->dv_parent->dv_parent == NULL) return; pagezero_cookie = hp700_pagezero_map(); - /* Currently only GSC devices are supported. */ -#if NPCI > 0 -#error Root device identification code needs PCI support. -#endif - /* - * The boot device is described in PAGE0->mem_boot. - * The bit PCL_NET_MASK is set in PAGE0->mem_boot.pz_class if it - * is a network interface. All we need to compare in that case is - * the HPA to get the boot device. - * If it is a SCSI device we need the HPA of the controller and - * the SCSI target / lun. Target and lun are stored in the device - * path layer array. When booting from disk / cdrom / tape remember - * the controller of the boot device in boot_device when the HPA - * matches. Later, when SCSI devices are attached, look if the - * SCSI device hangs below the boot controller. If so, look for - * the target and lun of the SCSI device. If they match the layer - * of the boot device path in PAGE0 we found the boot device. + /* Currently only GSC and PCI devices are supported. */ + /* + * The boot device is described in PAGE0->mem_boot. We need to do it + * this way as the MD device path (DP) information in struct confargs + * is only available in hp700 MD devices. So boot_device is used to + * propagate information down the device tree. + * + * If the boot device is a GSC network device all we need to compare + * is the HPA or device path (DP) to get the boot device. + * If the boot device is a SCSI device below a GSC attached SCSI + * controller PAGE0->mem_boot.pz_hpa contains the HPA of the SCSI + * controller. In that case we remember the the pointer to the + * controller's struct dev in boot_device. The SCSI device is located + * later, see below. */ if (strcmp(dev->dv_parent->dv_cfdata->cf_name, "gsc") == 0 && (hppa_hpa_t)PAGE0->mem_boot.pz_hpa == ((struct gsc_attach_args *)aux)->ga_ca.ca_hpa) /* This is (the controller of) the boot device. */ boot_device = dev; - if ((PAGE0->mem_boot.pz_class & PCL_NET_MASK) == 0 + /* + * If the boot device is a PCI device the HPA is the address where the + * firmware has maped the PCI memory of the PCI device. This is quite + * device dependent, so we compare the DP. It encodes the bus routing + * information to the PCI bus bridge in the DP head and the PCI device + * and PCI function in the last two DP components. So we compare the + * head of the DP when a PCI bridge attaches and remember the struct + * dev of the PCI bridge in boot_dev if it machtes. Later, when PCI + * devices are attached, we look if this PCI device hangs below the + * boot PCI bridge. If yes we compare the PCI device and PCI function + * to the DP tail. In case of a network boot we found the boot device + * on a match. In case of a SCSI boot device we have to do the same + * check when SCSI devices are attached like on GSC SCSI controllers. + */ + if (strcmp(dev->dv_cfdata->cf_name, "dino") == 0) { + struct confargs *ca = (struct confargs *)aux; + int i, n; + + for (n = 0 ; ca->ca_dp.dp_bc[n] < 0 ; n++) { + /* Skip unused DP components. */ + } + for (i = 0 ; i < 6 && n < 6 ; i++) { + /* Skip unused DP components... */ + if (PAGE0->mem_boot.pz_dp.dp_bc[i] < 0) + continue; + /* and compare the rest. */ + if (PAGE0->mem_boot.pz_dp.dp_bc[i] + != ca->ca_dp.dp_bc[n]) { + hp700_pagezero_unmap(pagezero_cookie); + return; + } + n++; + } + if (PAGE0->mem_boot.pz_dp.dp_bc[i] != ca->ca_dp.dp_mod) { + hp700_pagezero_unmap(pagezero_cookie); + return; + } + /* This is the PCI host bridge in front of the boot device. */ + boot_device = dev; + } + /* XXX Guesswork. No hardware to test how firmware handles a ppb. */ + if (strcmp(dev->dv_cfdata->cf_name, "ppb") == 0 + && boot_device == dev->dv_parent->dv_parent + && ((struct pci_attach_args*)aux)->pa_device + == PAGE0->mem_boot.pz_dp.dp_bc[3] + && ((struct pci_attach_args*)aux)->pa_function + == PAGE0->mem_boot.pz_dp.dp_bc[4]) + /* This is the PCI - PCI bridge in front of the boot device. */ + boot_device = dev; + if (strcmp(dev->dv_parent->dv_cfdata->cf_name, "pci") == 0 + && boot_device == dev->dv_parent->dv_parent + && ((struct pci_attach_args*)aux)->pa_device + == PAGE0->mem_boot.pz_dp.dp_bc[5] + && ((struct pci_attach_args*)aux)->pa_function + == PAGE0->mem_boot.pz_dp.dp_mod) + /* This is (the controller of) the boot device. */ + boot_device = dev; + /* + * When SCSI devices are attached, we look if the SCSI device hangs + * below the controller remembered in boot_device. If so, we compare + * the SCSI ID and LUN with the DP layer information. If they match + * we found the boot device. + */ + if (strcmp(dev->dv_parent->dv_cfdata->cf_name, "scsibus") == 0 && boot_device == dev->dv_parent->dv_parent && ((struct scsipibus_attach_args *)aux)->sa_periph->periph_target == PAGE0->mem_boot.pz_dp.dp_layers[0] @@ -369,7 +431,7 @@ cpu_rootconf(void) pagezero_cookie = hp700_pagezero_map(); printf("PROM boot device: hpa %p path ", PAGE0->mem_boot.pz_hpa); for (n = 0 ; n < 6 ; n++) { - if (PAGE0->mem_boot.pz_dp.dp_bc[n] > 0) + if (PAGE0->mem_boot.pz_dp.dp_bc[n] >= 0) printf("%d/", PAGE0->mem_boot.pz_dp.dp_bc[n]); } printf("%d dp_layers ", PAGE0->mem_boot.pz_dp.dp_mod); diff --git a/sys/arch/hp700/include/pci_machdep.h b/sys/arch/hp700/include/pci_machdep.h new file mode 100644 index 000000000000..5726ca66e00f --- /dev/null +++ b/sys/arch/hp700/include/pci_machdep.h @@ -0,0 +1,93 @@ +/* $OpenBSD: pci_machdep.h,v 1.1 2003/09/29 19:23:02 mickey Exp $ */ + +/* + * Copyright (c) 2003 Michael Shalayeff + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_PCI_MACHDEP_H_ +#define _MACHINE_PCI_MACHDEP_H_ + +/* + * Types provided to machine-independent PCI code + */ +typedef struct hppa_pci_chipset_tag *pci_chipset_tag_t; +typedef u_long pcitag_t; +typedef u_long pci_intr_handle_t; + +struct pci_attach_args; + +struct hppa_pci_chipset_tag { + void *_cookie; + void (*pc_attach_hook)(struct device *, + struct device *, struct pcibus_attach_args *); + int (*pc_bus_maxdevs)(void *, int); + pcitag_t (*pc_make_tag)(void *, int, int, int); + void (*pc_decompose_tag)(void *, pcitag_t, int *, + int *, int *); + pcireg_t (*pc_conf_read)(void *, pcitag_t, int); + void (*pc_conf_write)(void *, pcitag_t, int, pcireg_t); + + int (*pc_intr_map)(struct pci_attach_args *, + pci_intr_handle_t *); + const char *(*pc_intr_string)(void *, pci_intr_handle_t); + void *(*pc_intr_establish)(void *, pci_intr_handle_t, + int, int (*)(void *), void *); + void (*pc_intr_disestablish)(void *, void *); + + void *(*pc_alloc_parent)(struct device *, + struct pci_attach_args *, int); +}; + +/* + * Functions provided to machine-independent PCI code. + */ +#define pci_attach_hook(p, s, pba) \ + (*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba)) +#define pci_bus_maxdevs(c, b) \ + (*(c)->pc_bus_maxdevs)((c)->_cookie, (b)) +#define pci_make_tag(c, b, d, f) \ + (*(c)->pc_make_tag)((c)->_cookie, (b), (d), (f)) +#define pci_decompose_tag(c, t, bp, dp, fp) \ + (*(c)->pc_decompose_tag)((c)->_cookie, (t), (bp), (dp), (fp)) +#define pci_conf_read(c, t, r) \ + (*(c)->pc_conf_read)((c)->_cookie, (t), (r)) +#define pci_conf_write(c, t, r, v) \ + (*(c)->pc_conf_write)((c)->_cookie, (t), (r), (v)) +#define pci_intr_map(p, ihp) \ + (*(p)->pa_pc->pc_intr_map)((p), (ihp)) +#define pci_intr_line(ih) (ih) +#define pci_intr_string(c, ih) \ + (*(c)->pc_intr_string)((c)->_cookie, (ih)) +#define pci_intr_establish(c, ih, l, h, a) \ + (*(c)->pc_intr_establish)((c)->_cookie, (ih), (l), (h), (a)) +#define pci_intr_disestablish(c, iv) \ + (*(c)->pc_intr_disestablish)((c)->_cookie, (iv)) +#define pci_enumerate_bus(sc, m, p) \ + pci_enumerate_bus_generic((sc), (m), (p)) + +#define pciide_machdep_compat_intr_establish(a, b, c, d, e) (NULL) +#define pciide_machdep_compat_intr_disestablish(a, b) ((void)(a), (void)(b)) + +#endif /* _MACHINE_PCI_MACHDEP_H_ */