Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup. Tested on a RaspberryPi. PL010 not tested.
This commit is contained in:
skrll
parent
128449c491
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File diff suppressed because it is too large
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@ -1,4 +1,4 @@
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/* $NetBSD: plcomreg.h,v 1.3 2012/05/14 19:40:06 skrll Exp $ */
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/* $NetBSD: plcomreg.h,v 1.4 2012/07/25 07:26:17 skrll Exp $ */
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/*-
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* Copyright (c) 2001 ARM Ltd
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@ -52,11 +52,12 @@
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#define PL01X_CR_UARTEN 0x0001 /* Uart enable */
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/* interrupt identification register */
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#define PL010_IIR_IMASK 0x0f
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#define PL010_IIR_RTIS 0x08
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#define PL010_IIR_TIS 0x04
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#define PL010_IIR_RIS 0x02
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#define PL010_IIR_MIS 0x01
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#define PL010_IIR_IMASK \
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(PL010_IIR_RTIS | PL010_IIR_TIS | PL010_IIR_RIS | PL010_IIR_MIS)
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/* line control register */
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#define PL011_LCR_SPS 0x80 /* Stick parity select */
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@ -77,16 +78,18 @@
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/* modem control register */
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#define PL01X_MCR_RTS 0x02 /* Request To Send */
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#define PL01X_MCR_DTR 0x01 /* Data Terminal Ready */
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#define PL011_MCR(mcr) ((mcr) << 10) /* MCR to CR bit values for PL011 */
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/* receive status register */
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#define PL01X_RSR_OE 0x08 /* Overrun Error */
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#define PL01X_RSR_BE 0x04 /* Break */
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#define PL01X_RSR_PE 0x02 /* Parity Error */
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#define PL01X_RSR_FE 0x01 /* Framing Error */
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#define PL01X_RSR_ERROR (PL01X_RSR_OE | PL01X_RSR_BE | PL01X_RSR_PE | PL01X_RSR_FE)
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#define PL01X_RSR_ERROR \
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(PL01X_RSR_OE | PL01X_RSR_BE | PL01X_RSR_PE | PL01X_RSR_FE)
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/* flag register */
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#define PL01X_FR_RI 0x100 /* Ring Indicator */
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#define PL011_FR_RI 0x100 /* Ring Indicator */
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#define PL01X_FR_TXFE 0x080 /* Transmit fifo empty */
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#define PL01X_FR_RXFF 0x040 /* Recive fifo full */
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#define PL01X_FR_TXFF 0x020 /* Transmit fifo full */
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@ -101,6 +104,7 @@
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#define PL01X_MSR_DCD PL01X_FR_DCD
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#define PL01X_MSR_DSR PL01X_FR_DSR
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#define PL01X_MSR_CTS PL01X_FR_CTS
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#define PL011_MSR_RI PL011_FR_RI
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/* All interrupt status/clear registers */
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#define PL011_INT_OE 0x400
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@ -114,6 +118,12 @@
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#define PL011_INT_DCD 0x004
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#define PL011_INT_CTS 0x002
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#define PL011_INT_RIR 0x001
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#define PL011_INT_MSMASK \
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(PL011_INT_DSR | PL011_INT_DCD | PL011_INT_CTS | PL011_INT_RIR)
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#define PL011_INT_ALLMASK \
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(PL011_INT_RT | PL011_INT_TX | PL011_INT_RX | PL011_INT_MSMASK)
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/* DMA control registers */
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#define PL011_DMA_ONERR 0x4
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@ -121,17 +131,27 @@
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#define PL011_DMA_RXE 0x1
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/* Register offsets */
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#define plcom_dr 0x00
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#define plcom_rsr 0x04
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#define plcom_ecr 0x04
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#define plcom_lcr 0x08
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#define plcom_dlbh 0x0c
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#define plcom_dlbl 0x10
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#define plcom_cr 0x14
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#define plcom_fr 0x18
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#define plcom_iir 0x1c
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#define plcom_icr 0x1c
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#define plcom_ilpr 0x20
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#define PL01XCOM_DR 0x00 /* Data Register */
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#define PL01XCOM_RSR 0x04 /* Receive status register */
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#define PL01XCOM_ECR 0x04 /* Error clear register - same as RSR */
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#define PL010COM_LCR 0x08 /* Line Control Register */
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#define PL010COM_DLBH 0x0c
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#define PL010COM_DLBL 0x10
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#define PL010COM_CR 0x14
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#define PL01XCOM_FR 0x18 /* Flag Register */
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#define PL010COM_IIR 0x1c
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#define PL010COM_ICR 0x1c
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#define PL01XCOM_ILPR 0x20 /* IrDA low-power control register */
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#define PL011COM_IBRD 0x24 /* Integer baud rate divisor register */
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#define PL011COM_FBRD 0x28 /* Fractional baud rate divisor register */
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#define PL011COM_LCRH 0x2c /* Line control register */
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#define PL011COM_CR 0x30 /* Control register */
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#define PL011COM_IFLS 0x34 /* Interrupt FIFO level select register */
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#define PL011COM_IMSC 0x38 /* Interrupt mask set/clear register */
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#define PL011COM_RIS 0x3c /* Raw interrupt status register */
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#define PL011COM_MIS 0x40 /* Masked interrupt status register */
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#define PL011COM_ICR 0x44 /* Interrupt clear register register */
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#define PL011COM_DMACR 0x48 /* DMA control register register */
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/* IFPGA specific */
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#define PLCOM_UART_SIZE 0x24
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#define PL010COM_UART_SIZE 0x100
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#define PL011COM_UART_SIZE 0x1000
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@ -1,4 +1,4 @@
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/* $NetBSD: plcomvar.h,v 1.10 2012/05/20 10:28:44 skrll Exp $ */
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/* $NetBSD: plcomvar.h,v 1.11 2012/07/25 07:26:18 skrll Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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@ -44,14 +44,16 @@
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#include <sys/timepps.h>
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#include <sys/simplelock.h>
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int plcomcnattach (bus_space_tag_t, bus_addr_t, int, int, tcflag_t, int);
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struct plcom_instance;
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int plcomcnattach (struct plcom_instance *, int, int, tcflag_t, int);
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void plcomcndetach (void);
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#ifdef KGDB
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int plcom_kgdb_attach (bus_space_tag_t, bus_addr_t, int, int, tcflag_t);
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int plcom_kgdb_attach (struct plcom_instance *, int, int, tcflag_t);
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#endif
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int plcom_is_console (bus_space_tag_t, int, bus_space_handle_t *);
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int plcom_is_console (bus_space_tag_t, bus_addr_t, bus_space_handle_t *);
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/* Hardware flag masks */
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#define PLCOM_HW_NOIEN 0x01
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@ -66,18 +68,43 @@ int plcom_is_console (bus_space_tag_t, int, bus_space_handle_t *);
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/* Buffer size for character buffer */
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#define PLCOM_RING_SIZE 2048
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struct plcom_instance {
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u_int pi_type;
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#define PLCOM_TYPE_PL010 0
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#define PLCOM_TYPE_PL011 1
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uint32_t pi_flags; /* flags for this PLCOM */
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#define PLC_FLAG_USE_DMA 0x0001
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#define PLC_FLAG_32BIT_ACCESS 0x0002
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void *pi_cookie;
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bus_space_tag_t pi_iot;
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bus_space_handle_t pi_ioh;
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bus_addr_t pi_iobase;
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bus_addr_t pi_size;
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struct plcom_registers *pi_regs;
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};
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struct plcomcons_info {
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int rate;
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int frequency;
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int type;
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tcflag_t cflag;
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};
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struct plcom_softc {
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device_t sc_dev;
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void *sc_si;
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struct tty *sc_tty;
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void *sc_si;
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struct callout sc_diag_callout;
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bus_addr_t sc_iounit;
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int sc_frequency;
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int sc_frequency;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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struct plcom_instance sc_pi;
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u_int sc_overflows,
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sc_floods,
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@ -112,12 +139,13 @@ struct plcom_softc {
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sc_rx_ready;
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volatile u_char sc_heldchange;
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volatile u_char sc_msr, sc_msr_delta, sc_msr_mask, sc_mcr,
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sc_mcr_active, sc_lcr, sc_cr, sc_dlbl, sc_dlbh;
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volatile u_int sc_cr, sc_ratel, sc_rateh, sc_imsc;
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volatile u_int sc_msr, sc_msr_delta, sc_msr_mask;
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volatile u_char sc_mcr, sc_mcr_active, sc_lcr;
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u_char sc_mcr_dtr, sc_mcr_rts, sc_msr_cts, sc_msr_dcd;
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u_int sc_fifo;
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/* Support routine to program mcr lines, if present. */
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/* Support routine to program mcr lines for PL010, if present. */
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void (*sc_set_mcr)(void *, int, u_int);
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void *sc_set_mcr_arg;
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@ -139,7 +167,9 @@ struct plcom_softc {
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kmutex_t sc_lock;
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};
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#if 0
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int plcomprobe1 (bus_space_tag_t, bus_space_handle_t);
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#endif
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int plcomintr (void *);
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void plcom_attach_subr (struct plcom_softc *);
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int plcom_detach (device_t, int);
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@ -1,4 +1,4 @@
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/* $NetBSD: ifpgareg.h,v 1.3 2005/12/11 12:17:09 christos Exp $ */
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/* $NetBSD: ifpgareg.h,v 1.4 2012/07/25 07:26:18 skrll Exp $ */
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/*
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* Copyright (c) 2001 ARM Ltd
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@ -32,6 +32,7 @@
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/* System clock defaults. */
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#define IFPGA_UART_CLK 14745600 /* Uart REFCLK freq */
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#define IFPGA_UART_SIZE 0x24
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/*
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* IFPGA registers
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@ -1,4 +1,4 @@
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/* $NetBSD: plcom_ifpga.c,v 1.13 2012/05/20 10:28:44 skrll Exp $ */
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/* $NetBSD: plcom_ifpga.c,v 1.14 2012/07/25 07:26:18 skrll Exp $ */
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/*
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* Copyright (c) 2001 ARM Ltd
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@ -32,7 +32,7 @@
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/* Interface to plcom (PL010) serial driver. */
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: plcom_ifpga.c,v 1.13 2012/05/20 10:28:44 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: plcom_ifpga.c,v 1.14 2012/07/25 07:26:18 skrll Exp $");
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#include <sys/types.h>
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#include <sys/device.h>
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@ -75,24 +75,27 @@ plcom_ifpga_attach(device_t parent, device_t self, void *aux)
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isc->sc_iot = ifa->ifa_iot;
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isc->sc_ioh = ifa->ifa_sc_ioh;
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sc->sc_dev = self;
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sc->sc_iounit = device_unit(sc->sc_dev);
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sc->sc_pi.pi_type = PLCOM_TYPE_PL010;
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sc->sc_pi.pi_iot = ifa->ifa_iot;
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sc->sc_pi.pi_iobase = ifa->ifa_addr;
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sc->sc_pi.pi_size = IFPGA_UART_SIZE;
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sc->sc_frequency = IFPGA_UART_CLK;
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sc->sc_iot = ifa->ifa_iot;
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sc->sc_hwflags = 0;
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sc->sc_swflags = 0;
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sc->sc_set_mcr = plcom_ifpga_set_mcr;
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sc->sc_set_mcr_arg = (void *)isc;
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if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, PLCOM_UART_SIZE, 0,
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&sc->sc_ioh)) {
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if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, IFPGA_UART_SIZE, 0,
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&sc->sc_pi.pi_ioh)) {
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printf("%s: unable to map device\n", device_xname(sc->sc_dev));
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return;
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}
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plcom_attach_subr(sc);
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isc->sc_ih = ifpga_intr_establish(ifa->ifa_irq, IPL_SERIAL, plcomintr,
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sc);
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isc->sc_ih = ifpga_intr_establish(ifa->ifa_irq, IPL_SERIAL,
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plcomintr, sc);
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if (isc->sc_ih == NULL)
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panic("%s: cannot install interrupt handler",
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device_xname(sc->sc_dev));
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@ -1,4 +1,4 @@
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/* $NetBSD: integrator_machdep.c,v 1.68 2011/07/01 20:39:34 dyoung Exp $ */
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/* $NetBSD: integrator_machdep.c,v 1.69 2012/07/25 07:26:18 skrll Exp $ */
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/*
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* Copyright (c) 2001,2002 ARM Ltd
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@ -68,7 +68,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: integrator_machdep.c,v 1.68 2011/07/01 20:39:34 dyoung Exp $");
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__KERNEL_RCSID(0, "$NetBSD: integrator_machdep.c,v 1.69 2012/07/25 07:26:18 skrll Exp $");
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#include "opt_ddb.h"
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#include "opt_pmap_debug.h"
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@ -383,9 +383,6 @@ initarm(void *arg)
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psize_t memsize;
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vm_offset_t physical_freestart;
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vm_offset_t physical_freeend;
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#if NPLCOM > 0 && defined(PLCONSOLE)
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static struct bus_space plcom_bus_space;
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#endif
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/*
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* Heads up ... Setup the CPU / MMU / TLB functions
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@ -402,13 +399,29 @@ initarm(void *arg)
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*/
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if (PLCOMCNUNIT == 0) {
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static struct bus_space plcom_bus_space;
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static struct plcom_instance ifpga_pi0 = {
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.pi_type = PLCOM_TYPE_PL010,
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.pi_iot = &plcom_bus_space,
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.pi_size = IFPGA_UART_SIZE,
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.pi_iobase = 0x0
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};
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ifpga_create_io_bs_tag(&plcom_bus_space, (void*)0xfd600000);
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plcomcnattach(&plcom_bus_space, 0, plcomcnspeed,
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IFPGA_UART_CLK, plcomcnmode, PLCOMCNUNIT);
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plcomcnattach(&ifpga_pi0, plcomcnspeed, IFPGA_UART_CLK,
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plcomcnmode, PLCOMCNUNIT);
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} else if (PLCOMCNUNIT == 1) {
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static struct bus_space plcom_bus_space;
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static struct plcom_instance ifpga_pi1 = {
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.pi_type = PLCOM_TYPE_PL010,
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.pi_iot = &plcom_bus_space,
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.pi_size = IFPGA_UART_SIZE,
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.pi_iobase = 0x0
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};
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ifpga_create_io_bs_tag(&plcom_bus_space, (void*)0xfd700000);
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plcomcnattach(&plcom_bus_space, 0, plcomcnspeed,
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IFPGA_UART_CLK, plcomcnmode, PLCOMCNUNIT);
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plcomcnattach(&ifpga_pi1, plcomcnspeed, IFPGA_UART_CLK,
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plcomcnmode, PLCOMCNUNIT);
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}
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#endif
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@ -788,9 +801,6 @@ void
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consinit(void)
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{
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static int consinit_called = 0;
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#if NPLCOM > 0 && defined(PLCONSOLE)
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static struct bus_space plcom_bus_space;
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#endif
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#if 0
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char *console = CONSDEVNAME;
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#endif
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@ -802,17 +812,35 @@ consinit(void)
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#if NPLCOM > 0 && defined(PLCONSOLE)
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if (PLCOMCNUNIT == 0) {
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static struct bus_space plcom_bus_space;
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static struct plcom_instance ifpga_pi1 = {
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.pi_type = PLCOM_TYPE_PL010,
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.pi_iot = &plcom_bus_space,
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.pi_size = IFPGA_UART_SIZE,
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.pi_iobase = 0x0
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};
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ifpga_create_io_bs_tag(&plcom_bus_space,
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(void*)UART0_BOOT_BASE);
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if (plcomcnattach(&plcom_bus_space, 0, plcomcnspeed,
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IFPGA_UART_CLK, plcomcnmode, PLCOMCNUNIT))
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if (plcomcnattach(&ifpga_pi1, plcomcnspeed, IFPGA_UART_CLK,
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plcomcnmode, PLCOMCNUNIT))
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panic("can't init serial console");
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return;
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} else if (PLCOMCNUNIT == 1) {
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static struct bus_space plcom_bus_space;
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static struct plcom_instance ifpga_pi1 = {
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.pi_type = PLCOM_TYPE_PL010,
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.pi_iot = &plcom_bus_space,
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.pi_size = IFPGA_UART_SIZE,
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.pi_iobase = 0x0
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};
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ifpga_create_io_bs_tag(&plcom_bus_space,
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(void*)UART0_BOOT_BASE);
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if (plcomcnattach(&plcom_bus_space, 0, plcomcnspeed,
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IFPGA_UART_CLK, plcomcnmode, PLCOMCNUNIT))
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if (plcomcnattach(&ifpga_pi1, plcomcnspeed, IFPGA_UART_CLK,
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plcomcnmode, PLCOMCNUNIT))
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panic("can't init serial console");
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return;
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}
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