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Revisit gpio and revisit register file mapping. The additional register files 

are now mapped behind the origional register file.

The gpio channel GPZ is mapped over I2S0 in the separate audio register file
and were both abusively mapped over I2C0 in the main register file!

While here, delay the gpio bootstrap till on attachment. We could hasten it in
the odroid_machdep.c if needed. Also make the gpio code more resilliant and
allow booting correctly without any GPIO bits defined/available.
This commit is contained in:
reinoud 2014-05-14 09:03:09 +00:00
parent 05e3c28794
commit 4bbeac14dd
6 changed files with 269 additions and 209 deletions
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294
sys/arch/arm/samsung/exynos4_reg.h
View File

@ -109,157 +109,163 @@
* elaborate comments to clarify the register offsets use
*/
#define EXYNOS4_CORE_SIZE 0x04000000
#define EXYNOS4_SDRAM_PBASE 0x40000000
/* CORE */
#define EXYNOS4_CORE_SIZE 0x04000000
#define EXYNOS4_SDRAM_PBASE 0x40000000
#define EXYNOS4_SYSREG_OFFSET 0x00010000
#define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */
#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* XXX unknown XXX */
#define EXYNOS4_SYSREG_OFFSET 0x00010000
#define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */
#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* XXX unknown XXX */
#define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* XXX unknown XXX */
#define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */
#define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */
#define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */
#define EXYNOS4_KEYIF_OFFSET 0x000A0000 /* Keypad interface */
#define EXYNOS4_HDMI_CEC_OFFSET 0x000B0000 /* HDMI Consumer Electronic Control */
#define EXYNOS4_TMU_OFFSET 0x000C0000 /* Thermal Managment */
#define EXYNOS4_SECKEY_OFFSET 0x00100000 /* XXX unknown XXX */
#define EXYNOS4_TZPC0_OFFSET 0x00110000 /* ARM Trusted Zone Protection Controller */
#define EXYNOS4_TZPC1_OFFSET 0x00120000
#define EXYNOS4_TZPC2_OFFSET 0x00130000
#define EXYNOS4_TZPC3_OFFSET 0x00140000
#define EXYNOS4_TZPC4_OFFSET 0x00150000
#define EXYNOS4_TZPC5_OFFSET 0x00160000
#define EXYNOS4_INTCOMBINER_OFFSET 0x00440000 /* combines first 32 interrupt sources */
#define EXYNOS4_GIC_CNTR_OFFSET 0x00480000 /* generic interrupt controller offset */
#define EXYNOS4_GIC_DISTRIBUTOR_OFFSET 0x00490000
#define EXYNOS4_AP_C2C_OFFSET 0x00540000 /* Chip 2 Chip XXX doc? XXX */
#define EXYNOS4_CP_C2C_MODEM_OFFSET 0x00580000
#define EXYNOS4_DMC0_OFFSET 0x00600000 /* Dynamic Memory Controller */
#define EXYNOS4_DMC1_OFFSET 0x00610000
#define EXYNOS4_PPMU_DMC_L_OFFSET 0x006A0000 /* event counters XXX ? */
#define EXYNOS4_PPMU_DMC_R_OFFSET 0x006B0000
#define EXYNOS4_PPMU_CPU_OFFSET 0x006C0000
#define EXYNOS4_GPIO_C2C_OFFSET 0x006E0000
#define EXYNOS4_TZASC_LR_OFFSET 0x00700000 /* trust zone access control */
#define EXYNOS4_TZASC_LW_OFFSET 0x00710000
#define EXYNOS4_TZASC_RR_OFFSET 0x00720000
#define EXYNOS4_TZASC_RW_OFFSET 0x00730000
#define EXYNOS4_G2D_ACP_OFFSET 0x00800000 /* 2D graphics engine */
#define EXYNOS4_SSS_OFFSET 0x00830000 /* Security Sub System */
#define EXYNOS4_CORESIGHT_1_OFFSET 0x00880000 /* 1st region */
#define EXYNOS4_CORESIGHT_2_OFFSET 0x00890000 /* 2nd region */
#define EXYNOS4_CORESIGHT_3_OFFSET 0x008B0000 /* 3rd region */
#define EXYNOS4_SMMUG2D_ACP_OFFSET 0x00A40000 /* system mmu for 2D graphics engine */
#define EXYNOS4_SMMUSSS_OFFSET 0x00A50000 /* system mmu for SSS */
#define EXYNOS4_GPIO_RIGHT_OFFSET 0x01000000
#define EXYNOS4_GPIO_LEFT_OFFSET 0x01400000
#define EXYNOS4_FIMC0_OFFSET 0x01800000 /* image for display */
#define EXYNOS4_FIMC1_OFFSET 0x01810000
#define EXYNOS4_FIMC2_OFFSET 0x01820000
#define EXYNOS4_FIMC3_OFFSET 0x01830000
#define EXYNOS4_JPEG_OFFSET 0x01840000 /* JPEG Codec */
#define EXYNOS4_MIPI_CSI0_OFFSET 0x01880000 /* MIPI-Slim bus Interface */
#define EXYNOS4_MIPI_CSI1_OFFSET 0x01890000
#define EXYNOS4_SMMUFIMC0_OFFSET 0x01A20000 /* system mmus */
#define EXYNOS4_SMMUFIMC1_OFFSET 0x01A30000
#define EXYNOS4_SMMUFIMC2_OFFSET 0x01A40000
#define EXYNOS4_SMMUFIMC3_OFFSET 0x01A50000
#define EXYNOS4_SMMUJPEG_OFFSET 0x01A60000
#define EXYNOS4_FIMD0_OFFSET 0x01C00000 /* LCD0 */
#define EXYNOS4_MIPI_DSI0_OFFSET 0x01C80000 /* LCD0 */
#define EXYNOS4_SMMUFIMD0_OFFSET 0x01E20000 /* system mmus */
#define EXYNOS4_FIMC_ISP_OFFSET 0x02000000 /* (digital) camera video input */
#define EXYNOS4_FIMC_DRC_TOP_OFFSET 0x02010000
#define EXYNOS4_FIMC_FD_TOP_OFFSET 0x02040000
#define EXYNOS4_MPWM_ISP_OFFSET 0x02110000 /* (specialised?) PWM */
#define EXYNOS4_I2C0_ISP_OFFSET 0x02130000 /* I2C bus */
#define EXYNOS4_I2C1_ISP_OFFSET 0x02140000
#define EXYNOS4_MTCADC_ISP_OFFSET 0x02150000 /* (specialised?) AD Converter */
#define EXYNOS4_PWM_ISP_OFFSET 0x02160000 /* PWM */
#define EXYNOS4_WDT_ISP_OFFSET 0x02170000 /* Watch Dog Timer */
#define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* XXX micro controller control unit? */
#define EXYNOS4_UART_ISP_OFFSET 0x02190000 /* uart base clock */
#define EXYNOS4_SPI0_ISP_OFFSET 0x021A0000
#define EXYNOS4_SPI1_ISP_OFFSET 0x021B0000
#define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */
#define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */
#define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */
#define EXYNOS4_KEYIF_OFFSET 0x000A0000 /* Keypad interface */
#define EXYNOS4_HDMI_CEC_OFFSET 0x000B0000 /* HDMI Consumer Electronic Control */
#define EXYNOS4_TMU_OFFSET 0x000C0000 /* Thermal Managment */
#define EXYNOS4_SECKEY_OFFSET 0x00100000 /* XXX unknown XXX */
#define EXYNOS4_TZPC0_OFFSET 0x00110000 /* ARM Trusted Zone Protection Controller */
#define EXYNOS4_TZPC1_OFFSET 0x00120000
#define EXYNOS4_TZPC2_OFFSET 0x00130000
#define EXYNOS4_TZPC3_OFFSET 0x00140000
#define EXYNOS4_TZPC4_OFFSET 0x00150000
#define EXYNOS4_TZPC5_OFFSET 0x00160000
#define EXYNOS4_INTCOMBINER_OFFSET 0x00440000 /* combines first 32 interrupt sources */
#define EXYNOS4_GIC_CNTR_OFFSET 0x00480000 /* generic interrupt controller offset */
#define EXYNOS4_GIC_DISTRIBUTOR_OFFSET 0x00490000
#define EXYNOS4_AP_C2C_OFFSET 0x00540000 /* Chip 2 Chip XXX doc? XXX */
#define EXYNOS4_CP_C2C_MODEM_OFFSET 0x00580000
#define EXYNOS4_DMC0_OFFSET 0x00600000 /* Dynamic Memory Controller */
#define EXYNOS4_DMC1_OFFSET 0x00610000
#define EXYNOS4_PPMU_DMC_L_OFFSET 0x006A0000 /* event counters XXX ? */
#define EXYNOS4_PPMU_DMC_R_OFFSET 0x006B0000
#define EXYNOS4_PPMU_CPU_OFFSET 0x006C0000
#define EXYNOS4_GPIO_C2C_OFFSET 0x006E0000
#define EXYNOS4_TZASC_LR_OFFSET 0x00700000 /* trust zone access control */
#define EXYNOS4_TZASC_LW_OFFSET 0x00710000
#define EXYNOS4_TZASC_RR_OFFSET 0x00720000
#define EXYNOS4_TZASC_RW_OFFSET 0x00730000
#define EXYNOS4_G2D_ACP_OFFSET 0x00800000 /* 2D graphics engine */
#define EXYNOS4_SSS_OFFSET 0x00830000 /* Security Sub System */
#define EXYNOS4_CORESIGHT_1_OFFSET 0x00880000 /* 1st region */
#define EXYNOS4_CORESIGHT_2_OFFSET 0x00890000 /* 2nd region */
#define EXYNOS4_CORESIGHT_3_OFFSET 0x008B0000 /* 3rd region */
#define EXYNOS4_SMMUG2D_ACP_OFFSET 0x00A40000 /* system mmu for 2D graphics engine */
#define EXYNOS4_SMMUSSS_OFFSET 0x00A50000 /* system mmu for SSS */
#define EXYNOS4_GPIO_RIGHT_OFFSET 0x01000000
#define EXYNOS4_GPIO_LEFT_OFFSET 0x01400000
#define EXYNOS4_FIMC0_OFFSET 0x01800000 /* image for display */
#define EXYNOS4_FIMC1_OFFSET 0x01810000
#define EXYNOS4_FIMC2_OFFSET 0x01820000
#define EXYNOS4_FIMC3_OFFSET 0x01830000
#define EXYNOS4_JPEG_OFFSET 0x01840000 /* JPEG Codec */
#define EXYNOS4_MIPI_CSI0_OFFSET 0x01880000 /* MIPI-Slim bus Interface */
#define EXYNOS4_MIPI_CSI1_OFFSET 0x01890000
#define EXYNOS4_SMMUFIMC0_OFFSET 0x01A20000 /* system mmus */
#define EXYNOS4_SMMUFIMC1_OFFSET 0x01A30000
#define EXYNOS4_SMMUFIMC2_OFFSET 0x01A40000
#define EXYNOS4_SMMUFIMC3_OFFSET 0x01A50000
#define EXYNOS4_SMMUJPEG_OFFSET 0x01A60000
#define EXYNOS4_FIMD0_OFFSET 0x01C00000 /* LCD0 */
#define EXYNOS4_MIPI_DSI0_OFFSET 0x01C80000 /* LCD0 */
#define EXYNOS4_SMMUFIMD0_OFFSET 0x01E20000 /* system mmus */
#define EXYNOS4_FIMC_ISP_OFFSET 0x02000000 /* (digital) camera video input */
#define EXYNOS4_FIMC_DRC_TOP_OFFSET 0x02010000
#define EXYNOS4_FIMC_FD_TOP_OFFSET 0x02040000
#define EXYNOS4_MPWM_ISP_OFFSET 0x02110000 /* (specialised?) PWM */
#define EXYNOS4_I2C0_ISP_OFFSET 0x02130000 /* I2C bus */
#define EXYNOS4_I2C1_ISP_OFFSET 0x02140000
#define EXYNOS4_MTCADC_ISP_OFFSET 0x02150000 /* (specialised?) AD Converter */
#define EXYNOS4_PWM_ISP_OFFSET 0x02160000 /* PWM */
#define EXYNOS4_WDT_ISP_OFFSET 0x02170000 /* Watch Dog Timer */
#define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* XXX micro controller control unit? */
#define EXYNOS4_UART_ISP_OFFSET 0x02190000 /* uart base clock */
#define EXYNOS4_SPI0_ISP_OFFSET 0x021A0000
#define EXYNOS4_SPI1_ISP_OFFSET 0x021B0000
#define EXYNOS4_GIC_C_ISP_OFFSET 0x021E0000
#define EXYNOS4_GIC_D_ISP_OFFSET 0x021F0000
#define EXYNOS4_SYSMMU_FIMC_ISP_OFFSET 0x02260000
#define EXYNOS4_SYSMMU_FIMC_DRC_OFFSET 0x02270000
#define EXYNOS4_SYSMMU_FIMC_FD_OFFSET 0x022A0000
#define EXYNOS4_SYSMMU_ISPCPU_OFFSET 0x022B0000
#define EXYNOS4_FIMC_LITE0_OFFSET 0x02390000 /* external image input? */
#define EXYNOS4_FIMC_LITE1_OFFSET 0x023A0000
#define EXYNOS4_SYSMMU_FIMC_ISP_OFFSET 0x02260000
#define EXYNOS4_SYSMMU_FIMC_DRC_OFFSET 0x02270000
#define EXYNOS4_SYSMMU_FIMC_FD_OFFSET 0x022A0000
#define EXYNOS4_SYSMMU_ISPCPU_OFFSET 0x022B0000
#define EXYNOS4_FIMC_LITE0_OFFSET 0x02390000 /* external image input? */
#define EXYNOS4_FIMC_LITE1_OFFSET 0x023A0000
#define EXYNOS4_SYSMMU_FIMC_LITE0_OFFSET 0x023B0000
#define EXYNOS4_SYSMMU_FIMC_LITE1_OFFSET 0x023C0000
#define EXYNOS4_USBDEV0_OFFSET 0x02480000 /* XXX unknown XXX */
#define EXYNOS4_USBDEV0_1_OFFSET 0x02480000
#define EXYNOS4_USBDEV0_2_OFFSET 0x02490000
#define EXYNOS4_USBDEV0_3_OFFSET 0x024A0000
#define EXYNOS4_USBDEV0_4_OFFSET 0x024B0000
#define EXYNOS4_TSI_OFFSET 0x02500000 /* Transport Stream Interface */
#define EXYNOS4_SDMMC0_OFFSET 0x02510000 /* SD card interface */
#define EXYNOS4_SDMMC1_OFFSET 0x02520000
#define EXYNOS4_SDMMC2_OFFSET 0x02530000
#define EXYNOS4_SDMMC3_OFFSET 0x02540000
#define EXYNOS4_SDMMC4_OFFSET 0x02550000
#define EXYNOS4_MIPI_HSI_OFFSET 0x02560000 /* LCD0 */
#define EXYNOS4_SROMC_OFFSET 0x02570000
#define EXYNOS4_USBHOST0_OFFSET 0x02580000 /* USB EHCI */
#define EXYNOS4_USBHOST1_OFFSET 0x02590000 /* USB OHCI companion to EHCI (paired) */
#define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */
#define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */
#define EXYNOS4_PDMA1_OFFSET 0x02690000
#define EXYNOS4_GADC_OFFSET 0x026C0000 /* General AD Converter */
#define EXYNOS4_ROTATOR_OFFSET 0x02810000 /* Image rotator for video output */
#define EXYNOS4_SMDMA_OFFSET 0x02840000 /* (s) Memory DMA */
#define EXYNOS4_NSMDMA_OFFSET 0x02850000 /* (ns) Memory DMA */
#define EXYNOS4_SMMUROTATOR_OFFSET 0x02A30000 /* system mmu for rotator */
#define EXYNOS4_SMMUMDMA_OFFSET 0x02A40000
#define EXYNOS4_VP_OFFSET 0x02C00000 /* Video Processor */
#define EXYNOS4_MIXER_OFFSET 0x02C10000 /* Video mixer */
#define EXYNOS4_HDMI0_OFFSET 0x02D00000
#define EXYNOS4_HDMI1_OFFSET 0x02D10000
#define EXYNOS4_HDMI2_OFFSET 0x02D20000
#define EXYNOS4_HDMI3_OFFSET 0x02D30000
#define EXYNOS4_HDMI4_OFFSET 0x02D40000
#define EXYNOS4_HDMI5_OFFSET 0x02D50000
#define EXYNOS4_HDMI6_OFFSET 0x02D60000
#define EXYNOS4_SMMUTV_OFFSET 0x02E20000
#define EXYNOS4_G3D_OFFSET 0x03000000 /* 3D Graphics Accelerator */
#define EXYNOS4_PPMU_3D_OFFSET 0x03220000
#define EXYNOS4_MFC_OFFSET 0x03400000 /* Multi Format Codec */
#define EXYNOS4_SMMUMFC_L_OFFSET 0x03620000
#define EXYNOS4_SMMUMFC_R_OFFSET 0x03630000
#define EXYNOS4_PMMU_MFC_L_OFFSET 0x03660000 /* ? */
#define EXYNOS4_PMMU_MFC_R_OFFSET 0x03670000 /* ? */
#define EXYNOS4_UART0_OFFSET 0x03800000 /* serial port 0 */
#define EXYNOS4_UART1_OFFSET 0x03810000 /* serial port 1 */
#define EXYNOS4_UART2_OFFSET 0x03820000 /* serial port 2 */
#define EXYNOS4_UART3_OFFSET 0x03830000 /* serial port 3 */
#define EXYNOS4_UART4_OFFSET 0x03840000 /* serial port 4 */
#define EXYNOS4_GPIO_I2C0_OFFSET 0x03860000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C1_OFFSET 0x03870000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C2_OFFSET 0x03880000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C3_OFFSET 0x03890000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C4_OFFSET 0x038A0000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C5_OFFSET 0x038B0000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C6_OFFSET 0x038C0000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C7_OFFSET 0x038D0000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2CHDMI_OFFSET 0x038E0000 /* I2C for HDMI */
#define EXYNOS4_SPI0_OFFSET 0x03920000 /* Serial Peripheral Interface0 */
#define EXYNOS4_SPI1_OFFSET 0x03930000 /* Serial Peripheral Interface0 */
#define EXYNOS4_SPI2_OFFSET 0x03940000 /* Serial Peripheral Interface0 */
#define EXYNOS4_I2S1_OFFSET 0x03960000 /* sound */
#define EXYNOS4_I2S2_OFFSET 0x03970000 /* sound */
#define EXYNOS4_PCM1_OFFSET 0x03980000 /* sound */
#define EXYNOS4_PCM2_OFFSET 0x03990000 /* sound */
#define EXYNOS4_AC97_OFFSET 0x039A0000 /* AC97 audio codec sound */
#define EXYNOS4_SPDIF_OFFSET 0x039B0000 /* SPDIF sound */
#define EXYNOS4_PWMTIMER_OFFSET 0x039D0000
#define EXYNOS4_USBDEV0_OFFSET 0x02480000 /* XXX unknown XXX */
#define EXYNOS4_USBDEV0_1_OFFSET 0x02480000
#define EXYNOS4_USBDEV0_2_OFFSET 0x02490000
#define EXYNOS4_USBDEV0_3_OFFSET 0x024A0000
#define EXYNOS4_USBDEV0_4_OFFSET 0x024B0000
#define EXYNOS4_TSI_OFFSET 0x02500000 /* Transport Stream Interface */
#define EXYNOS4_SDMMC0_OFFSET 0x02510000 /* SD card interface */
#define EXYNOS4_SDMMC1_OFFSET 0x02520000
#define EXYNOS4_SDMMC2_OFFSET 0x02530000
#define EXYNOS4_SDMMC3_OFFSET 0x02540000
#define EXYNOS4_SDMMC4_OFFSET 0x02550000
#define EXYNOS4_MIPI_HSI_OFFSET 0x02560000 /* LCD0 */
#define EXYNOS4_SROMC_OFFSET 0x02570000
#define EXYNOS4_USBHOST0_OFFSET 0x02580000 /* USB EHCI */
#define EXYNOS4_USBHOST1_OFFSET 0x02590000 /* USB OHCI companion to EHCI (paired) */
#define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */
#define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */
#define EXYNOS4_PDMA1_OFFSET 0x02690000
#define EXYNOS4_GADC_OFFSET 0x026C0000 /* General AD Converter */
#define EXYNOS4_ROTATOR_OFFSET 0x02810000 /* Image rotator for video output */
#define EXYNOS4_SMDMA_OFFSET 0x02840000 /* (s) Memory DMA */
#define EXYNOS4_NSMDMA_OFFSET 0x02850000 /* (ns) Memory DMA */
#define EXYNOS4_SMMUROTATOR_OFFSET 0x02A30000 /* system mmu for rotator */
#define EXYNOS4_SMMUMDMA_OFFSET 0x02A40000
#define EXYNOS4_VP_OFFSET 0x02C00000 /* Video Processor */
#define EXYNOS4_MIXER_OFFSET 0x02C10000 /* Video mixer */
#define EXYNOS4_HDMI0_OFFSET 0x02D00000
#define EXYNOS4_HDMI1_OFFSET 0x02D10000
#define EXYNOS4_HDMI2_OFFSET 0x02D20000
#define EXYNOS4_HDMI3_OFFSET 0x02D30000
#define EXYNOS4_HDMI4_OFFSET 0x02D40000
#define EXYNOS4_HDMI5_OFFSET 0x02D50000
#define EXYNOS4_HDMI6_OFFSET 0x02D60000
#define EXYNOS4_SMMUTV_OFFSET 0x02E20000
#define EXYNOS4_G3D_OFFSET 0x03000000 /* 3D Graphics Accelerator */
#define EXYNOS4_PPMU_3D_OFFSET 0x03220000
#define EXYNOS4_MFC_OFFSET 0x03400000 /* Multi Format Codec */
#define EXYNOS4_SMMUMFC_L_OFFSET 0x03620000
#define EXYNOS4_SMMUMFC_R_OFFSET 0x03630000
#define EXYNOS4_PMMU_MFC_L_OFFSET 0x03660000 /* ? */
#define EXYNOS4_PMMU_MFC_R_OFFSET 0x03670000 /* ? */
#define EXYNOS4_UART0_OFFSET 0x03800000 /* serial port 0 */
#define EXYNOS4_UART1_OFFSET 0x03810000 /* serial port 1 */
#define EXYNOS4_UART2_OFFSET 0x03820000 /* serial port 2 */
#define EXYNOS4_UART3_OFFSET 0x03830000 /* serial port 3 */
#define EXYNOS4_UART4_OFFSET 0x03840000 /* serial port 4 */
#define EXYNOS4_I2C0_OFFSET 0x03860000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C1_OFFSET 0x03870000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C2_OFFSET 0x03880000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C3_OFFSET 0x03890000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C4_OFFSET 0x038A0000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C5_OFFSET 0x038B0000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C6_OFFSET 0x038C0000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2C7_OFFSET 0x038D0000 /* Inter Integrated Circuit (I2C) */
#define EXYNOS4_I2CHDMI_OFFSET 0x038E0000 /* I2C for HDMI */
#define EXYNOS4_SPI0_OFFSET 0x03920000 /* Serial Peripheral Interface0 */
#define EXYNOS4_SPI1_OFFSET 0x03930000 /* Serial Peripheral Interface0 */
#define EXYNOS4_SPI2_OFFSET 0x03940000 /* Serial Peripheral Interface0 */
#define EXYNOS4_I2S1_OFFSET 0x03960000 /* sound */
#define EXYNOS4_I2S2_OFFSET 0x03970000 /* sound */
#define EXYNOS4_PCM1_OFFSET 0x03980000 /* sound */
#define EXYNOS4_PCM2_OFFSET 0x03990000 /* sound */
#define EXYNOS4_AC97_OFFSET 0x039A0000 /* AC97 audio codec sound */
#define EXYNOS4_SPDIF_OFFSET 0x039B0000 /* SPDIF sound */
#define EXYNOS4_PWMTIMER_OFFSET 0x039D0000
/* AUDIOCORE */
#define EXYNOS4_AUDIOCORE_OFFSET 0x04060000 /* on 1Mb L1 chunk */
#define EXYNOS4_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS4_AUDIOCORE_OFFSET)
#define EXYNOS4_AUDIOCORE_PBASE 0x03860000 /* Audio SFR */
#define EXYNOS4_AUDIOCORE_SIZE 0x00001000
#define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00000000)
/* standard frequency settings */
#define EXYNOS4_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */
#define EXYNOS4_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */
#endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */

52
sys/arch/arm/samsung/exynos5_reg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD */
/* $NetBSD: exynos5_reg.h,v 1.3 2014/05/14 09:03:09 reinoud Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@ -51,12 +51,11 @@
* 0x20000000 0xFFFFFFFF DRAM
*/
#define EXYNOS5_CORE_PBASE 0x10000000 /* SFR */
/* CORE */
#define EXYNOS5_CORE_SIZE 0x10000000
#define EXYNOS5_SDRAM_PBASE 0x20000000
#define EXYNOS5_CMU_COREPART 0x00010000
#define EXYNOS5_CMU_COREPART_OFFSET 0x00010000
#define EXYNOS5_CMU_TOPPART_OFFSET 0x00020000
#define EXYNOS5_CMU_MEMPART_OFFSET 0x00030000
#define EXYNOS5_ALIVE_OFFSET 0x00040000
@ -194,22 +193,22 @@
#define EXYNOS5_USI_OFFSET 0x02D00000
#define EXYNOS5_TSADC_OFFSET 0x02D10000
#define EXYNOS5_SPI0_OFFSET 0x02D20000
#define EXYNOS5_SPI1_OFFSET 0x12D30000
#define EXYNOS5_SPI2_OFFSET 0x12D40000
#define EXYNOS5_USI2_OFFSET 0x12D50000
#define EXYNOS5_I2S1_OFFSET 0x12D60000
#define EXYNOS5_I2S2_OFFSET 0x12D70000
#define EXYNOS5_PCM1_OFFSET 0x12D80000
#define EXYNOS5_PCM2_OFFSET 0x12D90000
#define EXYNOS5_AC97_OFFSET 0x12DA0000
#define EXYNOS5_SPDIF_OFFSET 0x12DB0000
#define EXYNOS5_PWM_OFFSET 0x12DD0000
#define EXYNOS5_USI3_OFFSET 0x12DE0000
#define EXYNOS5_FIMC_ISP_OFFSET 0x13000000
#define EXYNOS5_FIMC_DRC_TOP_OFFSET 0x13010000
#define EXYNOS5_FIMC_SCALERC_OFFSET 0x13020000
#define EXYNOS5_FIMC_SCALERP_OFFSET 0x13030000
#define EXYNOS5_FIMC_FD_TOP_OFFSET 0x13040000
#define EXYNOS5_SPI1_OFFSET 0x02D30000
#define EXYNOS5_SPI2_OFFSET 0x02D40000
#define EXYNOS5_USI2_OFFSET 0x02D50000
#define EXYNOS5_I2S1_OFFSET 0x02D60000
#define EXYNOS5_I2S2_OFFSET 0x02D70000
#define EXYNOS5_PCM1_OFFSET 0x02D80000
#define EXYNOS5_PCM2_OFFSET 0x02D90000
#define EXYNOS5_AC97_OFFSET 0x02DA0000
#define EXYNOS5_SPDIF_OFFSET 0x02DB0000
#define EXYNOS5_PWM_OFFSET 0x02DD0000
#define EXYNOS5_USI3_OFFSET 0x02DE0000
#define EXYNOS5_FIMC_ISP_OFFSET 0x03000000
#define EXYNOS5_FIMC_DRC_TOP_OFFSET 0x03010000
#define EXYNOS5_FIMC_SCALERC_OFFSET 0x03020000
#define EXYNOS5_FIMC_SCALERP_OFFSET 0x03030000
#define EXYNOS5_FIMC_FD_TOP_OFFSET 0x03040000
#define EXYNOS5_FIMC_ODC_OFFSET 0x03050000
#define EXYNOS5_FIMC_DIS_OFFSET 0x03060000
#define EXYNOS5_FIMC_3DNR_OFFSET 0x03070000
@ -314,7 +313,7 @@
#define EXYNOS5_AES0&EF0 (ER) 0x081D0000
#define EXYNOS5_AES0&EF0 (ER) 0x081E0000
#define EXYNOS5_AES0&EF0 (ER) 0x081F0000
#define EXYNOS5_EFCON0_SFR_OFFSET 0x08200000
#define EXYNOS5_EFCON0_OFFSET 0x08200000
#define EXYNOS5_AES0 SFR_OFFSET 0x08300000
#define EXYNOS5_AES1&EF1 (NEW) 0x08400000
#define EXYNOS5_AES1&EF1 (NEW) 0x08410000
@ -349,9 +348,16 @@
#define EXYNOS5_AES1&EF1 (ER) 0x085E0000
#define EXYNOS5_AES1&EF1 (ER) 0x085F0000
#endif
#define EXYNOS5_EFCON1_SFR_OFFSET 0x08600000
#define EXYNOS5_EFCON1_OFFSET 0x08600000
#define EXYNOS5_NS_NDMA_OFFSET 0x08680000
#define EXYNOS5_S_NDMA_OFFSET 0x08690000
#define EXYNOS5_AES1 SFR_OFFSET 0x08700000
#define EXYNOS5_AES1_OFFSET 0x08700000
/* AUDIOCORE */
#define EXYNOS5_AUDIOCORE_OFFSET 0x10000000
#define EXYNOS5_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS5_AUDIOCORE_OFFSET)
#define EXYNOS5_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */
#define EXYNOS5_AUDIOCORE_SIZE 0x00070000
#endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */

54
sys/arch/arm/samsung/exynos_gpio.c
View File

@ -32,7 +32,7 @@
#include "gpio.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.3 2014/05/10 21:46:15 reinoud Exp $");
__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.4 2014/05/14 09:03:09 reinoud Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -76,11 +76,11 @@ struct exynos_gpio_pin_group {
};
#define GPIO_OFFSET(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o))
#define GPIO_REG(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o))
#define GPIO_GRP(v, s, o, n, b) \
{ \
.grp_name = #n, \
.grp_core_offset = GPIO_OFFSET(v,s,o), \
.grp_core_offset = GPIO_REG(v,s,o), \
.grp_bits = b,\
}
@ -181,7 +181,7 @@ static struct exynos_gpio_pin_group exynos4_pin_groups[] = {
GPIO_GRP(4, RIGHT, 0x0C60, GPX3, 8),
/* EXTINT skipped */
GPIO_GRP(4, I2C0, 0x0000, GPZ, 8),
GPIO_GRP(4, I2S0, 0x0000, GPZ, 8),
/* EXTINT skipped */
GPIO_GRP(4, C2C, 0x0000, GPV0, 8),
@ -249,6 +249,9 @@ exynos_gpio_config_pins(device_t self)
size_t pin_count = 0;
int i, bit, mask, pincaps, data;
if (exynos_n_pin_groups == 0)
return;
/* find out how many pins we can offer */
pin_count = 0;
for (i = 0; i < exynos_n_pin_groups; i++) {
@ -306,9 +309,6 @@ exynos_gpio_attach(device_t parent, device_t self, void *aux)
char scrap[16];
int i;
KASSERT(exynos_pin_groups);
KASSERT(exynos_n_pin_groups);
/* construct softc */
sc->sc_dev = self;
@ -316,6 +316,15 @@ exynos_gpio_attach(device_t parent, device_t self, void *aux)
sc->sc_bst = exyoaa->exyo_core_bst;
sc->sc_bsh = exyoaa->exyo_core_bsh;
exynos_gpio_bootstrap();
if (exynos_n_pin_groups == 0) {
printf(": disabled, no pins defined\n");
return;
}
KASSERT(exynos_pin_groups);
KASSERT(exynos_n_pin_groups);
aprint_naive("\n");
aprint_normal("\n");
@ -466,6 +475,8 @@ exynos_gpio_pinset_available(const struct exynos_gpio_pinset *req)
int i, n, inuse;
KASSERT(req);
if (exynos_n_pin_groups == 0)
return false;
/* we need a pinset group */
if (strlen(req->pinset_group) == 0)
@ -598,6 +609,9 @@ exynos_gpio_pin_reserve(const char *name, struct exynos_gpio_pindata *pd)
int func, pud, pinnr;
int pi, i;
if (exynos_n_pin_groups == 0)
return false;
/* do we have a named pin description? */
if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data))
return false;
@ -722,19 +736,9 @@ exynos_gpio_bootstrap(void)
}
#endif
#ifdef VERBOSE_INIT_ARM
printf("gpio");
#endif
if (exynos_n_pin_groups == 0) {
#ifdef VERBOSE_INIT_ARM
printf(" (disabled)\n");
#endif
if (exynos_n_pin_groups == 0)
return;
}
#ifdef VERBOSE_INIT_ARM
printf(" free");
#endif
/* init groups */
for (i = 0; i < exynos_n_pin_groups; i++) {
grp = &exynos_pin_groups[i];
@ -743,6 +747,8 @@ exynos_gpio_bootstrap(void)
bus_space_subregion(&exynos_bs_tag, exynos_core_bsh,
grp->grp_core_offset, EXYNOS_GPIO_GRP_SIZE,
&grp->grp_bsh);
KASSERT(&grp->grp_bsh);
grp->grp_pin_mask = __BIT(grp->grp_bits) - 1;
grp->grp_pin_inuse_mask = 0;
@ -772,21 +778,17 @@ exynos_gpio_bootstrap(void)
grp->grp_pin_inuse_mask |= mask;
}
}
#ifdef VERBOSE_INIT_ARM
printf(" P%s = %d", grp->grp_name,
popcount32(grp->grp_pin_mask & ~grp->grp_pin_inuse_mask));
#endif
}
#ifdef VERBOSE_INIT_ARM
printf("\n");
#if 0
printf("\n");
printf("default NC pin list generated: \n");
/* enable this for default NC pins list generation */
for (i = 0; i < exynos_n_pin_groups; i++) {
grp = &exynos_pin_groups[i];
printf("prop_dictionary_set_uint32(dict, \"nc-%s\", 0x%02x - 0x00);\n",
printf("prop_dictionary_set_uint32(dict, \"nc-%s\", "
"0x%02x - 0b00000000);\n",
grp->grp_name, grp->grp_pin_mask);
}
#endif
#endif
}

5
sys/arch/arm/samsung/exynos_io.c
View File

@ -34,7 +34,7 @@
#include "opt_exynos.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: exynos_io.c,v 1.5 2014/05/10 20:38:15 reinoud Exp $");
__KERNEL_RCSID(1, "$NetBSD: exynos_io.c,v 1.6 2014/05/14 09:03:09 reinoud Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -78,6 +78,7 @@ exyo_match(device_t parent, cfdata_t cf, void *aux)
return 1;
}
static int
exyo_print(void *aux, const char *pnp)
{
@ -89,11 +90,13 @@ exyo_print(void *aux, const char *pnp)
return QUIET;
}
void
exyo_device_register(device_t self, void *aux)
{
}
void
exyo_device_register_post_config(device_t self, void *aux)
{

43
sys/arch/arm/samsung/exynos_soc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: exynos_soc.c,v 1.10 2014/05/10 20:38:15 reinoud Exp $ */
/* $NetBSD: exynos_soc.c,v 1.11 2014/05/14 09:03:09 reinoud Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@ -33,7 +33,7 @@
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.10 2014/05/10 20:38:15 reinoud Exp $");
__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.11 2014/05/14 09:03:09 reinoud Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -61,6 +61,7 @@ __KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.10 2014/05/10 20:38:15 reinoud Exp
#include <evbarm/odroid/platform.h>
bus_space_handle_t exynos_core_bsh;
bus_space_handle_t exynos_audiocore_bsh;
/* these variables are retrieved in start.S and stored in .data */
uint32_t exynos_soc_id = 0;
@ -205,18 +206,28 @@ exynos_l2cc_init(void)
#endif /* ARM_TRUSTZONE_FIRMWARE */
#ifndef EXYNOS4
# define EXYNOS4_CORE_SIZE 0
#endif
#ifndef EXYNOS5
# define EXYNOS5_CORE_SIZE 0
#endif
void
exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
{
int error;
size_t core_size = IS_EXYNOS4_P() ?
EXYNOS4_CORE_SIZE : EXYNOS5_CORE_SIZE;
size_t core_size, audiocore_size;
size_t audiocore_pbase;
#ifdef EXYNOS4
if (IS_EXYNOS4_P()) {
core_size = EXYNOS4_CORE_SIZE;
audiocore_size = EXYNOS4_AUDIOCORE_SIZE;
audiocore_pbase = EXYNOS4_AUDIOCORE_PBASE;
}
#endif
#ifdef EXYNOS5
if (IS_EXYNOS5_P()) {
core_size = EXYNOS5_CORE_SIZE;
audiocore_size = EXYNOS5_AUDIOCORE_SIZE;
audiocore_pbase = EXYNOS5_AUDIOCORE_PBASE;
}
#endif
/* set up early console so we can use printf() and friends */
#ifdef EXYNOS_CONSOLE_EARLY
@ -228,15 +239,21 @@ exynos_bootstrap(vaddr_t iobase, vaddr_t uartbase)
error = bus_space_map(&exynos_bs_tag, EXYNOS_CORE_PBASE,
core_size, 0, &exynos_core_bsh);
if (error)
panic("%s: failed to map in Exynos io registers: %d",
panic("%s: failed to map in Exynos SFR registers: %d",
__func__, error);
KASSERT(exynos_core_bsh == iobase);
error = bus_space_map(&exynos_bs_tag, audiocore_pbase,
audiocore_size, 0, &exynos_audiocore_bsh);
if (error)
panic("%s: failed to map in Exynos audio SFR registers: %d",
__func__, error);
KASSERT(exynos_audiocore_bsh == EXYNOS4_AUDIOCORE_VBASE);
/* init bus dma tags */
exynos_dma_bootstrap(physmem * PAGE_SIZE);
/* init gpio structures */
exynos_gpio_bootstrap();
/* gpio bootstrapping delayed */
}

30
sys/arch/evbarm/odroid/odroid_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: odroid_machdep.c,v 1.15 2014/05/10 22:24:32 reinoud Exp $ */
/* $NetBSD: odroid_machdep.c,v 1.16 2014/05/14 09:03:09 reinoud Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.15 2014/05/10 22:24:32 reinoud Exp $");
__KERNEL_RCSID(0, "$NetBSD: odroid_machdep.c,v 1.16 2014/05/14 09:03:09 reinoud Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_exynos.h"
@ -226,6 +226,14 @@ static const struct pmap_devmap e4_devmap[] = {
.pd_prot = VM_PROT_READ | VM_PROT_WRITE,
.pd_cache = PTE_NOCACHE
},
{
/* map in audiocore IO space */
.pd_va = _A(EXYNOS4_AUDIOCORE_VBASE),
.pd_pa = _A(EXYNOS4_AUDIOCORE_PBASE),
.pd_size = _S(EXYNOS4_AUDIOCORE_SIZE),
.pd_prot = VM_PROT_READ | VM_PROT_WRITE,
.pd_cache = PTE_NOCACHE
},
{0}
};
@ -238,6 +246,14 @@ static const struct pmap_devmap e5_devmap[] = {
.pd_prot = VM_PROT_READ | VM_PROT_WRITE,
.pd_cache = PTE_NOCACHE
},
{
/* map in audiocore IO space */
.pd_va = _A(EXYNOS5_AUDIOCORE_VBASE),
.pd_pa = _A(EXYNOS5_AUDIOCORE_PBASE),
.pd_size = _S(EXYNOS5_AUDIOCORE_SIZE),
.pd_prot = VM_PROT_READ | VM_PROT_WRITE,
.pd_cache = PTE_NOCACHE
},
{0}
};
#undef _A
@ -577,6 +593,16 @@ odroid_device_register(device_t self, void *aux)
prop_dictionary_set_cstring(dict, "hub_nreset", ">GPX3[5]");
prop_dictionary_set_cstring(dict, "hub_connect", ">GPX3[4]");
prop_dictionary_set_cstring(dict, "hub_nint", "<GPX3[0]");
prop_dictionary_set_cstring(dict, "iic0_enable", "gpio");
prop_dictionary_set_cstring(dict, "iic1_enable", "gpio");
prop_dictionary_set_cstring(dict, "iic2_enable", "gpio");
/* IIC3 not used (NC) */
/* IIC4 not used (NC) */
/* IIC5 not used (NC) */
/* IIC6 used differently (SCLK used as led1) */
/* IIC7 used differently (PWM, though NC) */
/* IIC8 HDMI, not possible trough GPIO */
}
#endif
#ifdef EXYNOS5