- handle INTFLY (interrupt on the fly) command
- hanlde set/clear carry - handle shl, shr (shift left and rigth) and xor operators
This commit is contained in:
bouyer
parent
884898e332
commit
4b8e2f7002
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@ -1,4 +1,4 @@
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/* $NetBSD: ncr53cxxx.c,v 1.9 2002/04/20 20:56:25 bouyer Exp $ */
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/* $NetBSD: ncr53cxxx.c,v 1.10 2002/04/21 22:40:10 bouyer Exp $ */
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/*
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* Copyright (c) 1995,1999 Michael L. Hitch
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@ -61,6 +61,7 @@ void f_jump (void);
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void f_call (void);
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void f_return (void);
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void f_int (void);
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void f_intfly (void);
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void f_select (void);
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void f_reselect (void);
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void f_wait (void);
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@ -88,6 +89,7 @@ struct {
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{"CALL", f_call},
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{"RETURN", f_return},
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{"INT", f_int},
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{"INTFLY", f_intfly},
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{"SELECT", f_select},
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{"RESELECT", f_reselect},
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{"WAIT", f_wait},
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@ -412,7 +414,7 @@ main (int argc, char *argv[])
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if (outfp) {
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time_t cur_time;
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fprintf(outfp, "/*\t$NetBSD: ncr53cxxx.c,v 1.9 2002/04/20 20:56:25 bouyer Exp $\t*/\n");
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fprintf(outfp, "/*\t$NetBSD: ncr53cxxx.c,v 1.10 2002/04/21 22:40:10 bouyer Exp $\t*/\n");
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fprintf(outfp, "/*\n");
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fprintf(outfp, " *\tDO NOT EDIT - this file is automatically generated.\n");
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time(&cur_time);
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@ -997,6 +999,11 @@ void f_int (void)
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transfer (0x98000000, 2);
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}
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void f_intfly (void)
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{
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transfer (0x98100000, 2);
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}
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void f_select (void)
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{
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int t = tokenix;
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@ -1270,8 +1277,12 @@ void set_clear (u_int32_t code)
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inst0 |= 0x0200;
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++i;
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}
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else if (reserved ("carry", i)) {
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inst0 |= 0x0400;
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++i;
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}
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else
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errout ("Expected ATN, ACK, or TARGET");
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errout ("Expected ATN, ACK, TARGET or CARRY");
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need_and = 1;
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}
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store_inst ();
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@ -1323,8 +1334,14 @@ void register_write ()
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if (reserved ("to", tokenix+1))
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op = 0;
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else if (reserved ("shl", tokenix+1))
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op = 1;
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else if (reserved ("shr", tokenix+1))
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op = 5;
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else if (tokens[tokenix+1].type == '|')
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op = 2;
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else if (reserved ("xor", tokenix+1))
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op = 3;
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else if (tokens[tokenix+1].type == '&')
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op = 4;
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else if (tokens[tokenix+1].type == '+')
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@ -1333,8 +1350,16 @@ void register_write ()
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op = 8;
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else
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errout ("Unknown register operator");
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if (op && reserved ("to", tokenix+3) == 0)
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errout ("Register command expected TO");
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switch (op) {
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case 2:
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case 3:
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case 4:
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case 6:
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case 8:
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if (reserved ("to", tokenix+3) == 0)
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errout ("Register command expected TO");
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default:
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}
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reg = CheckRegister (tokenix);
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if (reg < 0) { /* Not register, must be data */
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data = evaluate (tokenix);
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@ -1347,24 +1372,45 @@ void register_write ()
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#if 0
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fprintf (listfp, "Move data to register: %02x %d\n", data, reg);
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#endif
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}
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else if (op) { /* A register read/write operator */
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data = evaluate (tokenix+2);
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if (tokenix+5 < ntokens) {
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if (!reserved("with", tokenix+5) ||
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!reserved("carry", tokenix+6)) {
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errout("Expected 'WITH CARRY'");
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} else if (op != 6) {
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errout("'WITH CARRY' only valide with '+'");
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} else if (op) {
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switch (op) {
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case 2:
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case 3:
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case 4:
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case 6:
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case 8:
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inst0 = 0;
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/* A register read/write operator */
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if (reserved("sfbr", tokenix+2)) {
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if (arch < ARCH825)
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errout("wrong arch for add with SFBR");
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if (op == 8)
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errout("can't substract SFBR");
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inst0 |= 0x00800000;
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data = 0;
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} else
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data = evaluate (tokenix+2);
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if (tokenix+5 < ntokens) {
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if (!reserved("with", tokenix+5) ||
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!reserved("carry", tokenix+6)) {
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errout("Expected 'WITH CARRY'");
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} else if (op != 6) {
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errout("'WITH CARRY' only valide "
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"with '+'");
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}
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op = 7;
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}
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op = 7;
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if (op == 8) {
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data = -data;
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op = 6;
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}
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inst0 |= (data & 0xff) << 8;
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data = CheckRegister (tokenix+4);
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break;
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default:
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data = CheckRegister (tokenix+2);
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break;
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}
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if (op == 8) {
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data = -data;
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op = 6;
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}
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inst0 = (data & 0xff) << 8;
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data = CheckRegister (tokenix+4);
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if (data < 0)
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errout ("Expected register");
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if (reg != data && reg != 8 && data != 8)
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@ -1389,8 +1435,7 @@ fprintf (listfp, "Move register to SFBR: %02x %d %d\n", inst0 >> 8, op, reg);
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inst0 |= 0x70000000 | (op << 24) | (reg << 16);
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}
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}
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}
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else { /* register to register */
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} else { /* register to register */
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data = CheckRegister (tokenix+2);
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if (data < 0)
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errout ("Expected register");
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